Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 2003
(All Rights Reserved)
Cirrus Logic, Inc.
http://www.cirrus.com
CS5381
120 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-Bit Conversion
120 dB Dynamic Range
-110 dB THD+N
Supports all Audio Sample Rates Including
192 kHz
Less than 32 5mW Power Consumption
High Pass Filter or DC Offset Calibration
Supports Logic Levels Between 5 and 2.5V
Differential Analog Architecture
Low Latency Digital Filtering
Overflow Detection
Pin compatible with the CS5361
General Description
The CS5381 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form at
sample rates up to 200 kHz per channel.
The CS5381 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
The CS5381 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
A/V receivers, DVD-R, CD-R, digital mixing consoles,
and effects processors.
ORDERING INFORMATION
CS5381-KS -10° to 70° C 24-pin SOIC
CS5381-KZ -10° to 70° C 24-pin TSSOP
CDB5381 Evaluation Board
Voltage Reference Serial Output Interface
Digital
Filter
High
Pass
Filter
High
Pass
Filter
Decimation
Digital
Filter
Decimation
DAC
-
+
S/H
DAC
-
+
S/H
AINR+
SCLK SDOUT MCLK
RST
VQ LRCK
AINR-
AINL+
AINL-
FILT+ I
2
S/LJ
M/S
HPF
MODE0
MODE1
REFGND V
L
MDIV
LP Filter
LP Filter
∆Σ
∆Σ
OVFL
GND
VA
5.0 V GND VD
3.3V - 5.0V
2.5 V - 5.0 V
OCT ‘03
DS563A2
CS5381
2
TABLE OF CONTENTS
1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SPECIFIED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ANALOG CHARACTERISTICS (CS5381-KS/KZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 TYPICAL CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 Operational Mode/Sample Rate Range Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.5 High Pass Filter and DC Offset Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Overflow Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6.1 OVFL Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Grounding and Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Synchronization of Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 PACKAGE DIMENSIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 PARAMETER DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
“Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus")
believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided
"AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of s ale supplied at the time of order
acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this
information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This
document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights,
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for
copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does
not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies describ ed in this ma-
terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
ERS RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMERS CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS , EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade-
marks or service marks of their respective owners.
CS5381
3
LIST OF FIGURES
Figure 1. Master Mode, Left Justified SAI .......................................................................................9
Figure 2. Slave Mode, Left Justified SAI ......................................................................................... 9
Figure 3. Master Mode, I2S SAI ...................................................................................................... 9
Figure 4. Slave Mode, I2S SAI ........................................................................................................ 9
Figure 5. OVFL Output Timing ........................................................................................................ 9
Figure 6. Left Justified Serial Audio Interface ............................................................................... 10
Figure 7. I2S Serial Audio Interface............................................................................................... 10
Figure 8. OVFL Output Timing, I2S Format................................................................................... 10
Figure 9. OVFL Output Timing, Left-Justified Format ................................................................... 10
Figure 10. Typical Connection Diagram........................................................................................ 12
Figure 11. CS5381 Master Mode Clocking ................................................................................... 13
Figure 12. Recommended Analog Input Buffer............................................................................. 15
Figure 13. Single Speed Mode Stopband Rejection ..................................................................... 20
Figure 14. Single Speed Mode Transition Band ........................................................................... 20
Figure 15. Single Speed Mode Transition Band (Detail)............................................................... 20
Figure 16. Single Speed Mode Passband Ripple ......................................................................... 20
Figure 17. Double Speed Mode Stopband Rejection.................................................................... 20
Figure 18. Double Speed Mode Transition Band.......................................................................... 20
Figure 19. Double Speed Mode Transition Band (Detail) ............................................................. 21
Figure 20. Double Speed Mode Passband Ripple ........................................................................ 21
Figure 21. Quad Speed Mode Stopband Rejection ...................................................................... 21
Figure 22. Quad Speed Mode Transition Band............................................................................. 21
Figure 23. Quad Speed Mode Transition Band (Detail)................................................................ 21
Figure 24. Quad Speed Mode Passband Ripple........................................................................... 21
LIST OF TABLES
Table 1. Revision History ................................................................................................................ 3
Table 2. CS5381 Mode Control..................................................................................................... 13
Table 3. CS5381 Common Master Clock Frequencies................................................................. 14
Table 4. CS5381 Slave Mode Clock Ratios .................................................................................. 14
Table 1. Revision History
Release Date Changes
A1 December, 2002 Advanced Release
A2 October, 2003 Changed front page description of digital filter (pag e1)
Improved distortion specification from -105dB to -110dB (page6)
Modified serial port timing specifications for slave mode operation (page8)
Added pull-down resistors to recommended input buffer ( page15)
CS5381
4
1 PIN DESCRIPTIONS
Power Supply and Ground
Pin Name #Pin Description
RST 1Reset (
Input
) - The device enters a low power mode when low.
M/S 2Master/Slave Mode
(Input)
- Selects operation as either clock master or slave.
LRCK 3Left Right Clock (
Input
/
Output
) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK 4Serial Clock (
Input
/
Output
) - Serial clock for the serial audio interface.
MCLK 5Master Clock (
Input
) - Clock source for the delta-sigma modulator and digital filters.
VD 6Digital Power (
Input
) - Positive power supply for the digital section.
GND 7,18 Ground (
Input
) - Ground reference. Must be connected to analog ground.
VL 8Logic Power (
Input
) - Positive power for the digital input/output.
SDOUT 9Serial Audio Data Output (
Output
) - Output for two’s complement serial audio data.
MDIV 10 MCLK Divider
(Input
) - Enables a master clock divide by two function.
HPF 11 High Pass Filter Enable
(Input
) - Enables the Digital High-Pass Filter.
I2S/LJ 12 Serial Audio Interface Format Select (
Input
) -Selects either the left-justified or I2S format for the SAI.
M0
M1
13,
14
Mode Selection (
Input
) - Determines the operational mode of the device.
OVFL 15 Overflow
(Output, open drain)
- Detects an overflow condition on both left and right channels.
AINL+
AINL-
16,
17
Differential Left Channel Analog Input (
Input
) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VA 19 Analog Power (
Input
) - Positive power supply for the analog section.
AINR+
AINR-
20,
21
Differential Right Channel Analog Input (
Input
) -Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
VQ 22 Quiescent Voltage
(Output)
- Filter connection for the internal quiescent reference voltage.
REF_GND 23 Reference Ground (
Input
) - Ground reference for the internal sampling circuits.
FILT+ 24 Positive Voltage Reference (
Output
) - Positive reference voltage for the internal sampling circuits.
RST 124FILT+
M/S 223REFGND
LRCK 322VQ
SCLK 421AINR+
MCLK 520AINR-
VD 619VA
GND 718GND
VL 817AINL-
SDOUT 916AINL+
MDIV 10 15 OVFL
HPF 11 14 M1
I2S/LJ 12 13 M0
CS5381
5
2 CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at VA = 5. 0V, VD = VL = 3. 3V,
and TA = 25°C.
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to 0 V.)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 3)
Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SRC
latch-up.
2. The maximum over/under voltage is limited by the input current.
3. Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
Parameters Symbol Min Typ Max Units
DC Power Supply
DC Power Supplies: Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
4.75
3.1
2.37
5.0
-
-
5.25
5.25
5.25
V
V
V
Ambient Operating Temperature (Power Applied) TA-10 - +70 °C
Parameter Symbol Min Typ Max Units
DC Power Supplies: Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
-
-
-
+6.0
+6.0
+6.0
V
V
V
Input Current (Note 1) Iin --±10 mA
Analog Input Voltage (Note 2) VIN GND-0.7 - VA+0.7 V
Digital Input Voltage (Note 2) VIND -0.7 - VL+0.7 V
Ambient Operating Temperature (Power Applied) TA-50 - +95 °C
Storage Temperature Tstg -65 - +150 °C
CS5381
6
ANALOG CHARACTERISTICS (CS5381-KS/KZ) (Test conditions (unless otherwise speci-
fied): Input test signal is a 1kHz sine wave; measurement bandwidth is 10Hz t o 20kHz.)
Notes: 4. Referred to the typical full-scale input voltage.
5. Measured between AIN+ and AIN-
Parameter Symbol Min Typ Max Unit
Single Speed Mode Fs = 48kHz
Dynamic Range A-weighted
unweighted
114
111
120
117
-
-
dB
dB
Total Harmonic Distortion + Noise (Note 4)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-110
-97
-57
-104
-
-
dB
dB
dB
Double Speed Mode Fs = 96kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
114
111
-
120
117
114
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1dB
THD+N
-
-
-
-
-110
-97
-57
-107
-104
-
-
-
dB
dB
dB
dB
Quad Speed Mode Fs = 192kHz
Dynamic Range A-weighted
unweighted
40 kHz bandwidth unweighted
114
111
-
120
117
114
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Note 4)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth -1dB
THD+N
-
-
-
-
-110
-97
-57
-107
-104
-
-
-
dB
dB
dB
dB
Dynamic Performance for All Modes
Interchannel Isolation - 110 - dB
Interchannel Phase Deviation - 0.0001 - Degree
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Gain Error -±5%
Gain Drift - ±100 - ppm/°C
Offset Error HPF enabled
HPF disabled
-
-
0
100
-
-
LSB
LSB
Analog Input Characteristics
Full-scale Input Voltage 1.9 2.0 2.1 Vrms
Input Impedance (Differential) (Note 5) 37 - - kΩ
Common Mode Rejection Ratio CMRR - 100 - dB
CS5381
7
DIGITAL FILTER CHARACTERISTICS (Note 6)
Notes: 6. Amplitude vs. Frequency response plots of this data are available in “Appendix” on page20.
7. The filter frequency response scales precisely with Fs.
8. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
Parameter Symbol Min Typ Max Unit
Single Speed Mode (2 kHz to 50 kHz sample rates)
Passband (-0.1 dB) (Note 7) 0 - 0.47 Fs
Passband Ripple - - ±0.035 dB
Stopband (Note 7) 0.58 - - Fs
Stopband Attenuation -95 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs - s
Double Speed Mode (50 kHz to 100 kHz sample rates)
Passband (-0.1 dB) (Note 7) 0 - 0.45 Fs
Passband Ripple - - ±0.035 dB
Stopband (Note 7) 0.68 - - Fs
Stopband Attenuation -92 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs - s
Quad Speed Mode (100 kHz to 200 kHz sample rates)
Passband (-0.1 dB) (Note 7) 0 - 0.24 Fs
Passband Ripple - - ±0.035 dB
Stopband (Note 7) 0.78 - - Fs
Stopband Attenuation -97 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs - s
High Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 8)
-1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 8) - 10 - Deg
Passband Ripple - - 0 dB
Filter Setting Time 105/Fs s
CS5381
8
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL, CL = 20 pF)
Parameter Symbol Min Typ Max Unit
Output Sample Rate Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
50
100
200
kHz
kHz
kHz
OVFL to LRCK edge setup time tsetup 16/fsclk --s
OVFL to LRCK edge hold time thold 1/fsclk --s
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period tclkw 40 - 1953 ns
MCLK Duty Cycle tclkhl 40 - 60 %
Master Mode
SCLK falling to LRCK tmslr -20 - 20 ns
SCLK falling to SDOUT valid tsdo 0 - 32 ns
SCLK Duty Cycle - 50 - %
Slave Mode
Single Speed
Output Sample Rate Fs 2 - 50 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 163 - - ns
SCLK Low tsclkhl 55 - - ns
SCLK falling to SDOUT valid tdss - - 32 ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Double Speed
Output Sample Rate Fs 50 - 100 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 163 - - ns
SCLK Low tsclkhl 55 - - ns
SCLK falling to SDOUT valid tdss - - 32 ns
SCLK falling to LRCK edge tslrd -20 - 20 ns
Quad Speed
Output Sample Rate Fs 100 - 200 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period tsclkw 81 - - ns
SCLK Low tsclkhl 40 - - ns
SCLK falling to SDOUT valid tdss - - 32 ns
SCLK falling to LRCK edge tslrd -8 - 8 ns
CS5381
9
SCLK output
tmslr
SDOUT
tsdo
LRCK output
MSB MSB-1
SCLK input
LRCK input
sclkl
t
dss
t
MSB MSB-1 MSB-2
lrdss
t
sclkh
t
tsclkw
SDOUT
srdl
t
Figure 1. Master Mode, Left Justified SAI Figure 2. Slave Mode, Left Justified SAI
SCLK output
tmslr
tsdo
LRCK output
MSB
SDOUT
SCLK input
LRCK input
sclkl
t
dss
t
MSB MSB-1
sclkh
t
tsclkw
SDOUT
Figure 3. Master Mode, I2S SAI Figure 4. Slave Mode, I2S SAI
OVFL
tsetup
LRCK
thold
Figure 5. OVFL Output Timing
CS5381
10
SDATA 23 22 7 623 22
SCLK
LRCK
23 2254321087654321089 9
Left Channel Right Channel
Figure 6. Left Justified Serial Audio Interface
SDATA 23 22 8 723 22
SCLK
LRCK
23 2265432108765432109 9
Left Channel Right Channel
Figure 7. I2S Serial Audio Interface
LRCK
OVFL
SCLK
OVFL_R OVFL_L OVFL_R
Figure 8. OVFL Output Timing, I2S Format
LRCK
OVFL
SCLK
OVFL_R OVFL_L OVFL_R
Figure 9. OVFL Output Timing, Left-Justified Format
CS5381
11
DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to ground.
MCLK=12.288 MHz; Master Mode)
Notes: 9. Power-Down Mode is defined as RST = Low with all clocks and data lines held static.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Power Supply Current VA
(Normal Operation) VL,VD = 5 V
VL,VD = 3.3 V
IA
ID
ID
-
-
-
50
30
20
55
33
22
mA
mA
mA
Power Supply Current VA
(Power-Down Mode) (Note 9) VL,VD=5 V
IA
ID
-
-
100
100
-
-
uA
uA
Power Consumption
(Normal Operation) VL, VD =5V
VL, VD = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
400
316
1
440
348
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 10) PSRR - 65 - dB
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
2.5
25
0.01
-
-
-
V
kΩ
mA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
5
35
0.01
-
-
-
V
kΩ
mA
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VL) VIH 70% - - V
Low-Level Input Voltage (% of VL) VIL --30%V
High-Level Output Voltage at Io = 100 µA (% of VL) VOH 70% - - V
Low-Level Output Voltage at Io = 100 µA (% of VL) VOL --15%V
Input Leakage Current Iin --±10 µA
CS5381
12
3 TYPICAL CONNECTION DIAGRAM
FILT+
AINL+
AINL-
V
D
0.01 µ
F
A/D CONVERTER
SCLK
CS5381
M/S
MCLK
AINR+
AINR-
VQ
47 µ
F+
RST
VA V L
+5V
1µ
F
+5Vto 2.5 V
5.1 Ω
1µ
F
+
+ +
SDOUT
GND
I2S/LJ
LRCK
GND
Power Down
and Mode
Settings
Audio Data
Processor
Timing Logic
and Clock
0.01 µ
F
0.01 µ
F0.01
µF
HPF
M0
M1
REFGND
MDIV
+5 V to 3.3 V
1µF0.01 µF
1µ
F
+
Analog
Input
Buffer
(Figure 3)
Analog
Input
Buffer
(Figure 3)
OVFL
10 k
VL
*
* Resistor may only be
used if VD is derived
from VA. If used, do
not drive any other
logic from VD.
0.01 µF
Figure 10. Typical Connection Diagram
CS5381
13
4 APPLICATIONS
4.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2kHz to 200kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 2.
4.2 System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchro-
nously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial
clocks. The device also includes a master clock divider in Master Mode where the master clock will be
internally divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode,
the MDIV pin needs to be disabled, set to logic 0.
4.2.1 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 11. Refer to Table 3 for common master clock frequencies.
M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)
0 0 Single Speed Mode 2 kHz - 50 kHz
0 1 Double Speed Mode 50 kHz - 100 kHz
1 0 Quad Speed Mode 100 kHz - 200 kHz
11Reserved
Table 2. CS5381 Mode Control
÷ 128
÷ 256
÷ 64
M0M1
LRCK Output
(Equal to Fs)
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 4
÷ 1
SCLK Output
Single
Speed
Quad
Speed
Double
Speed
00
01
10
÷ 2
÷ 1 0
1
MCLK
MDIV
Figure 11. CS5381 Master Mode Clocking
CS5381
14
4.2.2 Slave Mode
LRCK and SCLK operate as inputs in Slave mode. It is recommended that the left/right clock be synchro-
nously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance.
Refer to Table 4 for required clock ratios.
* Only available in Master mode.
Table 4. CS5381 Slave Mode Clock Ratios
4.3 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-
lay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance.
4.4 Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-
band of the filter. However, there is no rejection for input signals which are (n ×6.144 MHz) the digital
passband frequency, where n=0,1,2, ... refer to Figure 12 which shows the suggested filter that will atten-
uate any noise energy at 6. 144MHz, in addition to providing the optimum source impedance for the mod-
ulators. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics)
must be avoided since these can degrade signal linearity.
Single Speed Mode
Fs = 2 kHz to 50 kHz
Double Speed Mode
Fs = 50 kHz to 100 kHz
Quad Speed Mode
Fs = 100 kHz to 200 kHz
MCLK/LRCK Ratio 256x, 512x 128x, 256x 64x*, 128x
SCLK/LRCK Ratio 64x, 128x 64x 64x
SAMPLE RATE (kHz)
MDIV = 0
MCLK (MHz)
MDIV = 1
MCLK (MHz)
32 8.192 16.384
44.1 11.2896 22.5792
48 12.288 24.576
64 8.192 16.384
88.2 11.2896 22.5792
96 12.288 24.576
176.4 11.2896 22.5792
192 12.288 24.576
Table 3. CS5381 Common Master Clock Frequencies
CS5381
15
4.5 High Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into
the A/D converter. The CS5381 includes a high pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding "clicks" when switching between devices in
a multichannel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is
frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it
possible to perform a system DC offset calibration by:
1) Running the CS5381 with the high pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5381.
VQ
10
kΩ
10
kΩ
+
634 Ω
634 Ω
91 Ω
91 Ω
+
-
-
2700 pF
470 pF
470 pF
COG
COG
10 uF
10 uF
ADC AIN+
ADC AIN-
AIN+
AIN-
COG
100
kΩ
100
kΩ
Figure 12. Recommended Analog Input Buffer
CS5381
16
4.6 Overflow Detection
The CS5381 includes overflow detection on both the left and right channels. This time multiplexed infor-
mation is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go
to a logical low as soon as an overrange condition in either channel is detected. The data will remain low
as specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to
detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R
data will return to a logical high if there has not been any other overrange condition detected. Please note
that an overrange condition on either channel will restart the timeout period for both channels.
4.6.1 OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I2S format,
the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 8 and 9. In both
cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified for-
mat, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK
would latch the left channel overflow status. In I2S format, the falling edge of LRCK would latch the right
channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
4.7 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5381 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 10 shows the recommended power
arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be
run from the system logic supply or may be powered from the analog supply via a resistor. In this case, no
additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as
possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The
FILT+ and VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the elec-
trical path from FILT+ and REFGND. The CDB5381 evaluation board demonstrates the optimum layout
and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to
CMOS inputs.
4.8 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5381’s in the sys-
tem. If only one master clock source is needed, one solution is to place one CS5381 in Master mode, and
slave all of the other CS5381’s to the one master. If multiple master clock sources are needed, a possible
solution would be to supply all clocks from the same external source and time the CS5381 reset with the
inactive edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.
CS5381
17
5 PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.598 0.614 15.20 15.60
E 0.291 0.299 7.40 7.60
e 0.040 0.060 1.02 1.52
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
∝0° 8° 0° 8°
24L SOIC (300 MIL BODY) PACKAGE DRAWING
D
HE
b
A1
A
c
L
∝
SEATING
PLANE
1
e
CS5381
18
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.0 7mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 a nd 0.25mm from lead tips.
6 THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A -- -- 0.043 -- -- 1.10
A1 0.002 0.004 0.006 0.05 -- 0.15
A2 0.03346 0.0354 0.037 0.85 0.90 0.95
b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3
D 0.303 0.307 0.311 7.70 7.80 7.90 1
E 0.248 0.2519 0.256 6.30 6.40 6.50
E1 0.169 0.1732 0.177 4.30 4.40 4.50 1
e -- 0.026 BSC -- -- 0.65 BSC --
L 0.020 0.024 0.028 0.50 0.60 0.70
∝0° 4° 8° 0° 4° 8°
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Unit
Allowable Junction Temperature - - 135 °C
Junction to Ambient Thermal Impedance θJA -70 -°C/W
24L TSSOP (4. 4mm BODY) PACKAGE DRAWING
E
N
123
eb2A1
A2 A
D
SEATING
PLANE
E11
L
SIDE VIEW
END VIEW
TOP VIEW
∝
CS5381
19
7 PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60dBFS signal. 60dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 1 0Hz to 2 0kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
CS5381
20
8 APPENDIX
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (n ormalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0. 50 0. 52 0. 54 0. 56 0.58 0. 60
Frequency (norm alized to Fs)
Amplitude (dB)
Figure 13. Single Speed Mode Stopband Rejection Figure 14. Single Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalize d to Fs)
Amplitude (dB)
Figure 15. Single Speed M ode Transition Band (Detail)
Figure 16. Single Speed Mode Passband Ripple
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0. 6 0. 7 0. 8 0. 9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.43 0.45 0.48 0.50 0.53 0. 55 0. 58 0. 60 0. 63 0.65 0. 68 0. 70
Frequency (normalized t o Fs)
Amplitude (dB)
Figure 17. Double Speed Mode Stopband Rejection Figure 18. Double Speed Mode Transition Band
CS5381
21
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.40 0.43 0.45 0.48 0.50 0.53 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.05
-0.03
0.00
0.03
0.05
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0. 25 0. 30 0. 35 0. 40 0.45 0. 50
Frequency (normalized to Fs)
Amplitude (dB)
Figure 19. Double Speed Mode Transition Band (Detail) Figure 20. Double Speed Mode Passband Ripple
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8
Frequency (n ormalized to Fs)
Amplitude (dB)
Figure 21. Quad Speed Mode Stopband Rejection Figure 22. Quad Speed Mode Transition Band
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.1 0.15 0.2 0. 25 0. 3 0. 35 0. 4 0. 45 0.5 0.55 0.6
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25
Frequency (normalized to Fs )
Amplitude (dB)
Figure 23. Quad Speed Mode Transition Band (Detail) Figure 24. Quad Speed Mode Passband Ripple
