Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features 1/2.5-Inch 5Mp CMOS Digital Image Sensor MT9P401 Data Sheet For the latest data sheet, refer to Aptina's Web site: www.aptina.com Features Table 2: * * * * Optical format Active imager size * * * * * * * * * * Digital still cameras Digital video cameras PC cameras Converged DSCs/camcorders Cellular phones PDAs The 5Mp CMOS image sensor features Aptina's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. Ordering Information Table 1: Available Part Numbers Part Number Description MT9P401I12STC 48-pin iLCC PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Value 1/2.5-inch (4:3) 5.70mm(H) x 4.28mm(V) 7.13mm diagonal Active pixels 2592H x 1944V Pixel size 2.2 x 2.2m Color filter array RGB Bayer pattern Global reset release (GRR), Snapshot Shutter type only Electronic rolling shutter (ERS) Maximum data rate/ 96 Mp/s at 96 MHz (2.8V I/O) master clock 48 Mp/s at 48 MHz (1.8V I/O) Full resolution Programmable up to 15 fps Frame HDTV (1280 x 720) Programmable up to 60 fps (with binning) rate ADC resolution 12-bit, on-chip Responsivity 1.4 V/lux-sec (550nm) Pixel dynamic range 70.1dB SNRMAX 38.1dB Supply I/O 1.7-3.1V Voltage Digital 1.7-1.9V (1.8V nominal) Analog 2.6-3.1V (2.8V nominal) Power consumption 381mW at 15 fps full resolution Operating temperature -30C to +70C Packaging 48-pin iLCC, die Applications * * * * * * Key Performance Parameters Parameter High frame rate Superior low-light performance Low dark current Global reset release, which starts the exposure of all rows simultaneously Bulb exposure mode, for arbitrary exposure times Snapshot mode to take frames on demand Horizontal and vertical mirror image Column and row skip modes to reduce image size without reducing field-of-view (FOV) Column and row binning modes to improve image quality when resizing Simple two-wire serial interface Programmable controls: gain, frame rate, frame size, exposure Automatic black level calibration On-chip phase-locked loop (PLL) 720p HDTV video at 60 fps General Description The Aptina(R) MT9P401 is a 1/2.5-inch CMOS activepixel digital image sensor with an active imaging pixel array of 2592H x 1944V. It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface. 1 (c)2007 Aptina Imaging Corporation All rights reserved. Products and specifications discussed herein are subject to change by Aptina without notice. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pixel Array Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Default Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Output Data Format (Default Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 LV and FV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Frame Rates at Common Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Two-Wire Serial Interface Sample Write and Read Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 16-Bit WRITE Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 16-Bit READ Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Power Up and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PLL-Generated Master Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PLL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Standby and Chip Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Full-Array Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Window Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Skipping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Binning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Column Mirror Image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Row Mirror Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Maintaining a Constant Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 1 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Table of Contents Synchronizing Register Writes to Frame Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Image Acquisition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Electronic Rolling Shutter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Global Reset Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Strobe Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Signal Chain and Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Analog Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Digital Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Analog Black Level Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Digital Black Level Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Classic Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Color Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Vertical Color Bars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Horizontal Gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Vertical Gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Diagonal Gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Walking 1s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Monochrome Vertical Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Monochrome Horizontal Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 2 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Timing Diagram Showing a WRITE to Reg0x09 with the Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . .19 Timing Diagram Showing a READ from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . .19 PLL-Generated Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Eight Pixels in Normal and Column Skip 2X Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Pixel Readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Pixel Readout (Column Skip 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Pixel Readout (Row Skip 2X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Pixel Readout (Column Skip 2X, Row Skip 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Pixel Readout (Column Bin 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Pixel Readout (Column Bin 2X, Row Bin 2X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 ERS Snapshot Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 GRR Snapshot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Typical Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 CRA vs. Image Height (7 deg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 CRA vs. Image Height (22 deg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 48-Pin iLCC Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 1 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Type by Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pixel Type by Row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Dark Rows Sampled as a Function of Row_Bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Dark Columns Sampled as a Function of Column_Bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 HBmin Values for Row_bin vs. Column_bin Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Standard Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Wide Screen (16:9) Resolutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Register List and Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Legal Values for Column_Skip Based on Column_Bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 STROBE Timepoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Gain Increment Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 I/O Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 1 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor General Description General Description The MT9P401 sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a full resolution image at 15 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 12 bits per pixel. FRAME_VALID (FV) and LINE_VALID (LV) signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. The MT9P401produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous HDTV video and single frames makes it the perfect choice for a wide range of consumer and digital video cameras. Functional Overview The MT9P401 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 6 and 27 MHz. The maximum pixel rate is 96 Mp/s, corresponding to a clock rate of 96 MHz. Figure 1 illustrates a block diagram of the sensor. Figure 1: Block Diagram Pixel Array EXTCLK RESET_BAR STANDBY_BAR OE Serial Interface Output 2752H x 2004V Array Control TRIGGER Analog Signal Chain Data Path SCLK SDATA SADDR PIXCLK DOUT[11:0] LV FV STROBE User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 5Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to 96 Mp/s, in addition to frame and line synchronization signals. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 1 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Functional Overview Figure 2: Typical Configuration (Connection) VDD_PLL VAA_PIX VAA VDD VDD_IO 10k 1.5k1 1.5k1 VDD_IO2,3 VDD2,3 VAA2,3 SADDR RESET_BAR STANDBY_BAR DOUT[11:0] PIXCLK FV LV STROBE 1F SCLK SDATA TRIGGER From controller Master clock EXTCLK TEST 1. A resistor value of 1.5k is recommended, but may be greater for slower two-wire speed. 2. All power supplies should be adequately decoupled. 3. All DGND pins must be tied together, as must all AGND pins, all VDD_IO pins, and all VDD pins. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN DOUT9 1 DOUT10 2 DOUT11 AGND 3 DGND TEST 4 VDD SCLK 5 VAA_PIX SDATA 6 VAA_PIX RSVD 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View) 48 47 46 45 44 43 DOUT6 DGND 39 VDD_IO VDD_IO 11 38 DOUT5 VDD 12 37 DOUT4 SADDR 13 36 DOUT3 STANDBY_BAR 14 35 DOUT2 TRIGGER 15 34 DOUT1 RESET_BAR 16 33 DOUT0 OE 17 32 PIXCLK NC 18 31 EXTCLK 19 20 21 22 23 24 25 26 27 28 29 30 NC 40 NC 9 10 NC STROBE NC DOUT7 DGND 41 VDD_PLL 8 VAA LINE_VALID VAA DOUT8 TEST 42 AGND 7 TEST FRAME_VALID NC Figure 3: AGND3 DGND3 OE RSVD Notes: To controller 2 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Functional Overview Table 3: Pin Description Name Type Description RESET_BAR Input EXTCLK SCLK OE Input Input Input STANDBY_BAR Input TRIGGER Input SADDR Input SDATA PIXCLK I/O Output DOUT[11:0] Output FRAME_VALID Output LINE_VALID STROBE VDD VDD_IO DGND VAA VAA_PIX AGND VDD_PLL TEST RSVD NC Output Output Supply Supply Supply Supply Supply Supply Supply -- -- -- When LOW, the MT9P401 asynchronously resets. When driven HIGH, it resumes normal operation with all configuration registers set to factory defaults. External input clock. Serial clock. Pull to VDD_IO with a 1.5k resistor. When HIGH, the PIXCLK, DOUT, FV, LV, and STROBE outputs enter a High-Z. When driven LOW, normal operation resumes. Standby. When LOW, the chip enters a low-power standby mode. It resumes normal operation when the pin is driven HIGH. Snapshot trigger. Used to trigger one frame of output in snapshot modes, and to indicate the end of exposure in bulb exposure modes. Serial address. When HIGH, the MT9P401 responds to device ID (BA)H. When LOW, it responds to serial device ID (90)H. Serial data. Pull to VDD_IO with a 1.5k resistor. Pixel clock. The DOUT, FV, LV, and STROBE outputs should be captured on the falling edge of this signal. Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each pixel, to be captured on the falling edge of PIXCLK. Frame valid. Driven HIGH during active pixels and horizontal blanking of each frame and LOW during vertical blanking. Line valid. Driven HIGH with active pixels of each line and LOW during blanking periods. Snapshot strobe. Driven HIGH when all pixels are exposing in snapshot modes. Digital supply voltage. Nominally 1.8V. IO supply voltage. Nominally 1.8 or 2.8V. Digital ground. Analog supply voltage. Nominally 2.8V. Pixel supply voltage. Nominally 2.8V, connected externally to VAA. Analog ground. PLL supply voltage. Nominally 2.8V, connected externally to VAA. Tie to AGND for normal device operation (factory use only). Tie to DGND for normal device operation (factory use only). No connect. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 3 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure The MT9P401 pixel array consists of a 2752-column by 2004-row matrix of pixels addressed by column and row. The address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in Figure 4 on page 5. The array consists of a 2592-column by 1944-row active region in the center representing the default output image, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see Table 4 and Table 5). The boundary region can be used to avoid edge effects when doing color processing to achieve a 2592 x 1944 result image, while the optically black column and rows can be used to monitor the black level. Pixels are output in a Bayer pattern format consisting of four "colors"--GreenR, GreenB, Red, and Blue (Gr, Gb, R, B)--representing three filter colors. When no mirror modes are enabled, the first row output alternates between Gr and R pixels, and the second row output alternates between B and Gb pixels. The Gr and Gb pixels have the same color filter, but they are treated as separate colors by the data path and analog signal chain. Table 4: Table 5: Pixel Type by Column Column Pixel Type 0-9 10-15 16-2607 2608-2617 2618-2751 Dark (10) Active boundary (6) Active image (2592) Active boundary (10) Dark (134) Row Pixel Type 0- 49 50-53 54-1997 1998-2001 2002-2003 Dark (50) Active boundary (4) Active image (1944) Active boundary (3) Dark (2) Pixel Type by Row PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 4 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Pixel Data Format Figure 4: Pixel Array Description (0,0) 50 black rows 4 (16,54) Active Image 134 black columns 6 2592 x 1944 active pixels 10 10 black columns 4 2 black rows (2751, 2003) Figure 5: Pixel Color Pattern Detail (Top Right Corner) column readout direction .. . black pixels FIrst clear pixel (10,50) Gr R Gr R Gr R Gr row readout direction B Gb B Gb B Gb B ... Gr R Gr R Gr R Gr B Gb B Gb B Gb B Gr R Gr R Gr R Gr B Gb B Gb B Gb B .. . Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 4). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (16, 54). When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 5. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 6 on page 6. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 5 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Pixel Data Format Figure 6: Imaging a Scene Lens Scene Sensor (rear view) Row Readout Order Column Readout Order Pixel (0,0) Output Data Format (Default Mode) The MT9P401 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown in Figure 7. LV is HIGH during the shaded region of the figure. FV timing is described in "Output Data Timing" on page 8. Figure 7: Spatial Illustration of Image Readout P0,0 P0,1 P0,2.....................................P0,n-1 P0,n P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VALID IMAGE HORIZONTAL BLANKING Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00 Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 6 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Pixel Data Format Readout Sequence Typically, the readout window is set to a region including only active pixels. The user has the option of reading out dark regions of the array, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. Rows are read from the array in the following order: 1. Dark rows: If Show_Dark_Rows is set, or if Manual_BLC is clear, dark rows on the top of the array are read out. The set of rows sampled are adjusted based on the Row_Bin setting such that there are 8 rows after binning, as shown in the Table 6. The Row_Skip setting is ignored for the dark row region. If Show_Dark_Rows is clear and Manual_BLC is set, no dark rows are read from the array as part of this step, allowing all rows to be part of the active image. This does not change the frame time, as HDR is included in the vertical blank period. 2. Active image: The rows defined by the row start, row size, bin, skip, and row mirror settings are read out. If this set of rows includes rows read out above, those rows are resampled, meaning that the data is invalid. Table 6: Dark Rows Sampled as a Function of Row_Bin Row_Bin HDR (Dark Rows After Binning) 0 1 3 8 8 8 Columns are read out in the following order: 1. Dark columns: If either Show_Dark_Columns or Row_BLC is set, dark columns on the left side of the image are read out followed by those on the right side. The set of columns read is shown in Table 7. The Column_Skip setting is ignored for the dark columns. If neither Show_Dark_Columns nor Row_BLC is set, no dark columns are read, allowing all columns to be part of the active image. This does not change the row time, as WDC is included in the vertical blank period. 2. Active image: The columns defined by column start, column size, bin, skip, and column mirror settings are read out. If this set of columns includes the columns read out above, these columns are resampled, meaning the data is invalid. Table 7: Dark Columns Sampled as a Function of Column_Bin PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Column_Bin WDC (Dark Columns After Binning) 0 1 3 80 40 20 7 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Output Data Timing Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 1944 rows of 2592 columns each. The FV and LV signals indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, one 12-bit pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is negated are called vertical blanking. PIXCLK cycles that occur when only LV is negated are called horizontal blanking. Figure 8: Default Pixel Output Timing PIXCLK FV LV DOUT[11:0] P0 Vertical Blanking Horiz Blanking P1 P2 P3 P4 Valid Image Data Pn Horiz Blanking Vertical Blanking LV and FV The timing of the FV and LV outputs is closely related to the row time and the frame time. FV will be asserted for an integral number of row times, which will normally be equal to the height of the output image. If Show_Dark_Rows is set, the dark sample rows will be output before the active image, and FV will be extended to include them. In this case, FV's leading edge happens at time 0. LV will be asserted during the valid pixels of each row. The leading edge of LV will be offset from the leading edge of FV by 609 PIXCLKs. If Show_Dark_Columns is set, the dark columns will be output before the image pixels, and LV will be extended back to include them; in this case, the first pixel of the active image still occurs at the same position relative to the leading edge of FV. Normally, LV will only be asserted if FV is asserted; this is configurable as described below. LV Format Options The default situation is for LV to be negated when FV is negated. The other option available is shown in Figure 9 on page 9. If Continuous_LV is set, LV is asserted even when FV is not, with the same period and duty cycle. If XOR_Line_Valid is set, but not Continuous_Line_Valid, the resulting LV will be the XOR of FV and the continuous LV. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 8 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Output Data Timing Figure 9: LV Format Options FV Default LV FV Continuous LV LV FV XOR LV LV The timing of an entire frame is shown in Figure 10. Figure 10: Frame Timing t ROW W WDC LV Dark Columns Dark Rows FV Row Readout H tFRAME HDR Column Readout Active Image Blanking Region PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 9 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Output Data Timing Frame Time The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array, and is typically equal to 1 EXTCLK period. The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row time (tROW) is the period from the first pixel output in a row to the first pixel output in the next row. The row time and frame time are defined by equations in Table 8. Table 8: Frame Time Parameter Name fps tFRAME t ROW Frame Rate Frame Time Row Time tROW_ Row Time Default tROW_ HDTV W H SW HB VB HBMIN VBMIN tPIXCLK Default Timing at EXTCLK = 96 MHz Equation 1/tFRAME (H + max(VB, VBMIN)) x tROW t 2 x PIXCLK x max(((W/2) + max(HB, HBMIN)), (41 + 346 x (Row_Bin+1) + 99)) 2 x tPIXCLK x max(((W/2) + max(HB, HBMIN)), (41 + 346 x (Row_Bin+1) + 99)) 2 x tPIXCLK x max(((W/2) + max(HB, HBMIN)), (41 + 186 x (Row_Bin+1) + 99)) 2 x ceil((Column_Size + 1) / (2 x (Column_Skip + 1))) 2 x ceil((Row_Size + 1) / (2 x (Row_Skip + 1))) max (1, (2 * 16 x Shutter_Width_Upper) + Shutter_Width_Lower) Horizontal_Blank + 1 Vertical_Blank + 1 346 x (Row_Bin + 1) + 64 + (WDC / 2) Row Time Output Image Width Output Image Height Shutter Width Horizontal Blanking Vertical Blanking Minimum Horizontal Blanking Minimum Vertical Blanking Pixclk Period max (8, SW - H) + 1 1/fPIXCLK 14 71.66ms 36.38s 36.38s 24.4s 2592 PIXCLK 1944 rows 1943 rows 1 PIXCLK 26 rows 450 PIXCLK 9 rows 10.42ns The minimum horizontal blanking (HBMIN) values for various Row_Bin and Column_Bin settings are shown in Table 9. Table 9: HBMIN Values for Row_bin vs. Column_bin Settings Row_b in PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 0 1 3 Column_bin (WDC) 0 1 450 430 796 776 1488 1468 10 3 420 766 1458 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Output Data Timing Frame Rates at Common Resolutions Table 10 and Table 11 show examples of register settings to achieve common resolutions and their frame rates. Frame rates are shown both with subsampling enabled and disabled. Table 10: Standard Resolutions Resolution 2592 x 1944 (Full Resolution) 2048 x 1536 QXGA 1600 x 1200 UXGA 1280 x 1024 SXGA Frame Rate Sub-sampling Column_Si Mode ze (R0x04) Row_ Size (R0x03) Shutter_ Width_ Lower (R0x09) Row_ Bin (R0x22 [5:4]) Row_ Skip (R0x22 [2:0]) Column_Bi Column_S n (R0x23 kip (R0x23 [5:4]) [2:0]) 14 N/A 2591 1943 <1943 0 0 0 0 21 31 42 63 63 47 90 90 65 123 123 53 N/A N/A N/A N/A skipping binning N/A skipping binning N/A skipping binning 2047 1599 1279 1023 2047 2047 799 1599 1599 639 2559 2559 1535 1199 1023 767 1535 1535 599 1199 1199 479 1919 1919 <1535 <1199 <1023 0 0 0 0 0 1 0 0 1 0 0 3 0 0 0 0 1 1 0 1 1 0 3 3 0 0 0 0 0 1 0 0 1 0 0 3 0 0 0 0 1 1 0 1 1 0 3 3 Resolution Frame Rate Subsampling Mode Column_Si ze (R0x04) Row_ Size (R0x03) Shutter_ Width_ Lower (R0x09) Row_ Bin (R0x22 [5:4]) Row_ Skip (R0x22 [2:0]) 1920 x 1080 HDTV 1280 x 720 HDTV 31 60 N/A binning 1919 2559 1079 1439 <1079 <719 0 1 0 1 1024 x 768 XGA 800 x 600 SVGA 640 x 480 VGA Table 11: <767 <599 <479 Wide Screen (16:9) Resolutions Notes: PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Column_Bi Column_S n (R0x23 kip (R0x23 [5:4]) [2:0]) 0 1 0 1 1. It is assumed that the minimum horizontal blanking and the minimum vertical blanking conditions are met, and that all other registers are set to default values. Please refer to TN09111 for instructions on how to configure 720p HDTV. 11 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9P401 through the two-wire serial interface bus. The MT9P401 is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9P401 through the serial data (SDATA) line. The SDATA line is pulled up to VDD_IO offchip by a 1.5k resistor. Either the slave or master device can pull the SDATA line LOW--the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial defines several different transmission codes, as follows: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request is a READ or a WRITE, where a "0" indicates a WRITE and a "1" indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request is a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9P401 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the WRITE request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 12 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Serial Bus Description Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A "0" in the LSB (least significant bit) of the address indicates write mode (0xBA), and a "1" indicates read mode (0xBB). Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock--it can only change when the serial clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 13 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Two-Wire Serial Interface Sample Write and Read Sequences Two-Wire Serial Interface Sample Write and Read Sequences 16-Bit WRITE Sequence A typical WRITE sequence for writing 16 bits to a register is shown in Figure 11. A start bit given by the master, followed by the write address, starts the sequence. The image sensor then gives an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each 8-bit transfer, the image sensor gives an acknowledge bit. All 16 bits must be written before the register is updated. After 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. The master stops writing by sending a start or stop bit. Figure 11: Timing Diagram Showing a WRITE to Reg0x09 with the Value 0x0284 SCLK SDATA Reg0x09 0xBA ADDR START ACK 0000 0010 ACK 1000 0100 ACK STOP ACK 16-Bit READ Sequence A typical READ sequence is shown in Figure 12. First the master has to write the register address, as in a WRITE sequence. Then a start bit and the read address specify that a READ is about to happen from the register. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Figure 12: Timing Diagram Showing a READ from Reg0x09; Returned Value 0x0284 SCLK SDATA 0xBA ADDR START PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Reg0x09 ACK 0xBB ADDR ACK START 14 1000 0100 0000 0010 ACK ACK STOP NACK . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Registers Register List Table 12 lists sensor registers and their default values. Table 12: Register List and Default Values 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic Register # Dec (Hex) Register Description Data Format (Binary) R0:0(R0x000) R1:0(R0x001) R2:0(R0x002) R3:0(R0x003) R4:0(R0x004) R5:0(R0x005) R6:0(R0x006) R7:0(R0x007) R8:0(R0x008) R9:0(R0x009) R10:0(R0x00A) R11:0(R0x00B) R12:0(R0x00C) R13:0(R0x00D) R15:0(R0x00F) R16:0(R0x010) R17:0(R0x011) R18:0(R0x012) R20:0(R0x014) R21:0(R0x015) R30:0(R0x01E) R32:0(R0x020) R34:0(R0x022) R35:0(R0x023) R36:0(R0x024) R39:0(R0x027) R41:0(R0x029) R42:0(R0x02A) R43:0(R0x02B) R44:0(R0x02C) R45:0(R0x02D) R46:0(R0x02E) R48:0(R0x030) R50:0(R0x032) R53:0(R0x035) R60:0(R0x03C) R61:0(R0x03D) R62:0(R0x03E) R63:0(R0x03F) Chip Version Row Start Column Start Row Size Column Size Horizontal Blank Vertical Blank Output Control Shutter Width Upper Shutter Width Lower Pixel Clock Control Restart Shutter Delay Reset Reserved PLL Control PLL Config 1 PLL Config 2 Reserved Reserved Read Mode 1 Read Mode 2 Row Address Mode Column Address Mode Reserved Reserved Reserved Reserved Green1 Gain Blue Gain Red Gain Green2 Gain Reserved Reserved Global Gain Reserved Reserved Reserved Reserved ???? ???? ???? ???? 0000 0ddd dddd dddd 0000 dddd dddd dddd 0000 0ddd dddd dddd 0000 dddd dddd dddd 0000 dddd dddd dddd 0000 0ddd dddd dddd 0d0d dddd dddd dddd 0000 0000 0000 dddd dddd dddd dddd dddd d000 0ddd 0ddd dddd 0000 0000 0000 0ddd 000d dddd dddd dddd 0000 0000 0000 000d - ddd0 000d dddd 00dd dddd dddd 00dd dddd 000d dddd 000d dddd - - 0ddd dddd dddd dddd dddd d000 0ddd 00d0 0ddd 0ddd 00dd 0ddd 0000 0ddd 00dd 0ddd - - - - 0ddd dddd dddd dddd 0ddd dddd dddd dddd 0ddd dddd dddd dddd 0ddd dddd dddd dddd - - dddd dddd dddd dddd - - - - PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 15 Default Value Dec (Hex) 6145 (0x1801) 54 (0x0036) 16 (0x0010) 1943 (0x0797) 2591 (0x0A1F) 0 (0x0000) 25 (0x0019) 8066 (0x1F82) 0 (0x0000) 1943 (0x0797) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 80 (0x0050) 25604 (0x6404) 0 (0x0000) 54 (0x0036) 16 (0x0010) 16390 (0x4006) 64 (0x0040) 0 (0x0000) 0 (0x0000) 2 (0x0002) 11 (0x000B) 1153 (0x0481) 4230 (0x1086) 8 (0x0008) 8 (0x0008) 8 (0x0008) 8 (0x0008) 0 (0x0000) 0 (0x0000) 8 (0x0008) 4112 (0x1010) 5 (0x0005) 64 (0x80C7) 4 (0x0004) . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 12: Register List and Default Values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic Register # Dec (Hex) Register Description Data Format (Binary) R64:0(R0x040) R65:0(R0x041) R66:0(R0x042) R67:0(R0x043) R68:0(R0x044) R69:0(R0x045) R70:0(R0x046) R71:0(R0x047) R72:0(R0x048) R73:0(R0x049) R74:0(R0x04A) R75:0(R0x04B) R76:0(R0x04C) R77:0(R0x04D) R78:0(R0x04E) R79:0(R0x04F) R80:0(R0x050) R81:0(R0x051) R82:0(R0x052) R83:0(R0x053) R84:0(R0x054) R86:0(R0x056) R87:0(R0x057) R88:0(R0x058) R89:0(R0x059) R90:0(R0x05A) R91:0(R0x05B) R92:0(R0x05C) R93:0(R0x05D) R94:0(R0x05E) R95:0(R0x05F) R96:0(R0x060) R97:0(R0x061) R98:0(R0x062) R99:0(R0x063) R100:0(R0x064) R101:0(R0x065) R104:0(R0x068) R105:0(R0x069) R106:0(R0x06A) R107:0(R0x06B) R108:0(R0x06C) R109:0(R0x06D) R112:0(R0x070) R113:0(R0x071) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reservedt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserveds Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 16 Default Value Dec (Hex) 7 (0x0007) 3 (0x0000) 5 (0x0003) 1 (0x0003) 515 (0x0203) 4112 (0x1010) 4112 (0x1010) 4112 (0x1010) 16 (0x0010) 168 (0x00A8) 16 (0x0010) 40 (0x0028) 16 (0x0010) 8224 (0x2020) 4112 (0x1010) 23 (0x0014) 32768 (0x8000) 7 (0x0007) 32768 (0x8000) 7 (0x0007) 8 (0x0008) 32 (0x0020) 4 (0x0004) 32768 (0x8000) 7 (0x0007) 4 (0x0004) 1 (0x0001) 90 (0x005A) 11539 (0x2D13) 16895 (0x41FF) 8989 (0x231D) 32 (0x0020) 32 (0x0020) 0 (0x0000) 32 (0x0020) 32 (0x0020) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 103 (0x00AC) 25604 (0xA700) . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 12: Register List and Default Values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic Register # Dec (Hex) Register Description Data Format (Binary) R114:0(R0x072) R115:0(R0x073) R116:0(R0x074) R117:0(R0x075) R118:0(R0x076) R119:0(R0x077) R120:0(R0x078) R121:0(R0x079) R122:0(R0x07A) R123:0(R0x07B) R124:0(R0x07C) R125:0(R0x07D) R126:0(R0x07E) R127:0(R0x07F) R128:0(R0x080) R129:0(R0x081) R130:0(R0x082) R131:0(R0x083) R132:0(R0x084) R134:0(R0x086) R135:0(R0x087) R144:0(R0x090) R145:0(R0x091) R146:0(R0x092) R147:0(R0x093) R149:0(R0x095) R150:0(R0x096) R151:0(R0x097) R152:0(R0x098) R153:0(R0x099) R154:0(R0x09A) R155:0(R0x09B) R156:0(R0x09C) R160:0(R0x0A0) R161:0(R0x0A1) R162:0(R0x0A2) R163:0(R0x0A3) R164:0(R0x0A4) R165:0(R0x0A5) R166:0(R0x0A6) R167:0(R0x0A7) R168:0(R0x0A8) R169:0(R0x0A9) R170:0(R0x0AA) R171:0(R0x0AB) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Test_Pattern_Control Test_Pattern_Green Test_Pattern_Red Test_Pattern_Blue Test_Pattern_Bar_Width Reserved Reserved Reserved Reserved Reserved Reserved Reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 17 Default Value Dec (Hex) 25094 (0xA700) 5128 (0x0C00) 5642 (0x0600) 13068 (0x5 617) 18229 (0x6B57) 18743 (0x6B57) 24633 (0xA500) 26114 (0xAB00) 25604 (0xA904) 25094 (0xA700) 25094 (0xA700) 65280 (0xFF00) 25608 (0xA900) 25604 (0x6404) 34 (0x0022) 7940 (0x1F04) 0 (0x0000) 6918 (0x1B06) 7432 (0x1D08) 6150 (0x1806) 6664 (0x1A08) 2000 (0x07D0) 0 (0x0000) 1 (0x0001) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 12: Register List and Default Values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic Register # Dec (Hex) Register Description Data Format (Binary) R172:0(R0x0AC) R173:0(R0x0AD) R174:0(R0x0AE) R175:0(R0x0AF) R176:0(R0x0B0) R177:0(R0x0B1) R178:0(R0x0B2) R179:0(R0x0B3) R180:0(R0x0B4) R181:0(R0x0B5) R182:0(R0x0B6) R183:0(R0x0B7) R184:0(R0x0B8) R185:0(R0x0B9) R186:0(R0x0BA) R187:0(R0x0BB) R188:0(R0x0BC) R189:0(R0x0BD) R190:0(R0x0BE) R191:0(R0x0BF) R192:0(R0x0C0) R193:0(R0x0C1) R194:0(R0x0C2) R195:0(R0x0C3) R196:0(R0x0C4) R197:0(R0x0C5) R198:0(R0x0C6) R199:0(R0x0C7) R200:0(R0x0C8) R201:0(R0x0C9) R202:0(R0x0CA) R203:0(R0x0CB) R204:0(R0x0CC) R205:0(R0x0CD) R206:0(R0x0CE) R207:0(R0x0CF) R208:0(R0x0D0) R209:0(R0x0D1) R210:0(R0x0D2) R211:0(R0x0D3) R212:0(R0x0D4) R213:0(R0x0D5) R214:0(R0x0D6) R215:0(R0x0D7) R216:0(R0x0D8) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 18 Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 32 (0x0020) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 12: Register List and Default Values (continued) 1 = read-only, always 1; 0 = read-only, always 0; d = programmable; ? = read-only, dynamic Register # Dec (Hex) Register Description Data Format (Binary) R217:0(R0x0D9) R218:0(R0x0DA) R219:0(R0x0DB) R220:0(R0x0DC) R221:0(R0x0DD) R222:0(R0x0DE) R223:0(R0x0DF) R224:0(R0x0E0) R225:0(R0x0E1) R226:0(R0x0E2) R227:0(R0x0E3) R228:0(R0x0E4) R229:0(R0x0E5) R230:0(R0x0E6) R231:0(R0x0E7) R232:0(R0x0E8) R233:0(R0x0E9) R234:0(R0x0EA) R235:0(R0x0EB) R236:0(R0x0EC) R237:0(R0x0ED) R238:0(R0x0EE) R239:0(R0x0EF) R240:0(R0x0F0) R241:0(R0x0F1) R248:0(R0x0F8) R250:0(R0x0FA) R251:0(R0x0FB) R252:0(R0x0FC) R253:0(R0x0FD) R255:0(R0x0FF) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chip_Version_Alt - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ???? ???? ???? ???? PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 19 Default Value Dec (Hex) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 0 (0x0000) 6145 (0x1801) . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Register Description Table 13 lists sensor register descriptions. Table 13: Register Description Reg. # Bits Default Name R0:0 R0x000 15:0 15:8 0x1801 RO 7:4 RO 3:0 RO Chip Version (RO) Part ID Two-digit BCD value typically derived from the reticle ID code. Legal values: [0, 255]. Analog Revision Constant value incremented with each mask change for the same Part ID. Legal values: [0, 15]. Digital Revision Constant value incremented with each digital functionality change for the same Part ID. Legal values: [0, 15]. R1:0 R0x001 R2:0 R0x002 R3:0 R0x003 R4:0 R0x004 R5:0 R0x005 R6:0 R0x006 Chip version. 15:0 0x0036 Row Start (RW) The Y coordinate of the upper-left corner of the FOV. If this register is set to an odd value, the next lower even value will be used. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [0, 2004], even. 15:0 0x0010 Column Start (RW) The X coordinate of the upper-left corner of the FOV. The value will be rounded down to the nearest multiple of 2 times the column bin factor. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Legal values: [0, 2750], even. Note: Set Column_Start such that it is in the form shown below, where n is an integer: Mirror_Column = 0 Mirror_Column = 1 no bin 4n 4n + 2 Bin 2x 8n 8n + 4 Bin 4x 16n 16n + 8 15:0 0x0797 Row Size (RW) The height of the FOV minus one. If this register is set to an even value, the next higher odd value will be used. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [1, 2005], odd. 15:0 0x0A1F Column Size (RW) The width of the field of view minus one. If this register is set to an even value, the next higher odd value will be used. In other words, it should be (2*n*(Column_Bin + 1) - 1) for some integer n. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [1, 2751], odd. 15:0 0x0000 Horizontal Blank (RW) Extra time added to the end of each row, in pixel clocks. Incrementing this register will increase exposure and decrease frame rate. Setting a value less than the minimum will use the minumum horizontal blank. The minimum horizontal blank depends on the mode of the sensor. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [0, 4095]. 15:0 0x0019 Vertical Blank (RW) Extra time added to the end of each frame in rows minus one. Incrementing this register will decrease frame rate, but not affect exposure. Setting a value less than the minimum will use the minimum vertical blank. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Legal values: [8, 2047]. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 20 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R7:0 R0x007 15:0 15 14 13 12:10 0x1F82 X 0x0000 X 0x0007 9:7 0x0007 6 5:4 3 2 0x0000 X 0x0000 0x0000 1 0x0001 0 0x0000 Output Control (RW) Reserved Reserved Reserved Output_Slew_Rate Controls the slew rate on digital output pads except for PIXCLK. Higher values imply faster transition times. Legal values: [0, 7]. PIXCLK_Slew_Rate Controls the slew rate on the PIXCLK pad. Higher values imply faster transition times. Legal values: [0, 7]. Reserved Reserved Reserved FIFO_Parallel_Data When set, pixels will be sent through the output FIFO before being sent off chip. This allows the output port to be running at a slower speed than f_PIXCLK, because the FIFO allows for pixels to be output during horizontal blank. Use of this mode requires the PLL to be set up properly. Chip Enable When clear, sensor readout is stopped and analog circuitry is put in a state which draws minimal power. When set, the chip operates according to the current mode. Writing this bit does not affect the values of any other registers. Synchronize Changes When set, changes to certain registers (those with the SC attribute) are delayed until the bit is clear. When cleared, all the delayed writes will happen immediately. Registers with the F attribute will still have the update synchronized to the next frame boundary. R8:0 R0x008 R9:0 R0x009 15:0 0x0000 Shutter Width Upper (RW) The most significant bits of the shutter width, which are combined with Shutter Width Lower (R9). 15:0 0x0797 Shutter Width Lower (RW) The least significant bits of the shutter width. This is combined with Shutter_Width_Upper and Shutter_Delay for the effective shutter width. If set to zero, a value of "1" will be used. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 21 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R10:0 R0x00A 15:0 15 0x0000 0x0000 14:11 10:8 X 0x0000 7 6:0 X 0x0000 15:0 15:3 2 0x0000 X 0x0000 1 0x0000 0 0x0000 Pixel Clock Control (RW) Invert Pixel Clock When set, LV, FV, and D_OUT should be captured on the rising edge of PIXCLK. When clear, they should be captured on the falling edge. This is accomplished by inverting the PIXCLK output. NOTE: This field is not reset by the soft Reset (R13). Reserved Shift Pixel Clock Two's complement value representing how far to shift the PIXCLK output pin relative to DOUT, in EXTCLK cycles. Positive values shift PIXCLK later in time relative to DOUT (and thus relative to the internal array/datapath clock). No effect unless PIXCLK is divided by Divide Pixel Clock. NOTE: This field is not reset by the soft Reset (R13). Legal values: [-2, 2]. Reserved Divide Pixel Clock Produces a PIXCLK that is divided by the value times two. The value must be zero or a power of 2. This will slow down the internal clock in the array control and datapath blocks, including pixel readout. It will not affect the two-wire serial interface clock. A value of "0" corresponds to a PIXCLK with the same frequency as EXTCLK. A value of 1 means f_PIXCLK = (f_EXTCLK / 2); 2 means f_PIXCLK = (f_EXTCLK / 4); 64 means f_PIXCLK = (f_EXTCLK / 128); and so on. NOTE: This field is not reset by the soft Reset (R13). This field should not be written while in streaming mode. Instead, Pause_Restart should be used to suspend output while the divider is being changed. Legal values: [0, 1, 2, 4, 8, 16, 32, 64]. Restart (RW) Reserved Trigger Setting this bit in Snapshot mode will cause the next trigger to occur as if the TRIGGER pin were properly asserted/negated. Ineffective if not in Snapshot mode. The sense of this bit is NOT affected by Invert Trigger. When using this bit instead of the TRIGGER pin, make sure that either the trigger pin is continuously asserted, or that the pad is continuously negated and Invert_Trigger is set. Pause Restart When set, Restart will not automatically be cleared. Instead, the sensor will pause at row 0 after Restart is set. When Pause_Restart is cleared, the sensor will resume. This allows for a repeatable delay from clearing restart to FV. When clearing this bit, be sure not to clear Restart as well: it will be cleared automatically when the device has restarted. Restart Setting this bit will cause the sensor to abandon the current frame and restart from the first row. It will take up to 2 * t_ROW for the restart to take effect. This bit resets to 0 automatically unless Pause_Restart is set. Manually setting this bit to zero will cause undefined behavior. Volatile. R11:0 R0x00B R12:0 R0x00C R13:0 R0x00D 15:0 0x0000 Shutter Delay (RW) A negative adjustment to the effective shutter width in ACLKs. See Shutter_Width_Lower. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Legal values: [0, 8191]. 15:0 0x0000 Reset (RW) Setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state and cause it to halt. Clearing this bit will resume normal operation. This is equivalent to pulling RESET_BAR LOW, except that the two-wire serial interface remains functional. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 22 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R16:0 R0x010 15:0 15 14:13 12:9 8 7:4 3:2 1 0x0050 0x0000 0x0000 X 0x0000 0x0005 X 0x0000 0 0x0000 15:0 15:8 0x6404 0x0064 7:6 5:0 X 0x0004 15:0 15:13 12:8 7:5 4:0 0x0000 X 0x0000 X 0x0000 PLL Control (RW) Reserved Reserved Reserved Reserved Reserved Reserved Use PLL When set, use the PLL output as the system clock. When clear, use EXTCLK as the system clock. Power PLL When set, the PLL is powered. When clear, it is not powered. PLL Config 1 (RW) PLL m Factor PLL output frequency multiplier. Legal values: [16, 255]. Reserved PLL n Divider PLL output frequency divider minus 1. Legal values: [0, 63]. PLL Config 2 (RW) Reserved Reserved Reserved PLL p1 Divider PLL system clock divider minus 1. Use odd numbers. If this is set to an even number, the system clock duty cycle will not be 50:50. In this case, set all bits in R101 or slow down EXTCLK. Legal values: [0, 127]. R17:0 R0x011 R18:0 R0x012 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 23 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R30:0 R0x01E 15:0 15 14 13 12 11 0x4006 X 0x0001 0x0000 0x0000 0x0000 10 0x0000 9 0x0000 8 0x0000 7 0x0000 6 0x0000 5 0x0000 4 0x0000 3:2 0x0001 1:0 0x0002 Read Mode 1 (RW) Reserved Reserved Reserved Reserved XOR Line Valid When set, produce a LV signal that is the XOR of FV and the normal line_valid. Ineffective if Continuous Line Valid is set. When clear, produce a normal LV. Continuous Line Valid When set, produce the LV signal even during the vertical blank period. When clear, produce LV only when active rows are being read out (that is, only when FV is high). Ineffective if FIFO_Parallel_Data is set. Invert Trigger When set, the sense of the TRIGGER input pin will be inverted. Snapshot When set, the sensor enters snapshot mode, and will wait for a trigger event between frames. When clear, the sensor is in continuous mode. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Global Reset When set, the Global Reset Release shutter will be used. When clear, the Electronic Rolling Shutter will be used. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Bulb Exposure When set, exposure time will be controlled by an external trigger. When clear, exposure time will be controlled by the Shutter_Width_Lower and Shutter_Width_Upper registers. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Invert Strobe When set, the STROBE signal will be active LOW (during exposure). When clear, the STROBE signal is active HIGH. Strobe Enable When set, a strobe signal will be generated by the digital logic during integration. When clear, the strobe pin will be set to the value of Invert_Strobe. Strobe Start Determines the timepoint when the strobe is asserted. 0 - first trigger 1 - start of simultaneous exposure 2 - shutter width 3 - second trigger Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Strobe End Determines the timepoint when the strobe is negated. If this is set equal to or less than Strobe_Start, the width of the strobe pulse will be t_ROW. See Strobe_Start. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 24 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R32:0 R0x020 15:0 0x0040 15 0x0000 14 0x0000 13 12 0x0000 0x0000 11 0x0000 10:7 6 X 0x0001 5 0x0000 4 3:0 15:0 0x0000 X 0x0000 Read Mode 2 (RW) Mirror Row When set, row readout in the active image occurs in reverse numerical order starting from (Row_Start + Row_Size). When clear, row readout of the active image occurs in numerical order. This has no effect on the readout of the dark rows. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Mirror Column When set, column readout in the active image occurs in reverse numerical order, starting from (Column_Start + Column_Size). When clear, column readout of the active image occurs in numerical order. This has no effect on the readout of the dark columns. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Reserved Show Dark Columns When set, the dark columns will be output to the left of the active image, making the output image wider. This has no effect on integration time or frame rate. When clear, only columns that are part of the active image will be output. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Show Dark Rows When set, the dark rows will be output before the active image rows, making the output image taller. This has no effect on integration time or frame rate. When clear, only rows from the active image will be output. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Reserved Row BLC When set, digitally compensate for differing black levels between rows by adding Dark Target (R73) and subtracting the average value of the 8 same-color dark pixels at the beginning of the row. When clear, digitally add Row Black Default Offset (R75) to the value of each pixel. Column Sum When set, column summing will be enabled, and in column bin modes, all sampled capacitors will be enabled for column readout, resulting in an effective gain equal to the column bin factor. When clear, column averaging will be done, and there will be no additional gain related to the column bin factor. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Reserved Reserved 15 14:12 11 10:8 7:6 5:4 X 0x0000 X 0x0000 X 0x0000 3 2:0 X 0x0000 R34:0 R0x022 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Row Address Mode (RW) Reserved Reserved Reserved Reserved Reserved Row Bin The number of rows to be read and averaged per row output minus one. The rows will be read independently into sampling capacitors, then averaged together before column readout. For normal readout, this should be 0. For Bin 2X, it should be 1; for Bin 4X, it should be 3. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [0, 3]. Reserved Row Skip The number of row-pairs to skip for every row-pair output. A value of zero means to read every row. For Skip 2X, this should be 1; for Skip 3X, it should be 2, and so on. This value should be no less than Row_Bin. For full binning, Row_Skip should equal Row_Bin. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [0, 7]. 25 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R35:0 R0x023 15:0 15:11 10:8 7:6 5:4 0x0000 X 0x0000 X 0x0000 3 2:0 X 0x0000 15:0 15 14:8 0x0008 X 0x0000 7 6 X 0x0000 5:0 0x0008 Column Address Mode (RW) Reserved Reserved Reserved Column Bin The number of columns to be read and averaged per column output minus one. For normal readout, this should be zero. For Bin 2X, it shoud be 1; for Bin 4X, it should be 3. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: {0, 1, 3}. Reserved Column Skip The number of column-pairs to skip for every column-pair output. A value of zero means to read every column in the active image. For Skip 2X, this should be 1; for Skip 3X, this should be 2, and so on. This value should be no less than Column_Bin. For full binning, Column_Skip should equal Column_Bin. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Causes a Bad Frame if written. Legal values: [0, 6]. Green1 Gain (RW) Reserved Green1 Digital Gain Digital Gain for the Green1 channel minus 1 times 8. The actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [0, 120]. Reserved Green1 Analog Multiplier Analog gain multiplier for the Green1 channel minus 1. If 1, an additional analog gain of 2X will be applied. If 0, no additional gain is applied. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Green1 Analogl Gain Analog gain setting for the Green1 channel times 8. The effective gain for the channel is (((Green1_Digital_Gain/8) + 1) * (Green1_Analog_Multiplier + 1) * (Green1_Analog_Gain/8)). Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [8, 63]. 15:0 0x0008 15 14:8 X 0x0000 7 6 X 0x0000 5:0 0x0008 R43:0 R0x02B R44:0 R0x02C PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Blue Gain (RW) Reserved Blue Digital Gain Digital Gain for the Blue channel minus 1 times 8. The actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [0, 120]. Reserved Blue Analog Multiplier Analog gain multiplier for the Blue channel minus 1. If 1, an additional analog gain of 2X will be applied. If 0, no additional gain is applied. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Blue Analog Gain Analog gain setting for the Blue channel times 8. The effective gain for the channel is (((Blue_Digital_Gain/8) + 1) * (Blue_Analog_Multiplier + 1) * (Blue_Analog_Gain/8)). Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [8, 63]. 26 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R45:0 R0x02D 15:0 0x0008 15 14:8 X 0x0000 7 6 X 0x0000 5:0 0x0008 15:0 15 14:8 0x0008 X 0x0000 7 6 X 0x0000 5:0 0x0008 Red Gain (RW) Reserved Red Digital Gain Digital Gain for the Red channel minus 1 times 8. The actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [0, 120]. Reserved Red Analog Multiplier Analog gain multiplier for the Red channel minus 1. If 1, an additional analog gain of 2X will be applied. If 0, no additional gain is applied. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Red Analog Gain Analog gain setting for the Red channel times 8. The effective gain for the channel is (((Red_Digital_Gain/8) + 1) * (Red_Analog_Multiplier + 1) * (Red_Analog_Gain/8)). Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [8, 63]. Green2 Gain (RW) Reserved Green2 Digital Gain Digital Gain for the Green2 channel minus 1 times 8. The actual digital gain is (1 + value/8), and can range from 1 (a setting of 0) to 16 (a setting of 120) in increments of 1/8. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [0, 120]. Reserved Green2 Analog Multiplier Analog gain multiplier for the Green2 channel minus 1. If 1, an additional analog gain of 2X will be applied. If 0, no additional gain is applied. Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Green2 Analog Gain Analog gain setting for the Green2 channel times 8. The effective gain for the channel is (((Green2_Digital_Gain/8) + 1) * (Green2_Analog_Multiplier + 1) * (Green2_Analog_Gain/8)). Writes are synchronized to frame boundaries. Affected by Synchronize_Changes. Volatile. Legal values: [8, 63]. 15:0 0x0008 R46:0 R0x02E R53:0 R0x035 R73:0 R0x049 R75:0 R0x04B R91:0 R0x05B R92:0 R0x05C Global Gain (WO) Writing the Global_Gain sets all four individual gain registers R43-R46 to the value. This register should not be read. See Green1_Gain (R43) for a description of the various fields. Affected by Synchronize_Changes. Duplicate. Legal values: special 15:0 0x00A8 Row Black Target (RW) Reserved 15:0 0x0028 Row Black Default Offset (RW) Reserved 15:0 0x0001 BLC_Sample_Size (RW) Reserved 15:0 0x005A BLC_Tune_1 (RW) 15:12 X Reserved 11:8 0x0000 Reserved 7:0 0x005A Reserved PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 27 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R93:0 R0x05D 15:0 15 14:8 7 6:0 15:0 15 14:12 11:9 8:0 15:0 15 14:8 7 6:0 15:0 0x2D13 X 0x002D X 0x0013 0x41FF X 0x0004 X 0x01FF 0x231D X 0x0023 X 0x001D 0x0020 BLC_Delta_Thresholds (RW) Reserved Reserved Reserved Reserved BLC_Tune_2 (RW) Reserved Reserved Reserved Reserved BLC_Target_Thresholds (RW) Reserved Reserved Reserved Reserved Green1_Offset (RW) R94:0 R0x05E R95:0 R0x05F R96:0 R0x060 R97:0 R0x061 R98:0 R0x062 R99:0 R0x063 R100:0 R0x064 Reserved 15:0 0x0020 Green2_Offset (RW) Reserved 15:0 15 14 13 12 11 10:2 1 0 15:0 Black_Level_Calibration (RW) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Red_Offset (RW) 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 X 0x0000 0x0000 0x0020 Reserved 15:0 0x0020 Blue_Offset (RW) Reserved PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 28 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Registers Table 13: Register Description (continued) Reg. # Bits Default Name R160:0 R0x0A0 6:3 0x0000 Test_Pattern_Control Sets the test pattern mode: 0: color field 1: horizontal gradient 2: vertical gradient 3: diagonal 4: classic 5: walking 1s 6: monochrome horizontal bars 7: monochrome vertical bars 8: vertical color bars Legal values: [0, 15]. Reserved Reserved Enable_Test_Pattern Enables the test pattern. When set, data from the ADC will be replaced with a digitally generated test pattern specified by Test_Pattern_Mode. 2 1 0 R161:0 R0x0A1 11:0 0x0 0x0 0x0 0x0000 R162:0 R0x0A2 11:0 0x0000 R163:0 R0x0A3 11:0 0x0000 R164:0 R0x0A4 11:0 0x0000 R255:0 R0x0FF 15:0 0x1801 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Test_Pattern_Green Value used for green pixels of dark rows and columns in all test patterns, and for the color field. Legal values: [0, 4095]. Test_Pattern_Red As above for red. Legal values: [0, 4095]. Test_Pattern_Blue As above for blue. Legal values: [0, 4095]. Test_Pattern_Bar_Width The width of the monochrome color bars in test modes 6 and 7. This should be set to an odd value. Legal values: [0, 4095], odd. Chip_Version_Alt Mirror of R0[15:0]. Read-only. Duplicate. Appears in all pages. Legal values: special. 29 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Features Reset The MT9P401 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset Assert (LOW) RESET_BAR, it is not necessary to clock the device. All registers return to the factory defaults. When the pin is negated (HIGH), the chip resumes normal operation. Soft Reset Set the Reset register field to "1" (R0x0D[0] = 1). All registers except the following will be reset: * Chip_Enable * Synchronize_Changes * Reset * Use_PLL * Power_PLL * PLL_m_Factor * PLL_n_Divider * PLL_p1_Divider When the field is returned to "0," the chip resumes normal operation. Power Up and Power Down When first powering on the MT9P401, follow this sequence: 1. Ensure RESET_BAR is asserted (LOW). 2. Bring up the supplies. If both the analog and the digital supplies cannot be brought up simultaneously, ensure the digital supply comes up first. 3. Negate RESET_BAR (HIGH) to bring up the sensor. When powering down, be sure to follow this sequence to ensure that I/Os do not load any buses that they are connected to. 1. Assert RESET_BAR. 2. Remove the supplies. Clocks The MT9P401 requires one clock (EXTCLK), which is nominally 96 MHz. By default, this results in pixels being output on the DOUT pins at a maximum data rate of 96 Mp/s. With VDD_IO = 1.8V, maximum master clock and maximum data rate become 48 MHz and 48 Mp/s, respectively. The EXTCLK clock can be divided down internally by setting Divide_Pixel_Clock to a non-zero value. This slows down the operation of the chip as though EXTCLK had been divided externally. fPIXCLK= { PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN fEXTCLK if Divide_Pixel_Clock = 0 fEXTCLK / (2 x Divide_Pixel_Clock) otherwise 30 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features The DOUT, LV, FV, and STROBE outputs are launched on the rising edge of PIXCLK, and should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of PIXCLK is inverted from that shown in Figure 8 on page 8. In addition, if the pixel clock has been divided by Divide_Pixel_Clock, it can be shifted relative to the other outputs by setting Shift_Pixel_Clock. PLL-Generated Master Clock The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to multiply the prescaler output, and another divider stage to generate the output clock. The clocking structure is shown in Figure 13. PLL control registers can be programmed to generate desired master clock frequency. Note: Figure 13: The PLL control registers must be programmed while the sensor is in the software Standby state. The effect of programming the PLL divisors while the sensor is in the streaming state is undefined. PLL-Generated Master Clock PLL Input Clock EXTCLK Pre PLL Div (PFD) PLL Multiplier (VCO) N PLL_n_divider +1 PLL Output Clock M PLL_m_factor PLL Output Div 1 SYSCLK (PIXCLK) P1 PLL_p1_divider +1 PLL Setup The MT9P401 has a PLL which can be used to generate the pixel clock internally. To use the PLL: 1. Bring the MT9P401 up as normal, make sure that fEXTCLK is between 6 and 27 MHz and then power on the PLL by setting Power_PLL (R0x10[0] = 1). 2. Set PLL_m_Factor, PLL_n_Divider, and PLL_p1_Divider based on the desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, and P1 values to achieve the desired fPIXCLK using this formula: f PIXCLK = (fEXTCLK x M) / (N x P1) where M = PLL_m_Factor N = PLL_n_Divider + 1 P1 = PLL_p1_Divider + 1 Note: PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN If P1 is odd (that is, PLL_p1_Divider is even), the duty cycle of the internal system clock will not be 50:50. In this case, it is important that either a slower clock is used or all clock enable bits are set in R101. 31 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features 2 MHz < fEXTCLK / N < 13.5 MHz 180 MHz < (fEXTCLK x M) / N < 360 MHz It is desirable to keep (fEXTCLK / n) as large as possible within the limits. Also, "m" must be between 16 and 255, inclusive. 3. Wait 1ms to ensure that the VCO has locked. 4. Set Use_PLL (R0x10[1] = 1) to switch from EXTCLK to the PLL-generated clock. Standby and Chip Enable The MT9P401 can be put in a low-power Standby state by either method below: 1. Hard Standby: By pulling STANDBY_BAR LOW, or 2. Soft Standby: By clearing the Chip_Enable register field (R0x07[1] = 0). When the sensor is put in standby, all internal clocks are gated, and analog circuitry is put in a state that it draws minimal power. The two-wire serial interface remains minimally active so that the Chip_Enable bit can subsequently be cleared. Reads cannot be performed and only the Chip_Enable and Invert_Standby registers are writable. If the sensor was in continuous mode when put in standby, it resumes from where it was when standby was deactivated. Naturally, this frame and the next frame are corrupted, though the sensor itself does not realize this. As this could affect automatic black level calibration, it is recommended that either the chip be paused (by setting Restart_Pause) before being put in standby mode, or it be restarted (setting Restart) upon resumption of operation. For maximum power savings in standby mode, EXTCLK should not be toggling. When standby mode is entered, either by clearing Chip_Enable or by asserting STANDBY_BAR, the PLL is disabled automatically or powered down. It must be manually re-enabled when leaving standby as needed. Full-Array Readout The entire array, including dark pixels, can be read out without digital processing or automatic black level adjustments. This can be accomplished as follows: 1. Set Row_Start and Column_Start to 0. 2. Set Row_Size to 2003. 3. Set Column_Size to 2751. 4. Set Manual_BLC to 1. 5. Set Row_BLC to 0. 6. Set Row_Black_Default_Offset to 0. 7. Set Show_Dark_Rows and Show_Dark_Columns to 0. If automatic analog (coarse) BLC is desired, but no digital processing, modify the above settings as follows: 1. Set Row_Start to 12. 2. Set Row_Size to 1993. 3. Set Manual_BLC to 0. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 32 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features These settings result in the same array layout as above, but only 22 dark rows are available at the top of the array; the first eight are used in the black level algorithm, and there should be a two-row buffer between the black region and the active region. Window Control The output image window of the pixel (the FOV) is defined by four register fields. Column_Start and Row_Start define the X and Y coordinates of the upper-left corner of the FOV. Column_Size defines the width of the FOV, and Row_Size defines the height of the FOV in array pixels. The Column_Start and Row_Start fields must be set to an even number. The Column_Size and Row_Size fields must be set to odd numbers (resulting in an even size for the FOV). The Row_Start register should be set no lower than 12 if either Manual_BLC is clear or Show_Dark_Rows is set. If no special resolution modes are set (see below), the width of the output image, W, is Column_Size + 1) and the height, H, is (Row_Size + 1. Readout Modes Subsampling By default, the resolution of the output image is the full width and height of the FOV as defined in "Window Control". The output resolution can be reduced by two methods: Skipping and Binning. Row and column skip modes use subsampling to reduce the output resolution without reducing FOV. The MT9P401 also has row and column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes. This is achieved by the averaging of 2 or 3 adjacent rows and columns (adjacent same-color pixels). Both 2X and 4X binning modes are supported. Rows and columns can be binned independently. Skipping Skipping reduces resolution by using only selected pixels from the FOV in the output image. In skip mode, entire rows and columns of pixels are not sampled, resulting in a lower resolution output image. A skip 2X mode skips one Bayer pair of pixels for every pair output. Skip 3X skips two pairs for each one pair output. Rows and columns are always read out in pairs. If skip 2X mode is enabled with otherwise default sensor settings, the columns in the output image correspond to the pixel array columns 16, 17, 20, 21, 24, 25... . Figure 14: Eight Pixels in Normal and Column Skip 2X Readout Modes LV Normal readout DOUT[11:0] G0 [11:0] R0 [11:0] G1 [11:0] R1 [11:0] G0 [11:0] R0 [11:0] G2 [11:0] R2 [11:0] G2 [11:0] R2 [11:0] G3 [11:0] R3 [11:0] LV Column skip 2X readout DOUT[11:0] PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 33 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Skipping can be enabled separately for rows and columns. To enable skip mode, set either or both of Row_Skip and Column_Skip to the number of pixel pairs that should be skipped for each pair used in the output image. For example, to set column skip 2X mode, set Column_Skip to "1." The size of the output image is reduced by the skip mode as shown in the following two equations: W = 2 x ceil((Column_Size + 1) / (2 x (Column_Skip + 1))) H = 2 x ceil((Row_Size + 1) / (2 x (Row_Skip + 1))) Figure 15: Pixel Readout (no skipping) Y incrementing X incrementing Figure 16: Pixel Readout (Column Skip 2X) Y incrementing X incrementing PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 34 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Figure 17: Pixel Readout (Row Skip 2X) Y incrementing X incrementing Figure 18: Pixel Readout (Column Skip 2X, Row Skip 2X) Y incrementing X incrementing Binning Binning reduces resolution by combining adjacent same-color imager pixels to produce one output pixel. All of the pixels in the FOV contribute to the output image in bin mode. This can result in a more pleasing output image with reduced subsampling artifacts. It also improves low-light performance. For columns, the combination step can be either an averaging or summing operation. Depending on lighting conditions, one or the other may be desirable. In low-light conditions, summing produces a gain roughly equivalent to the column bin factor. Column summing may be enabled by setting Column_Sum. Binning works in conjunction with skipping. Pixels that would be skipped because of the Column_Skip and Row_Skip settings can be averaged instead by setting Column_Bin and Row_Bin to the number of neighbor pixels to be averaged with each output pixel. For example, to set bin 2x mode, set Column_Skip and Column_Bin to 1. Additionally, Column_Start must be a multiple of (2 * (Column_Bin + 1)) and Row_Start must be a multiple of (2 * (Row_Bin + 1)). PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 35 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Only certain combinations of binning and skipping are allowed. These are shown in Table 14. If an illegal skip value is selected for a bin mode, a legal value is selected instead. Table 14: Legal Values for Column_Skip Based on Column_Bin Note: Column_Bin Legal Values for Column_Skip 0 (no binning) 1 (Bin 2x) 3 (Bin 4x) 0, 1, 2, 3, 4, 5, 6 1, 3, 5 3 Ensure that Column_Start (R0x02) is set in the form shown below, where n is an integer: Mirror Column = 0 4n 8n 16n no bin Bin 2x Bin 4x Mirror Column = 1 4n + 2 8n + 4 16n + 8 Bin mode is illustrated in Figure 19 and Figure 20. Figure 19: Pixel Readout (Column Bin 2X) Y incrementing X incrementing Figure 20: Pixel Readout (Column Bin 2X, Row Bin 2X) Y incrementing X incrementing PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 36 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Mirror Column Mirror Image By setting R0x20[14] = 1, the readout order of the columns is reversed, as shown in Figure 21. The starting color, thus Bayer pattern, is preserved when mirroring the columns. Figure 21: Six Pixels in Normal and Column Mirror Readout Modes LV Normal readout G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] DOUT[11:0] Reverse readout DOUT[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0] G0[11:0] Row Mirror Image By setting R0x20[15] = 1, the readout order of the rows is reversed as shown in Figure 22. The starting color, thus Bayer pattern, is preserved when mirroring the rows. Figure 22: Six Rows in Normal and Row Mirror Readout Modes FV Normal readout Row0 [11:0] Row1 [11:0] Row2 [11:0] Row3 [11:0] Row4 [11:0] Row5 [11:0] DOUT[11:0] Reverse readout DOUT[11:0] Row5 [11:0] Row4 [11:0] Row3 [11:0] Row2 [11:0] Row1 [11:0] Row0 [11:0] By default, active pixels in the resulting image are output in row-major order (an entire row is output before the next row is begun), from lowest row/column number to highest. If desired, the output (and sampling) order of the rows and columns can be reversed. This affects only pixels in the active region defined above, not any pixels read out as dark rows or dark columns. When the readout direction is reversed, the color order is reversed as well (red, green, red, and so on, instead of green, red, green, and so on, for example). If row binning is combined with row mirroring, the binning is still done in the positive direction. Therefore, if the first output row in bin 2x + row mirror was 1997, pixels on rows 1997 and 1999 would be averaged together. The next pixel output would be from rows 1996 and 1998, followed by the average of 1993 and 1995. For column mirroring plus binning, the span of pixels used should be the same as with non-mirror mode. Maintaining a Constant Frame Rate Maintaining a constant frame rate while continuing to have the ability to adjust certain parameters is the desired scenario. This is not always possible, however, because register updates are synchronized to the read pointer, and the shutter pointer for a frame is PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 37 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features usually active during the readout of the previous frame. Therefore, any register changes that could affect the row time or the set of rows sampled causes the shutter pointer to start over at the beginning of the next frame. By default, the following register fields cause a "bubble" in the output rate (that is, the vertical blank increases for one frame) if they are written in continuous mode, even if the new value would not change the resulting frame rate: * Row_Start * Row_Size * Column_Size * Horizontal_Blank * Vertical_Blank * Shutter_Delay * Mirror_Row * Row_Bin * Row_Skip * Column_Skip The size of this bubble is (SW x tROW), calculating the row time according to the new settings. The Shutter_Width_Lower and Shutter_Width_Upper fields may be written without causing a bubble in the output rate under certain circumstances. Because the shutter sequence for the next frame often is active during the output of the current frame, this would not be possible without special provisions in the hardware. Writes to these registers take effect two frames after the frame they are written, which allows the shutter width to increase without interrupting the output or producing a corrupt frame (as long as the change in shutter width does not affect the frame time). Synchronizing Register Writes to Frame Boundaries Changes to most register fields that affect the size or brightness of an image take effect on the frame after the one during which they are written. These fields are noted as "synchronized to frame boundaries" in Table 12: Register List and Default Values on page 15. To ensure that a register update takes effect on the next frame, the write operation must be completed after the leading edge of FV and before the trailing edge of FV. As a special case, in Snapshot modes (see "Operating Modes" on page 41), register writes that occur after FV but before the next trigger will take effect immediately on the next frame, as if there had been a Restart. However, if the trigger for the next frame in ERS Snapshot mode occurs during FV, register writes take effect as with continuous mode. Additional control over the timing of register updates can be achieved by using synchronize_changes. If this bit is set, writes to certain register fields that affect the brightness of the output image do not take effect immediately. Instead, the new value is remembered internally. When synchronize_changes is cleared, all the updates simultaneously take effect on the next frame (as if they had all been written the instant synchronize_changes was cleared). Register fields affected by this bit are identified in Table 13: Register Description on page 20. Fields not identified as being frame-synchronized or affected by synchronize_changes are updated immediately after the register write is completed. The effect of these registers on the next frame can be difficult to predict if they affect the shutter pointer. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 38 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Restart To restart the MT9P401 at any time during the operation of the sensor, write a "1" to the restart register (R0x0B[0] = 1). This has two effects: first, the current frame is interrupted immediately. Second, any writes to frame-synchronized registers and the shutter width registers take effect immediately, and a new frame starts (in continuous mode). Register updates being held by synchronize_changes do not take effect until that bit is cleared. The current row and one following row complete before the new frame is started, so the time between issuing the Restart and the beginning of the next frame can vary by about tROW. If Pause_Restart is set, rather than immediately beginning the next frame after a restart in continuous mode, the sensor pauses at the beginning of the next frame until Pause_Restart is cleared. This can be used to achieve a deterministic time period from clearing the Pause_Restart bit to the beginning of the first frame, meaning that the controller does not need to be tightly synchronized to LV or FV. Note: PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN When Pause_Restart is cleared, be sure to leave Restart set to "1" for proper operation. The Restart bit will be cleared automatically by the device. 39 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Image Acquisition Modes The MT9P401 supports two image acquisition modes (Shutter Types) (see "Operating Modes" on page 41), electronic rolling shutter and global reset release. Electronic Rolling Shutter The ERS modes take pictures by scanning the rows of the sensor twice in the order described in "Full-Array Readout" on page 32. On the first scan, each row is released from reset, starting the exposure. On the second scan, the row is sampled, processed, and returned to the reset state. The exposure for any row is therefore the time between the first and second scans. Each row is exposed for the same duration, but at slightly different point in time, which can cause a shear in moving subjects. Whenever the mode is changed to an ERS mode (even from another ERS mode), and before the first frame following reset, there is an anti-blooming sequence where all rows are placed in reset. This sequence must complete before continuous readout begins. This delay is: t ALLRESET = 16 x 2004 x tACLK Global Reset Release The GRR modes attempt to address the shearing effect by starting all rows' exposures at the same time. Instead of the first scan used in ERS mode, the reset to each row is released simultaneously. The second scan occurs as normal, so the exposure time for each row would different. Typically, an external mechanical shutter would be used to stop the exposure of all rows simultaneously. In GRR modes, there is a startup overhead before each frame as all rows are initially placed in the reset state (tALLRESET). Unlike ERS mode, this delay always occurs before each frame. However, it occurs as soon as possible after the preceding frame, so typically the time from trigger to the start of exposure does not include this delay. To ensure that this is the case, the first trigger must occur no sooner than tALLRESET after the previous frame is read out. Exposure The nominal exposure time, tEXP, is the effective shutter time in ERS modes, and is defined by the shutter width, SW, and the shutter overhead, SO, which includes the effect of Shutter_Delay. Exposure time for other modes is defined relative to this time. Increasing Shutter_Delay (SD) decreases the exposure time. Exposure times are typically specified in units of row time, although it is possible to fine-tune exposures in units of tACLKs (where tACLK is 2 * tPIXCLK). tEXP = SW x tROW - SO x 2 x tPIXCLK where: SW = max(1, (2 * 16 x Shutter_Width_Upper) + Shutter_Width_Lower) SO = 208 x (Row_Bin + 1) + 98 + min(SD, SDmax) - 94 SD = Shutter_Delay + 1 SDmax = 1232; if SW < 3 1504, otherwise PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 40 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features The exposure time is calculated by determining the reset time of each pixel row (with time 0 being the start of the first row time), and subtracting it from the sample time. Under normal conditions in ERS modes, every pixel should end up with the same exposure time. In global shutter release modes, or in row binning modes, the exposure times of individual pixels can vary. In global shutter release modes (described later) exposure time starts simultaneously for all rows, but still ends as defined above. In a real system, the exposure would be stopped by a mechanical shutter, which would effectively stop the exposure to all rows simultaneously. Because this specification does not consider the effect of an external shutter, each output row's exposure time will differ by tROW from the previous row. Global shutter modes also introduce a constant added to the shutter time for each row, because the exposure starts during the global shutter sequence, and not during any row's shutter sequence. For each additional row in a row bin, this offset will increase by the length of the shutter sequence. In Bulb_Exposure modes (also detailed later), the exposure time is determined by the width of the TRIGGER pulse rather than the shutter width registers. In ERS bulb mode, it is still a multiple of row times, and the shutter overhead equation still applies. In GRR bulb mode, the exposure time is granular to ACLKs, and shutter overhead (and thus Shutter_Delay) has no effect. Operating Modes In the default operating mode, the MT9P401 continuously samples and outputs frames. It can be put in "snapshot" or triggered mode by setting snapshot, which means that it samples and outputs a frame only when triggered. To leave snapshot mode, it is necessary to first clear Snapshot then issue a restart. When in snapshot mode, the sensor can use the ERS or the GRR. The exposure can be controlled as normal, with the Shutter_Width_Lower and Shutter_Width_Upper registers, or it can be controlled using the external TRIGGER signal. The various operating modes are summarized in Table 15. Table 15: Operating Modes Mode Settings Description ERS Continuous Default ERS Snapshot Snapshot = 1 ERS Bulb Snapshot = 1; Bulb_Exposure = 1 Snapshot = 1; Global_Reset = 1 Snapshot = 1; Bulb_Exposure = 1; Global_Reset = 1 Frames are output continuously at the frame rate defined by tFRAME. ERS is used, and the exposure time is electronically controlled to be tEXP. Frames are output one at a time, with each frame initiated by a trigger. ERS is used, and the exposure time is electronically controlled to be tEXP. Frames are output one at a time, with each frame's exposure initiated by a trigger. ERS is used. End of exposure and readout are initiated by a second trigger. Frames are output one at a time, with each frame initiated by a trigger. GRR is used. Readout is electronically triggered based on SW. Frames are output one at a time, with each frame initiated by a trigger. GRR is used. Readout is initiated by a second trigger. GRR Snapshot GRR Bulb Note: In ERS bulb mode, SW must be greater than 4 (use trigger wider than tROW * 4). All operating modes share a common set of operations: 1. Wait for the first trigger, then start the exposure. 2. Wait for the second trigger, then start the readout. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 41 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features The first trigger is by default automatic, producing continuous images. If snapshot is set, the first trigger can either be a low level on the TRIGGER pin or writing a "1" to the trigger register field. If Invert_Trigger is set, the first trigger is a high level on TRIGGER pin (or a "1" written to trigger register field). Because TRIGGER is level-sensitive, multiple frames can be output (with a frame rate of tFRAME) by holding TRIGGER pin at the triggering level. The second trigger is also normally automatic, and generally occurs SW row times after the exposure is started. If Bulb_Exposure is set, the second trigger can either be a high level on TRIGGER or a write to Restart. If Invert_Trigger is set, the second trigger is a low level on TRIGGER (or a Restart). In bulb modes, the minimum possible exposure time depends on the mechanical shutter used. After one frame has been output, the chip will reset step 1, above, eventually waiting for the first trigger again. The next trigger may be issued after ((VB - 8) x tROW) in ERS modes or tALLREST in GRR modes. The choice of shutter type is made by Global_Reset. If it is set, the GRR shutter is used; otherwise, ERS is used. The two shutters are described in "Electronic Rolling Shutter" on page 40 and "Global Reset Release" on page 40. The default ERS continuous mode is shown in Figure 8 on page 8. Figure 23 shows default signal timing for ERS snapshot modes, while Figure 24 on page 43 shows default signal timing for GRR snapshot modes. Figure 23: ERS Snapshot Timing TT1 TSE TSW TT2 SW x tROW TRIGGER 8 x tROW (H + VB) x tROW STROBE FV LV DOUT 8 x tROW tROW First Row Exposure tROW (a) ERS Snapshot Second Row Exposure TT1 TSE TSW TT2 SW x tROW TRIGGER 8 x tROW (H + VB) x tROW STROBE FV LV DOUT 8 x tROW tROW (b) ERS Bulb PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN First Row Exposure 42 tROW Second Row Exposure . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Figure 24: GRR Snapshot Timing TSW TT2 TSE TT1 SW x tROW + 2000 x tACLK TRIGGER VB x tROW + 2000 x tACLK STROBE 8 x tROW FV LV DOUT tROW First Row Exposure (a) GRR Snapshot Second Row Exposure TT1 TSE TSW TT2 SW x tROW + 2000 x tACLK TRIGGER 8 x tROW VB x tROW + 2000 x tACLK STROBE FV LV DOUT tROW First Row Exposure (b) GRR Bulb Second Row Exposure Strobe Control To support synchronization of the exposure with external events such as a flash or mechanical shutter, the MT9P401 produces a STROBE output. By default, this signal is asserted for approximately the time that all rows are simultaneously exposing, minus the vertical blanking time, as shown in Figure 23 on page 42 and Figure 24. Also indicated in these figures are the leading and trailing edges of STROBE, which an be configured to occur at one of several timepoints. The leading edge of STROBE occurs at STROBE_Start, and the trailing edge at STROBE_End, which are set to codes described in Table 16. Table 16: STROBE Timepoints Symbol TT1 TSE TSW TT2 Timepoint Code Trigger 1 (start of shutter scan) Start of exposure (all rows simultaneously exposing) offset by VB End of shutter width (expiration of the internal shutter width counter) Trigger 2 (start of readout scan) - 1 2 3 If STROBE_Start and STROBE_End are set to the same timepoint, the strobe is a tROW wide pulse starting at the STROBE_Start timepoint. If the settings are such that the strobe would occur after the trailing edge of FV, the strobe may be only tACKL wide; however, because there is no concept of a row at that time. The sense of the STROBE PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 43 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features signal can be inverted by setting Invert_Strobe (R0x1E[5] = 1. To use strobe as a flash in snapshot modes or with mechanical shutter, set the Strobe_Enable register bit field R0x1E[4] = 1. Signal Chain and Datapath The signal chain and datapath are shown in Figure 25. Each color is processed independently, including separate gain and offset settings. Voltages sampled from the pixel array are first passed through an analog gain stage, which can produce gain factors between 1 and 8. An analog offset is then applied, and the signal is sent through a 12-bit analog-todigital converter. In the digital space, a digital gain factor of between 1 and 16 is applied, and then a digital offset of between -2048 and 2047 is added. The resulting 12-bit pixel value is then output on the DOUT[11:0] ports. The analog offset applied is determined automatically by the black level calibration algorithm, which attempts to shift the output of the analog signal chain so that black is at a particular level. The digital offset is a fine-tuning of the analog offset. Figure 25: Signal Path Analog Signal Chain Pixel Voltage Analog Gain Analog Offset X + Digital Datapath Digital Offset Correction Black Level Calibration X ADC + DOUT[11:0] Digital Gain Gain There are two types of gain supported: analog gain and digital gain. Combined, gains of between 1 and 128 are possible. The recommended gain settings are shown in Table 17. Table 17: Gain Increment Settings Gain Range Increments Digital Gain Analog Multipier Analog Gain 1- 4 4.25-8 9-128 0.125 0.25 1 0 0 1-120 0 1 1 8-32 17-32 32 Note: Analog gain should be maximized before applying digital gain. The combined gain for a color C is given by: GC = AGC x DGC. Analog Gain The analog gain is specified independently for each color channel. There are two components, the gain and the multiplier. The gain is specified by Green1_Analog_Gain, Red_Analog_Gain, Blue_Analog_Gain, and Green2_Analog_Gain in steps of 0.125. The PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 44 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features analog multiplier is specified by Green1_Analog_Multiplier, Red_Analog_Multiplier, Blue_Analog_Multiplier, and Green2_Analog_Multiplier. These combine to form the analog gain for a given color C as shown in this equation: AGC = (1 + C_Analog_Multiplier) x (C_Analog_Gain / 8) The gain component can range from 0 to 7.875 in steps of 0.125, and the multiplier component can be either 0 or 1 (resulting in a multiplier of 1 or 2). However, it is best to keep the "gain" component between 1 and 4 for the best noise performance, and use the multiplier for gains between 4 and 8. Digital Gain The digital gain is specified independently for each color channel in steps of 0.125. It is controlled by the register fields Green1_Digital_Gain, Red_Digital_Gain, Blue_Digital_Gain, and Green2_Digital_Gain. The digital gain for a color C is given by: DGC = 1 + (C_Digital_Gain / 8) Offset The MT9P401 sensor can apply an offset or shift to the image data in a number of ways. An analog offset can be applied on a color-wise basis to the pixel voltage as it enters the ADC. This makes it possible to adjust for offset introduced in the pixel sampling and gain stages to be removed, centering the resulting voltage swing in the ADC's range. This offset can be automatically determined by the sensor using the automatic black level calibration (BLC) circuit, or it can be set manually by the user. It is a fairly coarse adjustment, with adjustment step sizes of 4 to 8 LSBs. Digital offset is also added on a color-wise and line-wise basis to fine tune the black level of the output image. This offset is based on an average black level taken from each row's dark columns, and is automatically determined by the digital row-wise black level calibration (RBLC) circuit. If the RBLC circuit is not used, a user defined offset can be applied instead. This offset has a resolution of 1 LSB. A digital offset is added on a color-wise basis to account for channel offsets that can be introduced due to "even" and "odd" pixels of the same color going through a slightly different ADC chain. This offset is automatically determined based on dark row data, but it can also be manually set. Analog Black Level Calibration The MT9P401 black level calibration circuitry provides a feedback control system since adjustments to the analog offset are imprecise by nature. The goal is that within the dark row region of any supported output image size, the offset should have been adjusted such that the average black level falls within the specified target thresholds. The analog offsets normally need a major adjustment only when leaving the Reset state or when there has been a change to a color's analog gain. Factors like shutter width and temperature have lower-order impact, and generally only require a minor adjustment to the analog offsets. The MT9P401 has various calibration modes to keep the system stable while still supporting the need for rapid offset adjustments when necessary. The two basic steps of black level calibration are: 1. Take a sample. 2. If necessary, adjust the analog offset. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 45 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Black level calibration is normally done separately for each color channel, and different channels can be using different sample or adjustment methods at the same time. However, because both Green1 and Green2 pixels go through the same signal chain, and Red and Blue pixels likewise go through the same signal chain, it is expected that the chosen offset for these pairs should be the same as long as the gains are the same. If Lock_Green_Calibration is set, and (Green1_Analog_Gain = Green2_Analog_Gain) and (Green1_Analog_Multiplier = Green2_Analog_Multiplier), the calculated or user-specified Green1_Offset is used for both green channels. Similarly, if Lock_Red/ Blue_Calibration is set, and (Red_Analog_Gain = Blue_Analog_Gain) and (Red_Analog_Multiplier = Blue_Analog_Multiplier), the calculated or user-specified Red_Offset is used for both the red and blue channels. The current values of the offsets can be read from the Green1_Offset, Red_Offset, Blue_Offset, and Green2_Offset registers. Writes to these registers when Manual_BLC is set change the offsets being used. In automatic BLC mode, writes to these registers are effective when manual mode is re-entered. In Manual_BLC mode, no sampling or adjusting takes place for any color. Digital Black Level Calibration Digital black level calibration is the final calculation applied to pixel data before it is output. It provides a precise black level to complement the coarser-grained analog black level calibration, and also corrects for black level shift introduced by digital gain. This correction applies to the active columns for all rows, including dark rows. Test Patterns The MT9P401 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are enabled when Enable_Test_Pattern is set. Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 18. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green for green pixels, Test_Pattern_Blue for blue pixels, and Test_Pattern_Red for red pixels. Table 18: Test Pattern Modes PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Test_Pattern_Mode Test Pattern Output 0 1 2 3 4 5 6 7 8 Color field (normal operation) Horizontal gradient Vertical gradient Diagonal gradient Classic test pattern Walking 1s Monochrome horizontal bars Monochrome vertical bars Vertical color bars 46 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Features Classic Test Pattern When selected, a value from Test_Data will be sent through the digital pipeline instead of sampled data from the sensor. The value will alternate between Test_Data for even and odd columns. Color Field When selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When selected, a typical color bar pattern will be sent through the digital pipeline. Horizontal Gradient When selected, a horizontal gradient will be produced based on a counter which increments on every active pixel. Vertical Gradient When selected, a vertical gradient will be produced based on a counter which increments on every active row. Diagonal Gradient When selected, a diagonal gradient will be produced based on the counter used by the horizontal and vertical gradients. Walking 1s When selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. Monochrome Vertical Bars When selected, vertical monochrome bars will be sent through the digital pipeline. The width of each bar can be set in Test_Pattern_Bar_Width and the intensity of each bar is set by Test_Pattern_Green for even bars and Test_Pattern_Blue for odd bars. Monochrome Horizontal Bars When selected, horizontal monochrome bars will be sent through the digital pipeline. The width of each bar can be set in Test_Pattern_Bar_Width and the intensity of each bar is set by Test_Pattern_Green for even bars and Test_Pattern_Blue for odd bars. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 47 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 26: Typical Spectral Characteristics Quantum Efficiency vs. Wavelength 50 Quantum Efficiency (%) G B 45 R 40 35 30 25 20 15 10 5 0 350 400 450 500 550 600 650 700 750 Wavelength (nm) Figure 27: CRA vs. Image Height (7 deg) Image Height CRA vs. Image Height Plot CRA Design 14 12 CRA (deg) 10 8 6 4 2 0 0 10 20 30 40 50 60 70 80 Image Height (%) PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 48 90 100 110 (%) (mm) CRA (Deg) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 0 0.178 0.356 0.535 0.713 0.891 1.069 1.247 1.426 1.604 1.782 1.960 2.138 2.317 2.495 2.673 2.851 3.029 3.208 3.386 3.564 0 0.35 0.70 1.05 1.40 1.75 2.10 2.45 2.80 3.15 3.50 3.85 4.20 4.55 4.90 5.25 5.60 5.95 6.30 6.65 7.00 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Electrical Specifications Electrical Specifications Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 29 and Table 19 on page 49. Figure 29: Two-Wire Serial Bus Timing Parameters tr_clk SCLK t SRTH t SDH t SCLK t SDS t SHAW tf_clk tr_sdat tf_sdat 90% 90% 10% 10% t AHSW t STPS t STPH S DATA Write Address Bit 7 Write Address Bit 0 Register Address Bit 7 Write Start Register Value Bit 0 ACK t AHSR t SHAR SCLK Stop t SDHR t SDSR S DATA Read Address Bit 7 Read Address Bit 0 Read Start Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Two-Wire Serial Bus Characteristics Symbol Definition fSCLK Serial interface input clock frequency Serial Input clock period SCLK duty cycle SCLK rise time SCLK fall time SDATA rise time SDATA fall time Start hold time SDATA hold SDATA setup SDATA hold to ACK ACK hold to SDATA Stop setup time Stop hold time SDATA hold to ACK ACK hold to SDATA SDATA hold SDATA setup Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor tSCLK tr_sclk tf_sclk tr_sdat tf_sdat t SRTH tSDH t SDS t SHAW tAHSW t STPS t STPH tSHAR t AHSR tSDHR tSDSR CIN_SI CLOAD_SD RSD Register Value Bit 0 ACK Note: Table 19: Register Value Bit 7 PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Condition Min Typ Max Unit - - - - - 40 - - - - 0 0 0 279 279 0 0 279 279 0 0 - - - - - 50 34 8 34 10 10 0 19.9 281 281 0 0 284 284 0 19.9 3.5 15 1.5 400 2.5 60 - - - - 28 0 59.9 300 300 0 0 300 300 0 59.9 - - - kHz sec % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF k WRITE/READ WRITE WRITE WRITE WRITE WRITE/READ WRITE/READ READ READ READ READ - - - 49 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Electrical Specifications I/O Timing By default, the MT9P401launches pixel data, FV and LV with the rising edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV and LV using the falling edge of PIXCLK. See Figure 30 and Table 20 for I/O timing (AC) characteristics. Figure 30: I/O Timing Diagram tR t RP tF t FP 90% 90% 10% 10% t EXTCLK EXTCLK t CP PIXCLK t PD t PD Data[7:0] Pxl _ 0 Pxl _ 1 Pxl _ 2 Pxl _ n t PFH t PFL t PLH FRAME_VALID/ LINE_VALID t PLL FRAME_VALID trails LINE_VALID by 16 PIXCLKs. FRAME_VALID leads LINE_VALID by 609 PIXCLKs. *PLL disabled for tCP Table 20: I/O Timing Characteristics Symbol Definition fEXTCLK1 Input clock frequency Input clock period Input clock frequency Input clock period Input clock rise time Input clock fall time Pixclk rise time Pixclk fall time Clock duty cycle Jitter on PIXCLK Input clock jitter 48 MHz Input clock jitter 96 MHz EXTCLK to PIXCLK propagation delay PIXCLK frequency PIXCLK to data valid PIXCLK to FV HIGH PIXCLK to LV HIGH PIXCLK to FV LOW PIXCLK to LV LOW tEXTCLK1 fEXTCLK2 tEXTCLK2 tR tF t RP tFP t (PIX JITTER) tJITTER1 tJITTER2 t CP fPIXCLK tPD tPFH tPLH tPFL tPLL PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Condition Min Typ Max Unit PLL enabled PLL enabled PLL disabled PLL disabled 6 166 6 125 0.03 0.03 0.03 0.03 40 - - - 11.5 6 0.8 2.8 2.2 2.4 2.6 - - - - - - - - 50 - 300 220 17.7 - 2.1 4.3 3.5 4.2 4.1 27 37 96 10.4 1 1 1 1 60 1.03 - - 19.1 96 3.9 5.9 5.9 5.9 5.9 MHz ns MHz ns V/ns V/ns V/ns V/ns % ns ps ps ns MHz ns ns ns ns ns Nominal voltages Default Default Default Default Default Default 50 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Electrical Specifications Table 20: I/O Timing Characteristics (continued) Symbol Definition CLOAD CIN Output load capacitance Input pin capacitance PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Condition 51 Min Typ Max Unit - - <10 2.5 - - pF pF . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in Table 21, Table 22 on page 53, and Table 23 on page 53. Table 21: DC Electrical Characteristics Symbol Definition VDD VDD_IO VAA VAA_PIX VDD_PLL VIH Core digital voltage I/O digital voltage Analog voltage Pixel supply voltage PLL supply voltage Input HIGH voltage VIL Input LOW voltage IIN VOH Input leakage current Output HIGH voltage VOL Output LOW voltage IOH Output HIGH current IOL IOZ IDD1 Output LOW current Tri-state output leakage current Digital operating current IDD_IO1 I/O digital operating current IAA1 Analog operating current IAA_PIX1 Pixel supply current IDD_PLL1 PLL supply current IDD2 Digital operating current IDD_IO2 I/O digital operating current IAA2 Analog operating current IAA_PIX2 Pixel supply current IDD_PLL2 PLL supply current ISTBY1 ISTBY2 ISTBY3 ISTBY4 Hard standby current PLL enabled Hard standby current PLL disabled Soft standby current PLL enabled Soft standby current PLL disabled PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Condition VDD_IO = 2.8V VDD_IO = 1.8V VDD_IO = 2.8V VDD_IO = 1.8V No pull-up resistor; VIN = VDD_IO or DGND VDD_IO = 1.8V VDD_IO = 2.8V VDD_IO = 2.8V VDD_IO = 2.8V At specified VOH = VDD_IO - 400mv at 1.7V VDD_IO At specified VOL = 400mv at 1.7V VDD_IO VIN = VDD_IO or GND Parallel mode 96 MHz full frame nominal voltage, PLL enabled Parallel mode 96 MHz full frame nominal voltage, PLL enabled Parallel mode 96 MHz full frame nominal voltage, PLL enabled Parallel mode 96 MHz full frame nominal voltage, PLL enabled Parallel mode 96 MHz full frame nominal voltage, PLL enabled Parallel mode 96 MHz 4X binning nominal voltage, PLL enabled Parallel mode 96 MHz 4X binning nominal voltage, PLL enabled Parallel mode 96 MHz 4X binning nominal voltage, PLL enabled Parallel mode 96 MHz 4X binning nominal voltage, PLL Enabled Parallel mode 96 MHz 4X binning nominal voltage, PLL enabled EXTCLK enabled EXTCLK disabled EXTCLK enabled (PLL enabled) EXTCLK enabled (PLL disabled) 52 Min Typ Max Unit 1.7 1.7 2.6 2.6 2.6 2 1.3 -0.3 -0.3 - 1.3 1.9 0.16 - 8.9 1.8 1.8/2.8 2.8 2.8 2.8 - - - - <10 - - - - - 1.9 3.1 3.1 3.1 3.1 3.3 2.3 0.8 0.5 - 1.82 - 0.35 0.6 22.3 V V V V V V V V V A V V V V mA 2.6 - - - - 28 5.1 2 35 mA A mA - 38.6 50 mA - 72 80 mA - 2.4 6 mA - 5 6 mA - 15 35 mA - 6.4 50 mA - 69 80 mA - 3.4 6 mA - 5 6 mA - - - - <500 <50 <500 <500 - - - - A A A A . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Electrical Specifications Table 22: Power Consumption Mode Full Resolution (15 fps) 4X Binning Unit Streaming 381 262 mW Caution Table 23: Stresses greater than those listed in Table 23 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Definition VDD_MAX VDD_IO_MAX VAA_MAX VAA_PIX_MAX VDD_PLL_MAX VIN_MAX IDD_MAX IDD_IO_MAX IAA_MAX IAA_PIX_MAX IDD_PLL_MAX TOP TST Core digital voltage I/O digital voltage Analog voltage Pixel supply voltage PLL supply voltage Input voltage Digital operating current I/O digital operating current Analog operating current Pixel supply current PLL supply current Operating temperature Storage temperature Notes: PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN Condition Measure at junction Min Max Unit -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - - - - - -30 -40 1.9 3.1 3.1 3.1 3.1 3.4 35 100 95 6 6 70 125 V V V V V V mA mA mA mA mA C C 1. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. To keep dark current and shot noise artifacts from impacting image quality, care should be taken to keep TOP at a minimum. 53 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Package Dimensions Package Dimensions Figure 31: 48-Pin iLCC Package Outline Drawing D 1.250 0.125 SEATING PLANE A 0.725 0.075 0.525 0.050 0.70 TYP 47X 0.80 7.57 1.455 0.125 (FOR REFERENCE ONLY) 7.70 1.40 C B 5.702 CTR FIRST CLEAR PIXEL 48 1 48X 0.40 1.45 5.000 0.075 OPTICAL CENTER 4.50 4.20 10.000 0.075 CL 7.70 4.277 7.02 CTR 0.70 TYP 3.85 OPTICAL 5.000 0.075 AREA OPTICAL CENTER MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES B AND C : 1 MAXIMUM TILT OF OPTICAL AREA RELATIVE TO SEATING PLANE A : 25 MICRONS RELATIVE TO TOP OF COVER GLASS D : 50 MICRONS CL 4.50 3.85 10.000 0.075 LEAD FINISH: GOLD PLATING, 0.50 MICRONS MINIMUM THICKNESS SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS IMAGE SENSOR DIE Notes: PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 1. All dimensions in millimeters.. 54 . (c)2007 Aptina Imaging Corporation. All rights reserved. Aptina Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor Revision History Revision History Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/22/11 * Updated to Aptina new template * Fixed part number and logo in header Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/28/10 * Updated to Aptina template Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .08/01/07 * Update VDDQ to VDD_IO * Update RESET# to RESET_BAR * Update STANDBY# to STANDBY_BAR * Update OE# to OE * Update Table 13, "Register Description," on page 20 (R255) * Update Table 20, "I/O Timing Characteristics," on page 50 * Update Table 21, "DC Electrical Characteristics," on page 52 * Update Table 23, "Absolute Maximum Ratings," on page 53 Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/07 * Initial release 10 Eunos Road 8 13-40, Singapore Post Center, Singapore 408600 prodmktg@aptina.com www.aptina.com Aptina, Aptina Imaging, and the Aptina logo are the property of Aptina Imaging Corporation All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 5810501876/Source: 4356288587 MT9P401_DS - Rev. D Pub. 3/11 EN 55 . (c)2007 Aptina Imaging Corporation All rights reserved.