Rev. 1.3 February 2009 www.aosmd.com Page 1 of 16
AOZ1092D
EZBuck™ 3A Simple Buck Regulator
General Description
The AOZ1092D is a high efficiency, simple to use, 3A
buck regulator. The AOZ1092D works from a 4.5V to 16V
input voltage range, and provides up to 3A of
continuous output current with an output voltage
adjustable down to 0.8V.
The AOZ1092D comes in 4x5 DFN-8 packages and is
rated over a -40°C to +85°C ambient temperature range.
Features
●4.5V to 16V operating input voltage range
●50mΩ internal PFET switch for high efficiency:
up to 95%
●Schottky diode is included
●Internal soft start
●Output voltage adjustable to 0.8V
●3A continuous output current
●Fixed 500kHz PWM operation
●Cycle-by-cycle current limit
●Short-circuit protection
●Output over voltage protection
●Thermal shutdown
●Small size 4x5 DFN-8 packages
Applications
●Point of load DC/DC conversion
●PCIe graphics cards
●Set top boxes
●DVD drives and HDD
●LCD panels
●Cable modems
●Telecom/networking/datacom equipment
Typical Application
Figure 1. 3.3V/3A Non-Synchronous Buck Regulator
LX
VIN
U1
VIN
FB
GND
EN
COMP
AGND
C1
22µF
Ceramic
C5
C2, C3
22µF
Ceramic
VOUT
3.3V
R1
R2
L1
4.7µH
AOZ1092D
RC
CC
Not Recommended For New Designs
No Replacement
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 2 of 16
Ordering Information
All AOS Products are offering in packaging with Pb-free plating and compliant to RoHS standards.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1092DI -40°C to +85°C DFN-8 4x5 RoHS
Pin Number Pin Name Pin Function
1V
IN Supply voltage input. When VIN rises above the UVLO threshold the device starts up.
2 PGND Power ground. Electrically needs to be connected to AGND.
3 AGND Reference connection for controller section. Also used as thermal connection for controller section.
Electrically needs to be connected to PGND.
4 FB The FB pin is used to determine the output voltage via a resistor divider between the output and
GND.
5 COMP External loop compensation pin.
6 EN The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN pin floating.
7, 8 LX PWM output connection to inductor. Thermal connection for output stage.
VIN
PGND
AGND
FB
LX
LX
EN
COMP
4x5 DFN
(Top View)
1
2
3
4
8
7
6
5
GND
LX
Not Recommended For New Designs
Rev. 1.3 February 2009 www.aosmd.com Page 3 of 16
AOZ1092D
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the
device.
Recommend Operating Ratings
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
500kHz/63kHz
Oscillator
AGND PGND
VIN
EN
FB
COMP
LX
OTP
Internal
+5V
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
Softstart
Reference
& Bias
0.8V
Q1
D1
PWM
Comp
Level
Shifter
+
FET
Driver
ISen
EAmp
0.2V
+
–
+
–
+
–
+
–
+
0.96V +
–
Frequency
Foldback
Comparator
Over Voltage
Protection
Comparator
Parameter Rating
Supply Voltage (VIN) 18V
LX to AGND -0.7V to VIN+0.3V
EN to AGND -0.3V to VIN+0.3V
FB to AGND -0.3V to 6V
COMP to AGND -0.3V to 6V
PGND to AGND -0.3V to 0.3V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
Parameter Rating
Supply Voltage (VIN) 4.5V to 16V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Thermal Resistance
DFN 4x5 (ΘJA)53°C/W
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 4 of 16
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.(3)
Note:
3. Specifications in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 16 V
VUVLO Input Under-Voltage Lockout Threshold VIN Rising
VIN Falling
4.00
3.70 V
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 1.2V 23mA
IOFF Shutdown Supply Current VEN = 0V 110µA
VFB Feedback Voltage 0.782 0.8 0.818 V
Load Regulation 0.5 %
Line Regulation 0.5 %
IFB Feedback Voltage Input Current 200 nA
ENABLE
VEN EN Input Threshold Off Threshold
On Threshold 2.0
0.6 V
VHYS EN Input Hysteresis 100 mV
MODULATOR
fOFrequency 400 500 600 kHz
DMAX Maximum Duty Cycle 100 %
DMIN Minimum Duty Cycle 6%
GVEA Error Amplifier Voltage Gain 500 V / V
GEA Error Amplifier T r ansconductance 200 µA / V
PROTECTION
ILIM Current Limit 4 5 A
VPR Output Over-Voltage Protection Threshold Off Threshold
On Threshold 960
840 mV
TJOver-Temperature Shutdown Limit 150 °C
tSS Soft Start Interval 2.2 ms
OUTPUT STAGE
High-Side Switch On-Resistance VIN = 12V
VIN = 5V 40
65 50
85 mΩ
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 5 of 16
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Startup to Full Load Full Load to Turn Off
50% to 100% Load Transient No Load to Turn Off
1μs/div1μs/div
400μs/div1ms/div
100
μ
s/div1s/div
Vin ripple
50mV/div
Vo ripple
50mV/div
Vo
2V/div
Vin
5V/div
lin
1A/div
Vo
1V/div
Vin
5V/div
lin
1A/div
Vo
1V/div
Vin
5V/div
lin
1A/div
Vo Ripple
0.1V/div
lo
2A/div
IL
2A/div
VLX
10V/div
Vin ripple
0.1V/div
Vo ripple
50mV/div
IL
2A/div
VLX
10V/div
Light Load (DCM) Operation Full Load (CCM) Operation
Not Recommended For New Designs
Rev. 1.3 February 2009 www.aosmd.com Page 6 of 16
AOZ1092D
Typical Performance Characteristics (Continued)
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Efficiency
Thermal Derating Curves
Thermal derating curves for 4x5 DFN-8 package part under typical line and output voltage condition based on
EVAL board. Circuit of Figure 1. 25°C ambient temperature and natural convection (air speed <50LFM) unless
otherwise specified.
100μs/div1ms/div
Vo
2V/div
IL
2A/div
Vo
2V/div
IL
2A/div
Short Circuit Protection Short Circuit Recovery
Efficiency (VIN = 12V) vs. Load Current
75
80
85
90
95
5.0V OUTPUT
3.3V OUTPUT
8.0V OUTPUT
100
00.5 1.0 1.5 2.0 2.5 3.0
Load Current (A)
Efficieny (%)
Derating Curve at 5V/6V Input
5.0V OUTPUT
1.8V
OUTPUT
3.3V
OUTPUT
Ambient Temperature (T
A)
Output Current (IO)
3.5
3.0
2.5
2.0
1.5
1.0
25 35 45 55 65 75 85
Derating Curve at 12 Input
1.8V OUTPUT
8.0V OUTPUT
Ambient Temperature (T
A)
Output Current (IO)
3.5
3.0
2.5
2.0
1.5
1.0
25 35 45 55 65 75 85
3.3V
OUTPUT5.0V
OUTPUT
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 7 of 16
Detailed Description
The AOZ1092D is a current-mode step down regulator
with integrated high side PMOS switch and low side
Schottky diode. It operates from a 4.5V to 16V input
voltage range and supplies up to 3A of load current. The
duty cycle can be adjusted from 6% to 100% allowing a
wide range of output voltage. Features include enable
control, Power-On Reset, input under voltage lockout,
fixed internal soft-start and thermal shut down.
The AOZ1092D is available in 4x5 DFN-8 package.
Enable and Soft Start
The AOZ1092D has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.0V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to r egulation voltage in typically 2.2ms.
The 2.2ms soft start time is set internally.
The EN pin of the AOZ1092D is active high. Con nect the
EN pin to VIN if enable function is not used. Pull it to
ground will disable the AOZ1092D. Do not leave it open.
The volt age on EN pin must be above 2.0 V to enable the
AOZ1092D. When voltage on EN pin falls below 0.6V,
the AOZ1092D is disabled.
Steady-State Operation
Under steady-state conditions, the converter operates
in fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1092D in tegrates a n inter nal P-MOSFET as the
high-side switch. In ductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the inp ut through the in ductor
to the output. When the current signal exceeds the error
voltage, the high -side switch is off. The inductor cu rrent is
freewheeling thr o ug h th e inte r na l Scho ttky diode to
output.
The AOZ1092D us es a P-Cha n nel MOS FET as th e hig h
side switch. It saves the bootstrap capacitor normally
seen in a circuit which is using an NMOS switch. It allows
100% turn-on of the upper switch to achieve linear regu-
lation mode of operation . The minimum voltage drop from
VIN to VO is the load current times DC resistance of
MOSFET plus DC resistance of buck inductor. It can be
calculated by equation below:
where;
VO_MAX is the maximum output voltage,
VIN is the input voltage from 4.5V to 16V,
IO is the output current from 0A to 3A,
RDS(ON) is the on resi stance of internal MOSFET, the value is
between 40mΩ and 70mΩ depen ding on input voltage and
junction temperature, and
Rinductor is the inductor DC resistance.
Switching Frequency
The AOZ1092D switching frequency is fixed and set by
an internal oscillator. The practical switching frequency
could range from 400kHz to 600kHz due to device
variation.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
Some standard value of R1, R2 and most common ly used
output voltage values are listed in Table 1.
The combination of R1 and R2 shou ld be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
VO (V) R1 (kΩ) R2 (kΩ)
0.8 1.0 open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.1 10
5.0 52.3 10
VO_MAX VIN IORDS ON()
Rinductor
+()×–=
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 8 of 16
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper PMOS and
inductor.
Protection Features
The AOZ1092D has multiple protection features to
prevent system circuit damage under abnormal
conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since AOZ1092D employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be betwee n 0.4V and 2.5V inte rnally.
The peak inductor current is automatically limited cycle
by cycle.
The cycle by cycle current limit threshold is set between
4A and 5A. When the load current reaches the current
limit threshold, the cycle by cycle current limit circuit turns
off the high side switch immediately to terminate the
current duty cycle. The inductor current stop rising. The
cycle by cycle current limit protection directly limits
inductor peak current. The average inductor current is
also limited due to the limita tion on peak inductor current.
When cycle by cycle current limit circuit is triggered, the
output voltage drops as the duty cycle decr ea sin g.
The AOZ1092D has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below
0.2V, the short circuit protection circuit is triggered. As a
result, the converter is shut down and hiccups at a
frequency equals to 1/8 of normal switching frequency.
The converter will start up via a soft start once the short
circuit condition dis ap p ea rs . In short circuit protection
mode, the inductor average current is greatly reduced
because of the low hic cu p fre q ue nc y.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4V, the converter st arts
operation. Wh en input voltage falls below 3.7V, the
converter will be shut down.
Output Over Voltage Protection (OVP)
The AOZ1092D monitors the fe edback voltage: when the
feedback voltage is higher than 960mV, it immediate
turns-off the PMOS to protect the output voltage
overshoot at fault condition. When feedback voltage is
lower than 840mV, the PMOS is allowed to turn on in the
next cycle.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shut s down the inter nal control circuit and
high side PMOS if the junction temperature exceeds
150ºC.
Application Information
The basic AOZ1092D application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input cap acitor must be conne cted to the VIN pin and
PGND pin of the AOZ1092D to maintain steady input
voltage and filter out the pulsing input current. The
voltage rating of input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concer n when selecting the cap acitor . For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
if let m equal the conversion ratio:
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
Figure 2. ICIN vs. Voltage Conversion Ratio
ΔVIN
IO
fC
IN
×
----------------- 1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IO
VO
VIN
---------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
I
CIN_RMS
(m)
I
O
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 9 of 16
For reliable operation and best performance, the input
capacitors must have cu rrent rating higher than I CIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used. When
selecting ceramic capacitors, X5R or X7R type dielectric
ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures are
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on indu ctor need s to be checke d for
thermal and efficiency requ ire m en ts.
Surface mount indu ctors in differ ent shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Table 2 lists some inductors for typical output voltage
design.
Table 2.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, ou tp ut ripp le vo ltage is deter m ine d by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where,
CO is output capacitor value, and
ESRCO is the equivalent series resistance of the output
capacitor.
When low ESR ceramic capacitor is used as output
capacitor , the imp edance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
ΔIL
VO
fL×
-----------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
VOUT L1 Manufacturer
5.0V Shi elded, 6. 8µ H
MSS1278-682MLD Coilcraft
Shielded, 6.8µH
MSS1260-682MLD
3.3V Un-shielded, 4.7µH
DO3316P-472MLD Coilcraft
Shielded, 4.7µH
DO1260-472NXD
Shielded, 3.3µH
ET553-3R3 ELYTONE
1.8V Shi elded, 2. 2µ H
ET553-2R2 ELYTONE
Un-shielded, 3.3µH
DO3316P-222MLD Coilcraft
Shielded, 2.2µH
MSS1260-222NXD
ΔVOΔILESRCO
1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL
1
8fC
O
××
-------------------------
⎝⎠
⎛⎞
×=
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 10 of 16
If the impedance of ESR at switching frequency
dominates, the output r ipple volt age is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as
output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
Usually, the ripple current rating of the output cap acitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
The AOZ1092D employs peak current mode control for
easy use and fast tr ansient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter clos e loo p tran sfe r func tio n to ge t de sired gain
and phase. Several different types of compensation
network can be used for the AOZ1 092D. For most cases,
a series capacitor and resistor network connected to the
COMP pin set s the pole-zero and is a dequate for a st able
high-bandwidth control loop.
In the AOZ1092D, FB pin and COMP pin are the invert-
ing input and the output of internal transconductance
error amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is cthe compensation capacitor.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. Th e system
crossover frequency is where con trol loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high because of system stability
concern. When designing the compensation loop,
converter stability under all line and load condition must
be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. The AOZ1092D
operates at a fixed switching frequency range from
400kHz to 600kHz. It is recommended to choose a
crossover frequency less than 50kHz.
The strategy for choosing RC and CC is to set the
cross over frequency with RC and set the compensator
zero with CC. Using selected crossover frequency, fC,
to calculate RC:
ΔVOΔILESRCO
×=
ICO_RMS
ΔIL
12
----------
=
fp1
1
2πCORL
××
-----------------------------------
=
fZ1
1
2πCOESRCO
××
------------------------------------------------
=
fp2
GEA
2πCCGVEA
××
-------------------------------------------
=
fZ2
1
2πCCRC
××
-----------------------------------
=
fC50kHz=
RCfC
VO
VFB
---------- 2πCO
×
GEA GCS
×
------------------------------
××=
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 11 of 16
where;
where fC is desired crossover frequency,
VFB is 0.8V,
G
EA
is the error amplifier transconductance, which is 200 x 10
-6
A/V , and
GCS is the current sense circuit transconductance, which is 6.86 A/V
The compensation capacitor CC and resistor RC to gether
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected cross-
over frequency. CC can is selected by:
The above equation can be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1092D buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the anode of Schottky
diode, to the cathode of Schottky diode. Current flows in
the second loop whe n th e low sid e dio de is on.
In PCB layout, minimizing the two loops area redu ces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ1092D.
In the AOZ1092D buck regulator circuit, th e major power
dissipating components are the AOZ1092D and output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
The power dissipation of inductor can be approximately
calculated by output current and DCR of the inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ1092D and thermal
impedance from junction to ambient.
The maximum junction temperature of AOZ1092D is
150ºC, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1092D under different ambient
temperature.
The thermal performance of the AOZ1092D is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 on the next page
illustrates a PCB layout example as reference.
1. Do not use thermal relief connection to the VIN
and the PGND pin. Pour a maximized coppe r area to
the PGND pin and the VIN pin to help thermal
dissipation.
2. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
3. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4. Make the curren t trac e from LX pins to L to Co to th e
PGND as short as possible .
5. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or VOUT.
6. The two LX pins are connected to internal PFET
drain. They are low resistance thermal conduction
path and most noisy switching node. Connected a
copper plane to LX pin to help thermal dissipation.
This copper plane should no t be too lar ger otherwise
switching noise may be coupled to other part of
circuit.
7. Keep sensitive signal trace far away form the LX
pins.
CC
1.5
2πRCfp1
××
-----------------------------------
=
CC
CORL
×
R3
---------------------
=
Ptotal_loss VIN IIN VOIO
×–×=
Pinductor_loss IO2Rinductor 1.1××=
Tamb
+
Tjunction Ptotal_loss Pinductor_loss
–()Θ×JA
=
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 12 of 16
Figure 3. AOZ1092D PCB Layout
LX
LXVin
PG
AG
FB
EN
CP
Cin
L
Cout
Thermal PAD: LX
Thermal PAD: AGND
Via to ground plane
Vin Vo
GND
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 13 of 16
Package Dimensions, DFN 4x5
D
Index Area
(D/2
x
E/2)
L
R
1
E2 E3
L1
D2 D3
aaa
C
ccc
C
ddd
C
bbb
aaa
C
D/2
E/2
A3
b
A1
2.125 1.775
0.6
2.2
0.950.5
0.8
2.7
Unit: mm
A
Ae
B
E
C
CAB
Seating
Plane
Pin #1 IDA
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
Dimensions in millimeters
Recommended Land Pattern
Min.
0.80
0.00
0.35
1.975
1.625
2.500
2.050
0.600
0.400
–
–
–
–
Nom.
0.90
0.02
0.20 REF
0.40
5.00 BSC
2.125
1.775
4.00 BSC
2.650
2.200
0.95 BSC
0.700
0.500
0.30 REF
0.15
0.10
0.10
0.08
Max.
1.00
0.05
0.45
2.225
1.875
2.750
2.300
0.800
0.600
–
–
–
–
Symbols
A
A1
A3
b
D
D2
D3
E
E2
E3
e
L
L1
R
aaa
bbb
ccc
ddd
Dimensions in inches
Min.
0.031
0.000
0.014
0.078
0.064
0.098
0.081
0.024
0.016
–
–
–
–
Nom.
0.035
0.001
0.008 REF
0.016
0.197 BSC
0.084
0.070
0.157 BSC
0.104
0.087
0.037 BSC
0.028
0.020
0.012 REF
0.006
0.004
0.004
0.003
Max.
0.039
0.002
0.018
0.088
0.074
0.108
0.091
0.031
0.024
–
–
–
–
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 14 of 16
Tape Dimensions, DFN 4x5
R0.40
P0
K0 A0
E
E2 D0
E1
D1
B0
Package
DFN 5x4
(12 mm)
A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T
5.30
±0.10 ±0.10
4.30
±0.10
1.20 Min.
1.50 1.50 12.00
±0.10
1.75
±0.10
5.50
±0.10
8.00
±0.20
4.00
±0.10
2.00
±0.05
0.30
Unit: mm
T
Typ.
0.20
Feeding
Direction
Tape
Leader/Trailer and Orientation
±0.30
+0.10 / –0
Trailer Tape
(300mm Min.)
Components Tape
Orientation in Pocket
Leader Tape
(500mm Min.)
Not Recommended For New Designs
Rev. 1.3 February 2009 www.aosmd.com Page 15 of 16
AOZ1092D
Reel Dimensions, DFN 4x5
VIEW: C
C
0.05
3-1.8
ø96±0.2
6.45±0.05
3-ø2.9±0.05
3-ø1/8"
3-ø1/4"
8.9±0.1
11.90
14 REF
1.8
5.0
12 REF
41.5 REF
43.00
44.5±0.1
2.00
6.50
10.0
10.71
10°
3-ø3/16"
R48 REF
ø86.0±0.1
2.20
6.2
ø13.00
ø21.20
ø17.0
R1.10
R3.10
2.00
3.3
4.0
6.10
0.80
3.00
8.00
+0.05
0.00
R0.5
1.80
2.5
38°
44.5±0.1
46.0±0.1
8.0±0.1
40°
6°
3-ø3/16"
R3.95
6.50
ø90.00
6.0
1.8
1.8
R1
8.00
0.00
-0.05
N=ø100±2 A
A
A
R121
R127
R159
R6
R55
P
B
W1
M
II I
I
6.0±1
R1
Zoom In
III
Zoom In
II
Zoom In
A
Not Recommended For New Designs
AOZ1092D
Rev. 1.3 February 2009 www.aosmd.com Page 16 of 16
Package Marking
Z1092DI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perfor m can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This data sheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Not Recommended For New Designs
