1/23
L6206
September 2003
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■5.6A OUTPUT PEAK CURRENT (2.8A DC)
■RDS(ON) 0.3Ω TY P. VAL U E @ Tj = 25 °C
■OPERA TING FREQUENCY UP T O 100KHz
■
PROGRAMMABLE HIGH SIDE OVERCURRENT
DETECTION AND PROTECTION
■
DIAGNOSTIC OUTPUT
■
PARALLELED OPERATION
■CROSS CONDUCTION PROTECTION
■THERMAL SHUTDOWN
■UNDER VOLTAG E LOCKOUT
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■BIPOLAR STEPPER MOTOR
■DUAL OR QUAD DC MOT OR
DESCRIPTION
The L6206 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar c ircuits on
the same chip. Available in PowerDIP24 (20+2+2),
PowerSO36 and SO24 (20+2+2) packages, the
L620 6 features thermal shutdown and a non-dis sipa-
tive overcurrent detection on the high side Power
MOSFETs plus a diagnosti c output that can be easily
used to implement the overcurrent protection.
BLOCK DIAGRAM
D99IN1088A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
PROGCL
B
OCD
B
OCD
A
PROGCL
A
OCD
A
OCD
B
ORDERING NUMBERS:
L6206N (PowerDIP24)
L6206PD (PowerSO36)
L6206D (SO24)
PowerDIP24
(20+2+2) PowerSO36 SO24
(20+2+2)
DMOS DUAL FULL BRIDGE DRIVER
L6206
2/23
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test conditions Value Unit
VSSupply Voltage
V
SA
=
VSB =
VS60 V
VOD Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS = 60V;
V
SENSEA
= V
SENSEB = GND 60 V
OCD
A
,OCD
B
OCD pins Voltage Range -0.3 to +10 V
PROGCL
A
,
PROGCLBPROGCL pins Voltage Range -0.3 to +7 V
VBOOT Bootstrap Peak Voltage
V
SA
=
VSB =
VSVS + 10 V
VIN,VEN Input and Enable Voltage Range -0.3 to +7 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB -1 to +4 V
IS(peak) Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
V
SA
=
VSB =
VS;
tPULSE < 1ms 7.1 A
ISRMS Supply Current (for each
VS pin)
V
SA
=
VSB =
VS2.8 A
Tstg, TOP Storage and Operating
Temperature Range -40 to 150 °C
Symbol Parameter Test Conditions MIN MAX Unit
VSSupply Voltage
V
SA
=
VSB =
VS852V
V
OD Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS;
V
SENSEA
= V
SENSEB 52 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB(pulsed tW < trr)
(DC) -6
-1 6
1V
V
IOUT RMS Output Current 2.8 A
TjOperating Junction Temperature -25 +125 °C
fsw Switching Frequency 100 KHz
3/23
L6206
THE RMAL DA TA
PIN CONNECTIONS (Top View)
(5) The slug is internally c onnected to pins 1,18,19 and 36 (GND pins).
Symbol Description PowerDIP24 SO24 PowerSO36 Unit
Rth-j-pins MaximumThermal Resistance Junction-Pins 18 14 - °C/W
Rth-j-case Maximum Thermal Resistance Junction-Case - - 1 °C/W
Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 1
(1) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the bot tom side of 6 c m 2 (with a thic kness of 35 µm ).
43 51 - °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2
(2) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the top side of 6 cm2 (wi t h a thickness of 35 µm).
--35°C/W
Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on t he top side of 6 cm2 (with a thickness of 35 µm), 16 via holes
and a ground l ayer.
--15°C/W
Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4
(4) Mounted on a m ul ti-layer FR4 PCB without any heat s i nking surf ace on th e board.
58 77 62 °C/W
PowerDIP24/SO24 PowerSO36(5)
GND
GND
OUT1B
OCDB
SENSEB
IN2B
IN1B
1
3
2
4
5
6
7
8
9
PROGCLB
VBOOT
ENB
OUT2B
VSB
GND
GND19
18
17
16
15
13
14
D99IN1089A
10
11
12
24
23
22
21
20
IN1A
IN2A
SENSEA
OCDA
OUT1AVSA
OUT2A
VCP
ENA
PROGCLA
GND
N.C.
N.C.
VSA
OCDA
OUT1A
N.C.
N.C.
N.C. N.C.
N.C.
OUT1B
OCDB
N.C.
VSB
N.C.
N.C.
GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
GND GND
D99IN1090A
IN1A
SENSEA
IN2ASENSEB
IN2B
IN1B
9
8
7
28
29
30
PROGCLAPROGCLB
10 27
OUT2A
ENA
VCP
ENB
OUT2B
VBOOT
14
12
11
23
25
26
N.C. N.C.
13 24
L6206
4/23
PIN DESCRIPTION
PACKAGE
Name Type Function
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
1 10 IN1ALogic input Bridge A Logic Input 1.
2 11 IN2ALogic input Bridge A Logic Input 2.
3 12 SENSEAPower Supply Bridge A Source Pin. This pin must be connected to Po wer
Ground directly or through a sensing power resistor.
413OCD
A
Open Drain
Output Bridge A Overcurrent Detection and thermal protection pin.
An internal open drain transistor pulls to GND when
overcurrent on bridge A is detected or in case of thermal
protection.
5 15 OUT1APower Output Bridge A Output 1.
6, 7,
18, 19 1, 18,
19, 36 GND GND Signal Ground terminals. In Power DIP and SO packages,
these pins are also used for heat dissipation toward the
PCB.
8 22 OUT1BPower Output Bridge B Output 1.
9 24 OCDBOpen Drain
Output Bridge B Overcurrent Detection and thermal protection pin.
An internal open drain transistor pulls to GND when
overcurrent on bridge B is detected or in case of thermal
protection.
10 25 SENSEBPower Supply Bridge B Source Pin. This pin must be connected to Po wer
Ground directly or through a sensing power resistor.
11 26 IN1BLogic Input Bridge B Input 1
12 27 IN2BLogic Input Bridge B Input 2
13 28 PROGCLBR Pin Bridge B Overcurrent Level Programming. A resistor
connected between this pin and Ground sets the
programmable current limiting value for the bridge B. By
connecting this pin to Ground the maximum current is set.
This pin cannot be left non-connected.
14 29 ENBLogic Input Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B.
If not used, it has to be connected to +5V.
15 30 VBOOT Supply
Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16 32 OUT2BPower Output Bridge B Output 2.
17 33 VSBPower Supply Bridge B Power Supply Voltage. It must be connected to
the supply voltage together with pin VSA.
20 4 VSAPower Supply Bridge A Power Supply Voltage. It must be connected to
the supply voltage together with pin VSB.
21 5 OUT2APower Output Bridge A Output 2.
5/23
L6206
PACKAGE
Name Type Function
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
22 7 VCP Output Charge Pump Oscillator Output.
23 8 ENALogic Input Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A.
If not used, it has to be connected to +5V.
24 9 PROGCLAR Pin Bridge A Overcurrent Level Programming. A resistor
connected between this pin and Ground sets the
programmable current limiting value for the bridge A. By
connecting this pin to Ground the maximum current is set.
This pin cannot be left non-connected.
ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
VSth(ON) Turn-on Threshold 6.6 7 7.4 V
VSth(OFF) Turn-off Threshold 5.6 6 6.4 V
ISQuiescent Supply Current All Bridges OFF;
Tj = -25°C to 125°C (6) 510mA
T
j(OFF) Thermal Shutdown Temperature 165 °C
Output DMOS Transist ors
RDS(ON) High-Side Switch ON Resistance Tj = 25 °C 0.34 0.4 Ω
Tj =125 °C (6) 0.53 0.59 Ω
Low-Side Switch ON Resistance Tj = 25 °C 0.28 0.34 Ω
Tj =125 °C (6) 0.47 0.53 Ω
IDSS Leakage Current EN = Low; OUT = VS2mA
EN = Low; OUT = GND -0.15 mA
Source Drain Diodes
VSD Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 1.3 V
trr Reverse Recove r y Time If = 2.8A 300 ns
tfr Forward Recovery Time 200 ns
Logic Input
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA
PIN DESCRIPTION
(continued)
L6206
6/23
(6) Tested at 25°C in a restricted range and guaranteed by characterization.
(7) See Fig. 1.
(8) See Fig. 2.
IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA
Vth(ON) Turn-on Input Threshold 1.8 2.0 V
Vth(OFF) Turn-off Input Threshold 0.8 1.3 V
Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V
Switching Characteristics
tD(on)EN
Enable to out turn O N delay time
(7)
ILOAD =2.8A, Resistive Load 100 250 400 ns
tD(on)IN Input to out turn ON delay time ILOAD =2.8A, Resistive Load
(dead time included) 1.6 µs
tRISE Output rise time(7) ILOAD =2.8A, Resistive Load 40 250 ns
tD(off)EN
Enable to out turn OFF delay time
(7)
ILOAD =2.8A, Resistive Load 300 550 800 ns
tD(off)IN
Input to out turn OFF delay time
ILOA D =2.8A, Resistive Load 600 ns
tFALL Output Fall Time (7) ILOAD =2.8A, Resistive Load 40 250 ns
tdt Dead Time Protection 0.5 1 µs
fCP Charge pump frequency -25°C<Tj <125°C 0.6 1 MHz
Over Current Detection
Is over Input Supply Over Current
DetectionThreshold -25°C<Tj <125 °C; RCL= 39 kΩ
-25°C<Tj <125 °C; RCL= 5 kΩ
-25°C<Tj <125 °C; RCL= GND
-10%
-10%
-30%
0.57
4.42
5.6
+10%
+10%
+30%
A
A
A
ROPDR Open Drain ON Resistance I = 4mA 40 60 Ω
tOCD(ON) OCD Turn-on Delay Time (8) I = 4mA; CEN < 100pF 200 ns
tOCD(OFF) OCD Turn-off Delay Time (8) I = 4mA; CEN < 100pF 100 ns
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
7/23
L6206
Figure 1. Switching Characteristi c Definition
Figu re 2. Overcurre nt D et ect i on Tim i ng Defi ni tio n
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
OCD
Threshold
90%
10%
I
OUT
V
OCD
t
t
t
OCD(OFF)
t
OCD(ON)
D01IN1222
L6206
8/23
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6206 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.3ohm (typical value @ 25°C), with intrinsic
fast freewheeling diode. Cross conduc tion protection
is achieved using a dead time (td = 1
µ
s typical) be-
tween the switch off and switch on of two Pow er MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive vol tage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figu re 3. Charge Pum p Circ u it
LOGIC INPUTS
Pins IN 1
A
, IN2
A
, IN1
B
, IN2
B
, EN
A
and EN
B
are TTL/
CMOS and uC compatible logic inputs. The internal
structure is shown in Fig. 4. Typical value for turn-on
and turn-off thresholds are respectively Vthon=1.8V
and Vthoff = 1.3V.
Pins EN
A
and EN
B
are commonly used to implement
Overcurrent and Thermal protection by connecting
them respectively to the outputs OCD
A
and OCD
B
,
which are open-drain outputs. If that type of connec-
tion is chosen, some care needs to be taken in driving
these pins. Two configurations are shown in Fig. 5
and Fig. 6. If driven by an open drain (collec tor) struc-
ture, a pull-up resistor R
EN
and a capacitor C
EN
are
connected as shown in Fig. 5. If the driver is a stan-
dard Push- Pull structur e the resis tor R
EN
and the ca-
pacitor C
EN
are connected as shown in Fig. 6. The
resistor R
EN
should be chosen in the range from
2.2k
Ω
to 180K
Ω
. Recommended values for R
EN
and
C
EN
are respectively 100K
Ω
and 5.6nF. Mor e infor-
mation on selecting the values is found in the Over-
current Protection section.
Figu re 4. Lo gi c Inp uts I nte rn al S truc ture
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
TRUTH TABLE
X = Don't care
High Z = High Impedance Output
CBOOT 220nF
CP10nF
RP100Ω
D1 1N4148
D2 1N4148
D2 CBOOT
D1
RP
CP
VS
VSA
VCP VBOOT VSB
D01IN1328
INPUTS OUTPUTS
EN IN1 IN2 OUT1 OUT2
L X X High Z High Z
H L L GND GND
H H L Vs GND
HLHGNDVs
HHHVsVs
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
REN
CEN ENA or ENB
OCDA or OCDB
D02IN135
5
5V
PUSH-PULL
OUTPUT
REN
CEN
ENA or ENB
D02IN135
6
OCDA or OCDB
9/23
L6206
NON-DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION
In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated. This circuit can be
used to provides protection against a short circuit to ground or between two phases of the bridge as well as a
roughl y regulation of the load c urrent. With this internal over cur rent detecti on, the external cur rent sense res is-
tor normally used and its associated power dissipation are eliminated. Fig. 7 shows a simplified schematic of
the overcurrent detection circuit for the Bridge A. Bridge B is provided of an analogous circuit.
To implement the over current detection, a sens ing element that deli vers a small but preci se fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current reaches the detection threshold Isover the OCD comparator signals a fault
condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA
connected to OCD pin is turned on. Fig. 8 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to EN pin and adding
an external R-C as shown in Fig.7. The off time before recovering normal operation can be easily programmed
by means of the accurate thresholds of the logic inputs.
I
REF
and, ther efore, the output c urren t detection threshold are s electabl e by R
CL
value, followi ng the equati ons:
– Isover = 5.6A ±30% at -25°C < T
j
< 125°C if R
CL
= 0
Ω
(PROGCL connected to GND)
– Isover = ±10% at -25°C < T
j
< 125°C if 5K
Ω <
R
CL
< 40k
Ω
Fig. 9 show s the output current protection threshold versus R
CL
value in the range 5k
Ω
to 40k
Ω
.
T he Disa bl e Time t
DISABLE
before recovering normal operation can be easily programmed by means of the accu-
rate thresholds of the logic inputs. It is affected whether by C
EN
an d R
EN
values and its magnitude is reported in
Figure 10. The Delay Time t
DELAY
before turning off the bridge when an overcurrent has been detected depends
only by C
EN
va lue. Its m agnitude is reported i n Figure 11.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should
be chosen as big as possible according to the maximum tolerable Delay Time and the R
EN
value should be chosen
according to the desired Disable Time.
The resistor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Rec om men de d va lu e s fo r R
EN
and C
EN
a re res pe c tiv el y 10 0K
Ω
an d 5.6nF that al low obtaining 20 0
µ
s Disable Time.
22100
RCL
----------------
L6206
10/23
Figure 7. Overcur rent Protection Simpl ified Schema tic
Figure 8. Overcur rent Protection Wavefor m s
+
OVER
TEMPERATURE
I
REF
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
ENA
R
ENA
R
CLA
.
EN
A
OCD
A
PROGCL
A,
+5V
1.2V
-
+
µC or LOGIC
D02IN1354
I
SOVER
I
OUT
V
th(ON)
V
th(OFF)
V
EN(LOW)
V
DD
t
OCD(ON)
t
D(ON)EN
t
EN(FALL)
t
EN(RISE)
t
DISABLE
t
DELAY
t
OCD(OFF)
t
D(OFF)EN
V
EN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
11/23
L6206
Figu re 9. Ou tput C ur re nt P rot ect i on Thresho ld vers us R
CL
Valu e
Figure 10. tDISABLE versu s C EN and REN (VDD = 5V ).
5k 10k 15k 20k 25k 30k 35k 40k
0
0.5
1
1.5
2
2.5
3
3.5
5
R
CL
[
Ω ]
4
4.5
I
SOVER
[A]
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
L6206
12/23
Figure 11. tDELAY versus CEN (VDD = 5V ).
THERMAL PROTECTION
In addition to the Ovecurrent Detection, the L6206 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
1 10 100
0.1
1
10
Cen [nF]
tdelay [µs]
13/23
L6206
APPLICATION INFORMATION
A typical application using L6206 is shown in Fig. 12. Typical component values for the application are shown
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the pow er
pins ( VS
A
and VS
B
) and ground near the L6206 to improve the high frequenc y fil tering on the power supply and
reduce high frequency transients generated by the switching. The capacitors connected from the EN
A
/OCD
A
and EN
B
/OCD
B
nodes to gr ound set the shut down time for the Br gidge A and Bridge B respectively when an
over current is detected (see Overcurrent Protection). The two current sources (SENSE
A
and SENSE
B
) should
be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immu-
nity, unused logic pins are best connected to 5V (High Logi c Level) or GND (Low Logi c Level) (see pin des cr ip-
tion). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Valu es for Typ ical Application
Figure 12. Typical Appli cation
C1100uF D11N4148
C2100nF D21N4148
CBOOT 220nF RCLA 5KΩ
CP10nF RCLB 5KΩ
CENA 5.6nF RENA 100kΩ
CENB 5.6nF RENB 100kΩ
CREF 68nF RP100Ω
CP
CBOOT
RP
D2
D1
C2
OUT1A
LOADA
LOADB
OCDA
OCDB
1
5
21
18
19
8
16
OUT2A
GND
GND
GND
GND
PROGCLA
OUT2B
OUT1B
VSA
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52VDC
4VSB
VCP
VBOOT
C1
SENSEA
20
IN1A
IN2A
IN1A
IN2A
2
6
7
9
ENA
ENB
CENB
RENB
RENA ENA
ENB
23
IN2B
12
IN1B
IN2B
IN1B
11
14
24
17
3
15
22
SENSEB
RCLA
10
CENA
PROGCLB
13 RCLB
D02IN1344
L6206
14/23
PARALLELED OPERATION
The outputs of the L6206 can be paralleled to increase the output current capability or reduce the power dissi-
pation in the device at a given current level. It must be noted, however, that the internal wire bond connections
from the die to the power o r sense pins of the pa ckage m ust carry curr ent in both of the as sociated half bri dges.
When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on the power supply
or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detec-
tion threshold.
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 13. The current in the two devices
connected in parallel will share very well since the R
DS(ON)
of the devices on the same die is well matched.
When c onnected i n this configuration the over c ur rent detection circuit, whic h senses the c urrent in each bridge
(A and B), will sens e the c urrent in upper device s connec ted in parallel independently and the sens e circ uit w ith
the lowest threshold w ill trip first. With t he enables connected in parallel , the first detection of an over current in
either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current
equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors
R
CLA
or R
CLB
in figure 13. It is recommended to use R
CLA
= R
CLB
.
In this configuration the resulting Bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.15
Ω
Typ. Value @ T
J
= 25°C
- 5.6A max RMS Load Current
- 11.2A max OCD Thr eshold
Figure 13. Parallel connection for higher current
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN2
IN1
A
IN2
B
12
6
7
9
EN
A
EN
B
R
EN
EN23
IN1
B
11
IN2
A
IN1
2
14
24
17
3
15
22
SENSE
B
R
CLA
10
C
EN
PROGCL
B
13 R
CLB
D02IN1364
15/23
L6206
To operate the device in parallel and maintain a lower over current threshol d, Half Bridge 1 and the Half B ridge
2 of the Bridge A can be connected in parallel and the same done for the B ridge B as shown in Figure 14. In
this c onfiguration, the peak current for eac h hal f br idge is stil l l imited by the bond wires for the s upply and s ense
pins so the dissipation in the device will be reduced, but the peak current rating is not increased.
When connected in this configuration the over current detection circuit, senses the sum of the current in upper
devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges.
Sinc e the circui t senses the total current in the upper devices , the over current threshol d is equal to the thres hold
set the resistor R
CLA
or R
CLB
in figure 14. R
CLA
sets the threshold when outputs OUT1
A
and OUT2
A
are high
and resistor R
CLB
sets the threshold when outputs OUT1
B
and OUT2
B
are high.
It is recommended to use R
CLA
= R
CLB
.
In this configuration, the resulting bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.15
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load Current
- 5.6A max OCD Thr eshold
Figure 14. Paral le l connec tion with low er Over curr ent Th resho ld
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4
VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
A
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
IN
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13 R
CLB
D02IN1361
L6206
16/23
It is also possible to parallel the four H alf Bridges to obtain a simple Half B ridge as shown in Fig. 15. In this
configuration the, the over curr ent threshold is equal to twice the minimum threshold set by the resistors R
CLA
or R
CLB
in Figure 15. It is recommended to use R
CLA
= R
CLB
.
The resulting half bridge has the following characteristics.
- Equivalent Device: HALF BRIDGE
- R
DS(ON)
0.075
Ω
Typ. Value @ T
J
= 25°C
- 5.6A max RMS Load Current
- 11.2A max OCD Thr eshold
Figure 15. Paralleling the four Half Bridges
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
LOAD
OCD
A
OCD
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
PROGCL
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
4VS
B
VCP
VBOOT
C
1
SENSE
A
20
IN
IN1
A
IN2
A
2
6
7
9
EN
A
EN
B
C
EN
R
EN
EN
23
IN2
B
12
IN1
B
11
14
24
17
3
15
22
SENSE
B
R
CLA
10
PROGCL
B
13 R
CLB
D02IN1365
17/23
L6206
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fi g. 16 and Fig. 17 are show n the approxi mate relation between th e output curr ent and the IC power dis sipa-
tion using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig.16) in which only one load at a t i me is energized.
– Two Full Bridges ON at the sam e time (Fig.17) in which two loads at the sam e time are energize d.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125°C maximum).
Figure 16. IC Power Dis sipation versu s Outp ut Current wi th One Full Bridge ON at a tim e.
Figure 17. IC P ower Dissipation versus Ou tput Curren t wi th Two Full Bridges ON at the same time.
THERMAL MANAGEMENT
In m ost applications the power dissi pation in the IC is the m ain f actor that sets the maximum current that can be de-
li ver by the dev ice in a saf e operating condit ion. Ther efore, it ha s to be taken i nto account very car ef ully. Besides the
a vai la ble space on the PCB, the r igh t package should be chose n considering the power dissi pat ion. Heat sinki ng can
be achieved using copper on the PCB with proper area and thickness. Figures 19, 20 and 21 show the Junction-to-
Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerS O package with copper slug soldered on a 1.5 mm copper thickness F R4 board
with 6cm
2
dissipati ng footpr int (cop per thicknes s of 35µ m), the R
th j-amb
is about 35° C/W. Fig. 18 shows mount-
ing methods for this pack age. Using a multi-layer board wi th vias to a ground plane, thermal impeda nce can be
reduced dow n to 15°C/W.
No PWM
fSW = 30kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
0 0.5 1 1.5 2 2.5 3
0
2
4
6
8
10
PD [W]
IOUT [A]
ONE FULL BRIDGE ON AT A TIME
No PWM
fSW = 30kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
00.511.522.53
0
2
4
6
8
10
PD [W]
IOUT [A]
TWO FULL BRIDGES ON AT THE SAME TIME
L6206
18/23
Figure 18. Mou nting the PowerS O pack age.
Figure 19. Pow erSO36 Junction-Am bient thermal resistance versus on -board co pp er area.
Figure 20. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 21. SO24 Ju nction -Am bient thermal resistance ve rsus on -board co pp er area.
Sl ug soldered
to PC B with
dissipating area
Sl ug soldered
to PC B with
dissipating area
plus grou nd l ayer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
13
18
23
28
33
38
43
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq. cm
ºC / W
On-Board Copper Area
39
40
41
42
43
44
45
46
47
48
49
1 2 3 4 5 6 7 8 9 101112
Copper Area is on Bottom
Side
Copper Are a is on To p Side
sq . cm
ºC / W On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
123456789101112
Copper Area is on Top Side
sq. cm
ºC / W On-Board Copper Area
19/23
L6206
Figure 22. Typical Quie scen t Curren t vs.
Sup ply Voltage
Figure 23. Normalized Ty pi cal Quiescent
Current vs. Switching Frequen cy
Figu re 24. Typical Lo w-S i de RDS(ON) vs.
Sup ply Voltage
Fi gur e 25 . Typi cal High-Side RDS(ON) vs.
Supply Voltage
Figure 26. Normalized RDS(ON) vs.Junction
Tempe rature (typical value)
Figure 27. Typ ical Drai n-Sou rce Diode
Forward ON Characteristic
4.6
4.8
5.0
5.2
5.4
5.6
0 102030405060
Iq [m A ]
VS [V ]
fsw = 1k Hz Tj = 25°C
Tj = 85°C
Tj = 125°C
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0 20406080100
Iq / (Iq @ 1 kHz)
fSW [kHz]
0.276
0.280
0.284
0.288
0.292
0.296
0.300
0 5 10 15 20 25 30
RDS(ON) [Ω]
VS [V]
Tj = 25°C
0.336
0.340
0.344
0.348
0.352
0.356
0.360
0.364
0.368
0.372
0.376
0.380
0 5 10 15 20 25 30
RDS(ON) [Ω]
VS [V]
Tj = 25°C
0.8
1.0
1.2
1.4
1.6
1.8
0 20406080100120140
R
DS(ON)
/ (R DS(ON) @ 25 °C)
Tj [°C]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
700 800 900 1000 1100 1200 1300
ISD [A]
VSD [mV]
Tj = 25°C
L6206
20/23
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.60 0.141
a1 0.10 0.30 0.004 0.012
a2 3.30 0.130
a3 0 0.10 0 0.004
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D (1) 15.80 16.00 0.622 0.630
D1 9.40 9.80 0.370 0.385
E 13.90 14.50 0.547 0.570
e 0.65 0.0256
e3 11.05 0.435
E1 (1) 10.90 11.10 0.429 0.437
E2 2.90 0.114
E3 5.80 6.20 0.228 0.244
E4 2.90 3.20 0.114 0.126
G 0 0.10 0 0.004
H 15.50 15.90 0.610 0.626
h 1.10 0.043
L 0.80 1.10 0.031 0.043
N10°(max.)
S8°(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2 A
Ea1
PSO36MEC
DETAIL A
D
118
1936
E1
E2
h x 45˚
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
c
NN
⊕
M
0.12 AB
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
21/23
L6206
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.320 0.170
A1 0.380 0.015
A2 3.300 0.130
B 0.410 0.460 0.510 0.016 0.018 0.020
B1 1.400 1.520 1.650 0.055 0.060 0.065
c 0.200 0.250 0.300 0.008 0.010 0.012
D 31.62 31.75 31.88 1.245 1.250 1.255
E 7.620 8.260 0.300 0.325
e 2.54 0.100
E1 6.350 6.600 6.860 0.250 0.260 0.270
e1 7.620 0.300
L 3.180 3.430 0.125 0.135
M 0˚ min, 15˚ max.
Powerdip 24
A1
B eB1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DAT A
L6206
22/23
OUTLINE AND
M E CHANICAL DA T A
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D
(1)
15.20 15.60 0.598 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0;75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “ D” d i m ens i on does not i n c l u de m ol d f l ash, p rotu s ions or gat e
bur rs . M ol d flas h, p rotus ion s o r gat e b urrs shal l no t ex ceed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Information furnishe d is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the c onsequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No lic ense is granted
by i m pl icati on or otherwise under any patent or patent right s of ST M icroe l ectronics. Sp ecification s mentioned in this p ublicat i on are subject
to change without notice. This publication supersedes and replaces all i nformation previously supplied. STMicroelectronics produ ct s are not
authorized for use as critical comp onents in life support dev i ces or systems without express wri tten ap proval of ST M i croel ectronics.
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23/23
L6206
