93LC46B/56B/66B 1K/2K/4K 2.0V CMOS Serial EEPROM FEATURES DESCRIPTION * Single supply with programming operation down to 2.0V (Commercial only) * Low power CMOS technology - 1 mA active current typical - 5 A standby current (typical) at 3.0V * x16 bit organization * 64x16 (93LC46B) * 128x16 (93LC56B) * 256x16 (93LC66B) * Self-timed ERASE and WRITE cycles (including auto-erase) * Automatic ERAL before WRAL * Power on/off data protection circuitry * Industry standard 3-wire serial I/O * Device status signal during ERASE/WRITE cycles * Sequential READ function * 10,000,000 ERASE/WRITE cycles guaranteed on 93LC56B and 93LC66B * 1,000,000 E/W cycles guaranteed on 93LC46B* * Data retention > 200 years * 8-pin PDIP/SOIC and 14-pin SOIC package (SOIC in JEDEC and EIAJ standards) * Available for extended temperature ranges: - Commercial: 0C to +70C - Industrial: -40C to +85C The Microchip Technology Inc. 93LC46B/56B/66B are 1K, 2K and 4K low voltage serial Electrically Erasable PROMs. The device memory is configured as x16. Advanced CMOS technology makes these devices ideal for low power non-volatile memory applications. The 93LC Series is available in standard 8-pin DIP and 8/14-pin surface mount SOIC packages. BLOCK DIAGRAM VCC VSS MEMORY ARRAY ADDRESS DECODER ADDRESS COUNTER OUTPUT BUFFER DATA REGISTER DO DI MODE DECODE LOGIC CS CLOCK GENERATOR CLK PACKAGE TYPE SOIC DIP SOIC CS 1 8 V CC CLK 2 7 DI 3 DO 4 SOIC 14 NC CS 2 13 Vcc CLK 3 12 NU NU 8 NC NC 4 11 NC NU Vcc 2 7 Vss DI 5 10 NC 6 NC CS 3 6 DO DO 6 9 Vss 5 V SS CLK 4 5 DI NC 7 8 NC CS 8 V CC NU CLK 2 7 6 NC DI 3 5 V SS DO 4 93LC46B 93LC56B 93LC66B 1 1 1 93LC46B 93LC56B 93LC66B NC 93LC46BX 93LC56BX 93LC66BX 93LC56B 93LC66B **Future: 10,000,000 E/W cycles guaranteed 1995 Microchip Technology Inc. DS20068F-page 1 93LC46B/56B/66B 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name VCC ........................................................................ 7.0V All inputs and outputs w.r.t. VSS ....-0.6V to VCC +1.0V Storage temperature ...........................-65C to +150C Ambient temp. with power applied ......-65C to +125C Soldering temperature of leads (10 seconds) ...+300C ESD protection on all pins..................................... 4 kV *Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: Parameter (C): Vcc = +2.0V to +6.0V (I): Vcc = +2.5V to +6.0V Symbol Min Max Units VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT 2.0 0.7 VCC -0.3 -0.3 -- -- 2.4 VCC-0.2 -10 -10 -- VCC + 1 VCC + 1 0.8 0.2 VCC 0.4 0.2 -- -- 10 10 7 V V V V V V V V A A pF ICC write ICC read -- -- Standby current ICCS -- 3 1 500 100 30 mA mA A A A Clock frequency FCLK -- Clock high time Clock low time TCKH TCKL 250 2 1 -- MHz MHz ns High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current 250 -- TCSS 50 -- TCSH 0 -- TCSL 250 -- TDIS 100 -- TDIH 100 -- TPD -- 400 TCZ -- 100 TSV -- 500 TWC -- 10 TEC -- 15 TWL -- 30 This parameter is tested at tamb = 25C and FCLK = 1 MHz. Typical program cycle time is 4 ms per word. This parameter is periodically sampled and not 100% tested. Chip select setup time Chip select hold time Chip select low time Data input setup time Data input hold time Data output delay time Data output disable time Status valid time Program cycle time DS20068F-page 2 Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground NC No Connect NU Not Utilized VCC Power Supply DC AND AC ELECTRICAL CHARACTERISTICS Commercial Industrial Note 1: Note 2: Note 3: PIN FUNCTION TABLE ns ns ns ns ns ns ns ns ns ms ms ms (C): Tamb = 0C to +70C (I): Tamb = -40C to +85C Conditions VCC 2.7V VCC < 2.7V VCC 2.7V VCC < 2.7V IOL = 2.1 mA; VCC = 4.5V IOL = 100 A; VCC = Vcc Min. IOH = -400 A; VCC = 4.5V IOH = -100 A; VCC = VCC Min. VIN = 0.1V to VCC VOUT = 0.1V to VCC VIN/VOUT = 0 V (Note 1 & 3) Tamb = +25C, FCLK = 1 MHz FCLK = 2 MHz; VCC = 6.0V (Note 3) FCLK = 2 MHz; VCC = 6.0V FCLK = 1 MHz; VCC = 3.0V CLK = CS = 0V; VCC = 6.0V CLK = CS = 0V; VCC = 3.0V VCC 4.5V VCC < 4.5V Relative to CLK Relative to CLK Relative to CLK Relative to CLK CL= 100 pF CL = 100 pF (Note 3) CL= 100 pF ERASE/WRITE mode (Note 2) ERAL mode WRAL mode 1995 Microchip Technology Inc. 93LC46B/56B/66B TABLE 1-3: Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS TABLE 1-4: Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS TABLE 1-5: Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS INSTRUCTION SET FOR 93LC46B SB Opcode Address Data In Data Out Req. CLK Cycles 1 1 1 1 1 1 1 10 00 11 00 01 00 00 A5 A4 A3 A2 A1 A0 1 1 X X X X A5 A4 A3 A2 A1 A0 1 0 X X X X A5 A4 A3 A2 A1 A0 0 1 X X X X 0 0 X X X X -- -- -- -- D15 - D0 D15 - D0 -- D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z 25 9 9 9 25 25 9 INSTRUCTION SET FOR 93LC56B SB Opcode Address Data In Data Out Req. CLK Cycles 1 1 1 1 1 1 1 10 00 11 00 01 00 00 X A6 A5 A4 A3 A2 A1 A0 1 1 X X X X X X X A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X X X A6 A5 A4 A3 A2 A1 A0 0 1 X X X X X X 0 0 X X X X X X -- -- -- -- D15 - D0 D15 - D0 -- D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z 27 11 11 11 27 27 11 INSTRUCTION SET FOR 93LC66B SB Opcode Address Data In Data Out Req. CLK Cycles 1 1 1 1 1 1 1 10 00 11 00 01 00 00 A7 A6 A5 A4 A3 A2 A1 A0 1 1 X X X X X X A7 A6 A5 A4 A3 A2 A1 A0 1 0 X X X X X X A7 A6 A5 A4 A3 A2 A1 A0 0 1 X X X X X X 0 0 X X X X X X -- -- -- -- D15 - D0 D15 - D0 -- D15 - D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z 27 11 11 11 27 27 11 1995 Microchip Technology Inc. DS20068F-page 3 93LC46B/56B/66B 2.0 FUNCTIONAL DESCRIPTION Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the ready/busy status during a programming operation. The ready/busy status can be verified during an Erase/ Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-Z state on the falling edge of the CS. 2.1 START Condition The START bit is detected by the device if CS and DI are both HIGH with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (READ, WRITE, ERASE, EWEN, EWDS, ERAL, and WRAL). As soon as CS is HIGH, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new start condition is detected. 2.2 DI/DO It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a "bus conflict" to occur during the "dummy zero" that precedes the READ operation, if A0 is a logic HIGH level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. 2.3 Data Protection During power-up, all programming modes of operation are inhibited until VCC has reached a level greater than 1.4V. During power-down, the source data protection circuitry acts to inhibit all programming modes when VCC has fallen below 1.4V at nominal conditions. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. DS20068F-page 4 3.0 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16 bit (x16 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. 4.0 ERASE/WRITE ENABLE AND DISABLE The 93LC46B/56B/66B powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturb, the EWDS instruction can be used to disable all Erase/Write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. 5.0 ERASE The ERASE instruction forces all data bits of the specified address to the logical "1" state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been erased and the device is ready for another instruction. The ERASE cycle takes 4 ms per word (Typical). 6.0 WRITE The WRITE instruction is followed by 16 bits of data which are written into the specified address. After the last data bit is put on the DI pin, CS must be brought low before the next rising edge of the CLK clock. This falling edge of CS initiates the self-timed auto-erase and programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical "0" indicates that programming is still in progress. DO at logical "1" indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. The WRITE cycle takes 4 ms per word (Typical). 1995 Microchip Technology Inc. 93LC46B/56B/66B 7.0 ERASE ALL The ERAL instruction will erase the entire memory array to the logical "1" state. The ERAL cycle is identical to the ERASE cycle except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is guaranteed at VCC = +4.5V to +6.0V. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. The ERAL cycle takes 15 ms maximum (8 ms typical). 8.0 WRITE ALL The WRAL instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is guaranteed at VCC = +4.5V to +6.0V. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). The WRAL cycle takes 30 ms maximum (16 ms typical). 9.0 PIN DESCRIPTION 9.1 Chip Select (CS) A HIGH level selects the device. A LOW level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated and/or in progress will be completed, regardless of the CS input signal. If CS is brought LOW during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. and clock LOW time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a "Don't Care" if CS is LOW (device deselected). If CS is HIGH, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. After detection of a start condition the specified number of clock cycles (respectively LOW to HIGH transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (see instruction set truth table). CLK and DI then become don't care inputs waiting for a new start condition to be detected. Note: 9.3 CS must go LOW between consecutive instructions. Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 9.4 Data Out (DO) Data Out is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought HIGH after being LOW for minimum chip select LOW time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held LOW or HIGH during the entire WRITE or ERASE cycle. In all other cases DO is in the HIGH-Z mode. If status is checked after the WRITE/ERASE cycle, a pull-up resistor on DO is required to read the READY signal. CS must be LOW for 250 ns minimum (TCSL) between consecutive instructions. If CS is LOW, the internal control logic is held in a RESET status. 9.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93LCXXB. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at HIGH or LOW level) and can be continued anytime with respect to clock HIGH time (TCKH) 1995 Microchip Technology Inc. DS20068F-page 5 93LC46B/56B/66B FIGURE 9-1: SYNCHRONOUS DATA TIMING V IH CS TCSS V IL TCKH TCKL TCSH V IH CLK V IL TDIH TDIS V IH DI V IL TPD DO (READ) TCZ TPD V OH TCZ V OL TSV DO V OH (PROGRAM) V OL FIGURE 9-2: STATUS VALID READ TIMING TCSL CS CLK DI 1 1 0 *A n *** A0 TRI-STATETM DO 0 Dx *** D0 Dx* *** D0 Dx* *** D0 Tri-State is a trademark of National Semiconductor. FIGURE 9-3: EWEN TIMING TCSL CS CLK DI DS20068F-page 6 1 0 0 1 1 X *** X 1995 Microchip Technology Inc. 93LC46B/56B/66B FIGURE 9-4: EWDS TIMING T CSL CS CLK DI 1 FIGURE 9-5: 0 0 0 0 *** X X WRITE TIMING TCSL CS CLK DI 1 0 1 *A n *** A0 Dx *** D0 TRI-STATE DO BUSY READY TWC FIGURE 9-6: WRAL TIMING TCSL CS CLK DI DO 1 0 0 TRI-STATE 0 1 X *** X Dx *** D0 BUSY READY TWL Guarantee at Vcc = +4.5V to +6.0V. 1995 Microchip Technology Inc. DS20068F-page 7 93LC46B/56B/66B FIGURE 9-7: ERASE TIMING TCSL CS STANDBY CHECK STATUS CLK 1 DI 1 1 An An-1 An-2 *** A0 TSV TRI-STATE BUSY DO TCZ READY TRI-STATE TWC FIGURE 9-8: ERAL TIMING TCSL CS CHECK STATUS STANDBY CLK 1 DI 0 0 1 0 TCZ TSV DO TRI-STATETM BUSY READY TRI-STATE TEC Guarantee at Vcc = +4.5V to +6.0V. DS20068F-page 8 1995 Microchip Technology Inc. 93LC46B/56B/66B NOTES 1995 Microchip Technology Inc. DS20068F-page 9 93LC46B/56B/66B 93LC46B/56B/66B Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 93LC46B/56B/66B - /P Package: Temperature Range: P SN SM SL = = = = Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (207 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead (93LC56B/93LC66B) Blank = 0C to +70C I = -40C to +85C Device: Configuration 93LC46B/56B/66B 93LC46BX/56BX/66BX 93LC46BT/56BT/66BT 93LC46BXT/56BXT/66BXT CMOS Serial EEPROM CMOS Serial EEPROM in alternate pinouts (SN package only) CMOS Serial EEPROM (Tape and Reel) CMOS Serial EEPROM (Tape and Reel) AMERICAS AMERICAS (continued) EUROPE Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602 786-7200 Fax: 602 786-7277 Technical Support: 602 786-7627 Web: http://www.mchip.com/biz/mchip Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770 640-0034 Fax: 770 640-0307 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508 480-9990 Fax: 508 480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 708 285-0071 Fax: 708 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 214 991-7177 Fax: 214 991-8588 Dayton Microchip Technology Inc. 35 Rockridge Road Englewood, OH 45322 Tel: 513 832-2543 Fax: 513 832-2841 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 455 Irvine, CA 92715 Tel: 714 263-1888 Fax: 714 263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408 436-7950 Fax: 408 436-7955 United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL8 5AJ Tel: 44 0 1628 851077 Fax: 44 0 1628 850259 France Arizona Microchip Technology SARL 2 Rue du Buisson aux Fraises 91300 Massy - France Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muenchen, Germany Tel: 49 89 627 144 0 Fax: 49 89 627 144 44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Pegaso Ingresso No. 2 Via Paracelso 23, 20041 Agrate Brianza (MI) Italy Tel: 39 039 689 9939 Fax: 39 039 689 9883 ASIA/PACIFIC Hong Kong Microchip Technology Unit No. 3002-3004, Tower 1 Metroplaza 223 Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 9/5/95 Printed in the USA, 9/95 1995, Microchip Technology Incorporated "Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS20068F-page 10 1995 Microchip Technology Inc.