1995 Microchip Technology Inc. DS20068F-page 1
FEATURES
• Single supply with programming operation down
to 2.0V (Commercial only)
• Low power CMOS technology
- 1 mA active current typical
-5
µ
A standby current (typical) at 3.0V
• x16 bit organization
• 64x16 (93LC46B)
• 128x16 (93LC56B)
• 256x16 (93LC66B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles guaranteed
on 93LC56B and 93LC66B
• 1,000,000 E/W cycles guaranteed on 93LC46B*
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC package
(SOIC in JEDEC and EIAJ standards)
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 93LC46B/56B/66B are
1K, 2K and 4K low voltage serial Electrically Erasable
PROMs. The device memory is configured as x16.
Advanced CMOS technology makes these devices
ideal for low power non-volatile memory applications.
The 93LC Series is available in standard 8-pin DIP and
8/14-pin surface mount SOIC packages.
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
V
CC
V
SS
DATA REGISTER DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DI
CS
CLK
ADDRESS
COUNTER
93LC46B/56B/66B
1K/2K/4K 2.0V CMOS Serial EEPROM
PACKAGE TYPE
1
2
3
4
8
7
6
5
CS
CLK
DI
DO SS
V
NU
NC
V
CC 1
2
3
4
8
7
6
5SS
V
NU
NC
V
CC
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
NC
Vss
DO
DI
NU
Vcc
CS
CLK
NC
Vcc
NU
NC
NC
Vss
NC
NC
CS
CLK
NC
DI
DO
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
DIP SOIC
93LC46B
93LC56B
93LC66B
93LC46B
93LC56B
93LC66B
93LC46BX
93LC56BX
93LC66BX
93LC56B
93LC66B
SOIC
SOIC
**Future: 10,000,000 E/W cycles guaranteed
93LC46B/56B/66B
DS20068F-page 2
1995 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
V
CC
........................................................................7.0V
All inputs and outputs w.r.t. V
SS
....-0.6V to V
CC
+1.0V
Storage temperature...........................-65˚C to +150˚C
Ambient temp. with power applied......-65˚C to +125˚C
Soldering temperature of leads (10 seconds)...+300˚C
ESD protection on all pins..................................... 4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
V
SS
Ground
NC No Connect
NU Not Utilized
V
CC
Power Supply
TABLE 1-2: DC AND AC ELECTRICAL CHARACTERISTICS
Commercial (C): Vcc = +2.0V to +6.0V (C): Tamb = 0˚C to +70˚C
Industrial (I): Vcc = +2.5V to +6.0V (I): Tamb = -40˚C to +85˚C
Parameter Symbol Min Max Units Conditions
High level input voltage V
IH
1 2.0 V
CC
+ 1 V V
CC
≥
2.7V
V
IH
2 0.7 V
CC
V
CC
+ 1 V V
CC
< 2.7V
Low level input voltage V
IL
1 -0.3 0.8 V V
CC
≥
2.7V
V
IL
2 -0.3 0.2 V
CC
VV
CC
< 2.7V
Low level output voltage V
OL
1 — 0.4 V I
OL
= 2.1 mA; V
CC
= 4.5V
V
OL
2 — 0.2 V I
OL
= 100
µ
A; V
CC
= Vcc Min.
High level output voltage V
OH
1 2.4 — V I
OH
= -400
µ
A; V
CC
= 4.5V
V
OH
2V
CC
-0.2 — V I
OH
= -100
µ
A; V
CC
= V
CC
Min.
Input leakage current I
LI
-10 10
µ
AV
IN
= 0.1V to V
CC
Output leakage current I
LO
-10 10
µ
AV
OUT
= 0.1V to V
CC
Pin capacitance
(all inputs/outputs) C
IN
, C
OUT
— 7 pF V
IN
/V
OUT
= 0 V (Note 1 & 3)
Tamb = +25˚C, F
CLK
= 1 MHz
Operating current I
CC
write — 3 mA F
CLK
= 2 MHz; V
CC
= 6.0V (Note 3)
I
CC
read — 1
500 mA
µ
AF
CLK
= 2 MHz; V
CC
= 6.0V
F
CLK
= 1 MHz; V
CC
= 3.0V
Standby current I
CCS
— 100
30
µ
A
µ
ACLK = CS = 0V; V
CC
= 6.0V
CLK = CS = 0V; V
CC
= 3.0V
Clock frequency F
CLK
—2
1MHz
MHz V
CC
≥
4.5V
V
CC
< 4.5V
Clock high time T
CKH
250 — ns
Clock low time T
CKL
250 — ns
Chip select setup time T
CSS
50 — ns Relative to CLK
Chip select hold time T
CSH
0 — ns Relative to CLK
Chip select low time T
CSL
250 — ns
Data input setup time T
DIS
100 — ns Relative to CLK
Data input hold time T
DIH
100 — ns Relative to CLK
Data output delay time T
PD
— 400 ns CL= 100 pF
Data output disable time T
CZ
— 100 ns CL = 100 pF (Note 3)
Status valid time T
SV
— 500 ns CL= 100 pF
Program cycle time T
WC
— 10 ms ERASE/WRITE mode (Note 2)
T
EC
— 15 ms ERAL mode
T
WL
— 30 ms WRAL mode
Note 1: This parameter is tested at tamb = 25˚C and F
CLK
= 1 MHz.
Note 2: Typical program cycle time is 4 ms per word.
Note 3: This parameter is periodically sampled and not 100% tested.
1995 Microchip Technology Inc. DS20068F-page 3
93LC46B/56B/66B
TABLE 1-3: INSTRUCTION SET FOR 93LC46B
TABLE 1-4: INSTRUCTION SET FOR 93LC56B
TABLE 1-5: INSTRUCTION SET FOR 93LC66B
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25
EWEN 1 00 1 1 X X X X — High-Z 9
ERASE 1 1 1 A5 A4 A3 A2 A1 A0 — (RDY/BSY )9
ERAL 1 00 1 0 X X X X — (RDY/BSY)9
WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25
WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY)25
EWDS 1 00 0 0 X X X X — High-Z 9
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
EWEN 1 00 1 1 X X X X X X — High-Z 11
ERASE 1 1 1 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11
ERAL 1 00 1 0 X X X X X X — (RDY/BSY)11
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27
WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY)27
EWDS 1 00 0 0 X X X X X X — High-Z 11
Instruction SB Opcode Address Data In Data Out Req. CLK
Cycles
READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 27
EWEN 1 00 1 1 X X X X X X — High-Z 11
ERASE 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11
ERAL 1 00 1 0 X X X X X X — (RDY/BSY)11
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)27
WRAL 1 00 0 1 X X X X X X D15 - D0 (RDY/BSY)27
EWDS 1 00 0 0 X X X X X X — High-Z 11
93LC46B/56B/66B
DS20068F-page 4
1995 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The
DO pin is normally held in a high-Z state except when
reading data from the device, or when checking the
ready/busy status during a programming operation.
The ready/busy status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. The DO will enter the
high-Z state on the falling edge of the CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a ST AR T condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However , with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
2.3 Data Protection
During power-up, all programming modes of operation
are inhibited until V
CC
has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
V
CC
has fallen below 1.4V at nominal conditions.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
3.0 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit (x16 organization) output
string. The output data bits will toggle on the rising
edge of the CLK and are stable after the specified time
delay (T
PD
). Sequential read is possible when CS is
held high. The memory data will automatically cycle to
the next register and output sequentially.
4.0 ERASE/WRITE ENABLE AND
DISABLE
The 93LC46B/56B/66B powers up in the Erase/Write
Disable (EWDS) state. All programming modes must
be preceded by an Erase/Write Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is executed or V
CC
is removed from the device. To
protect against accidental data disturb, the EWDS
instruction can be used to disable all Erase/Write func-
tions and should follow all programming operations.
Execution of a READ instruction is independent of both
the EWEN and EWDS instructions.
5.0 ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical "1" state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical "0" indicates that program-
ming is still in progress. DO at logical "1" indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word (Typical).
6.0 WRITE
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. After the
last data bit is put on the DI pin, CS must be brought
low before the next rising edge of the CLK clock. This
falling edge of CS initiates the self-timed auto-erase
and programming cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is com-
plete. DO at logical "0" indicates that programming is
still in progress. DO at logical "1" indicates that the reg-
ister at the specified address has been written with the
data specified and the device is ready for another
instruction.
The WRITE cycle takes 4 ms per word (Typical).
1995 Microchip Technology Inc. DS20068F-page 5
93LC46B/56B/66B
7.0 ERASE ALL
The ERAL instruction will erase the entire memory
array to the logical "1" state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the self clocking mode. The ERAL instruction is guar-
anteed at V
CC
= +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is com-
plete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
8.0 WRITE ALL
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. Clocking of the CLK pin
is not necessary after the device has entered the self
clocking mode. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status. The WRAL
instruction is guaranteed at V
CC
= +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
The WRAL cycle takes 30 ms maximum (16 ms typi-
cal).
9.0 PIN DESCRIPTION
9.1 Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a programming cycle which is already initiated
and/or in progress will be completed, regardless of the
CS input signal. If CS is brought LOW during a pro-
gram cycle, the device will go into standby mode as
soon as the programming cycle is completed.
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
9.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LCXXB.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCKH)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't
care inputs waiting for a new start condition to be
detected.
9.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
9.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after being LOW for minimum chip select
LOW time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
Note: CS must go LOW between consecutive
instructions.
93LC46B/56B/66B
DS20068F-page 6 1995 Microchip Technology Inc.
FIGURE 9-1: SYNCHRONOUS DATA TIMING
FIGURE 9-2: READ TIMING
FIGURE 9-3: EWEN TIMING
CLK
STATUS VALID
VIH
VIL
CS TCSS
TDIS TDIH
TSV
TCSH
TCKH TCKL
TPD TCZ
TCZ
TPD
VIH
VIL
DI VIH
VIL
DO
(READ)
VOH
VOL
DO
(PROGRAM)
VOH
VOL
CLK
CS TCSL
• A • • • A001 1
DI
DO Dx • • • D00 Dx* • • • D0 Dx*
TRI-STATE™
n
D0
• • •
Tri-State is a trademark of National Semiconductor.
CLK
CS TCSL
0 01
DI 1 1 • • •
XX
1995 Microchip Technology Inc. DS20068F-page 7
93LC46B/56B/66B
FIGURE 9-4: EWDS TIMING
FIGURE 9-5: WRITE TIMING
FIGURE 9-6: WRAL TIMING
CLK
CS TCSL
0 01
DI 0 0 • • •
XX
CLK
CS TCSL
01
DI • • •
BUSY
D0
•A1 A0 • • •
Dx
READY
TWC
DO TRI-STATE
n
CLK
CS TCSL
01
DI • • •
BUSY
D0X0 X • • •Dx
READY
TWL
DO
01
TRI-STATE
Guarantee at Vcc = +4.5V to +6.0V.
93LC46B/56B/66B
DS20068F-page 8 1995 Microchip Technology Inc.
FIGURE 9-7: ERASE TIMING
FIGURE 9-8: ERAL TIMING
CLK
CS TCSL
1
DI An
BUSY
A0• • •
READY
TWC
DO
11
CHECK STATUS STANDBY
TCZ
TRI-STATE
TSV
TRI-STATE
An-1 An-2
Guarantee at Vcc = +4.5V to +6.0V.
CLK
CS TCSL
0
DI 0
BUSY
0
READY
TEC
DO
11
CHECK STATUS STANDBY
TCZ
TRI-STATE
TSV
TRI-STATE™
1995 Microchip Technology Inc. DS20068F-page 9
93LC46B/56B/66B
NOTES
93LC46B/56B/66B
DS20068F-page 10 1995 Microchip Technology Inc.
93LC46B/56B/66B Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
Package: P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (93LC56B/93LC66B)
Temperature Blank = 0°C to +70°C
Range: I= -40°C to +85°C
Device: Configuration
93LC46B/56B/66B CMOS Serial EEPROM
93LC46BX/56BX/66BX CMOS Serial EEPROM in alternate
pinouts (SN package only)
93LC46BT/56BT/66BT CMOS Serial EEPROM (Tape and Reel)
93LC46BXT/56BXT/66BXT CMOS Serial EEPROM (Tape and Reel)
93LC46B/56B/66B - /P
AMERICAS (continued)
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9/5/95
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Printed in the USA, 9/95
1995, Microchip Technology Incorporated
