Integrated Silicon Solution, Inc. 3
Rev. 00A
06/23/08
IS42SM32160C
IS42RM32160C
Symbol Type Description
CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
CKE Input ClockEnable:CKEactivates(HIGH)anddeactivates(LOW)theCLKsignal.IfCKEgoeslowsynchronously
withclock(set-upandholdtimesameasotherinputs),theinternalclockissuspendedfromthenextclock
cycleandthestateofoutputandburstaddressisfrozenaslongastheCKEremainslow.Whenallbanks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKEissynchronous except after thedeviceenters PowerDownandSelf Refreshmodes,whereCKE
becomesasynchronousuntilexitingthesamemode.Theinputbuffers,includingCLK,aredisabledduring
Power Down and Self Refresh modes, providing low standby power.
BA0, BA1 Input Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
A0-A12 Input Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respective bank. During a Precharge command,A10 is sampled to determine if all banks are to be precharged
(A10=HIGH).
The address inputs also provide the op-code during a Mode Register Set .
CS Input Chip Select: CSenables(sampledLOW)anddisables(sampledHIGH)thecommanddecoder.Allcommands
are masked when CSissampledHIGH.CSprovidesforexternalbankselectiononsystemswithmultiple
banks. It is considered part of the command code.
RAS Input Row Address Strobe: The RAS signal defines the operation commands in conjunction with the CAS and
WE signals and is latched at the positive edges of CLK. When RAS and CS are asserted “LOW” and CAS
isasserted“HIGH,”eithertheBankActivatecommandorthePrechargecommandisselectedbytheWE
signal. When the WEisasserted“HIGH,”theBankActivatecommandisselectedandthebankdesignated
by BA is turned on to the active state. When the WE is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
CAS Input Column Address Strobe: The CAS signal defines the operation commands in conjunction with the RAS
and WE signals and is latched at the positive edges of CLK. When RASisheld“HIGH”andCS is asserted
“LOW,” the column access is started by asserting CAS ”LOW.” Then, the Read or Write command is selected
by asserting WE“LOW”or“HIGH.”
WE Input WriteEnable:TheWE signal defines the operation commands in conjunction with the RAS and CAS signals
and is latched at the positive edges of CLK. The WE input is used to select the BankActivate or Precharge
command and Read or Write command.
DQM0-3 Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
areplacedinahigh-zstatewhenDQMissampledHIGH.InputdataismaskedwhenDQMissampled
HIGHduringawritecycle.Outputdataismasked(two-clocklatency)whenDQMissampledHIGHduring
a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
DQ0-31 Input/
Output
DataI/O:TheDQ0-31inputandoutputdataaresynchronizedwiththepositiveedgeofCLK.TheI/Osare
byte-maskable during Reads and Writes.
PIN DESCRIPTIONS