INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40106B gates Hex inverting Schmitt trigger Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger DESCRIPTION Each circuit of the HEF40106B functions as an inverter with Schmitt-trigger action. The Schmitt-trigger switches at different points for the positive and negative-going input signals. The difference between the positive-going voltage (VP) and the negative-going voltage (VN) is defined as hysteresis voltage (VH). This device may be used for enhanced noise immunity or to "square up" slowly changing waveforms. Fig.2 Pinning diagram. HEF40106BP(N): 14-lead DIL; plastic (SOT27-1) HEF40106BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF40106BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. Fig.3 Logic diagram (one inverter). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger DC CHARACTERISTICS VSS = 0 V; Tamb = 25 C VDD V Hysteresis 5 voltage 10 Switching levels SYMBOL VH MIN. TYP. MAX. 0,5 0,8 V 0,7 1,3 V 15 0,9 1,8 V 5 2 3,0 V positive-going 10 3,7 5,8 7 V input voltage 15 4,9 8,3 11 V 5 1,5 2,2 3 V negative-going input voltage 10 VP 3,5 VN 15 Fig.5 Fig.4 Transfer characteristic. January 1995 3 3 4,5 6,3 V 4 6,5 10,1 V Waveforms showing definition of VP, VN and VH, where VN and VP are between limits of 30% and 70%. Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays In On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 Output transition times HIGH to LOW 5 10 tTHL 15 5 LOW to HIGH 10 tTLH 15 Dynamic power dissipation per package (P) 90 180 ns 63 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) 30 60 ns 22 ns + (0,16 ns/pF) CL 75 150 ns 48 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V TYPICAL FORMULA FOR P (W) 5 2 300 fi + (foCL) x VDD2 where 10 9 000 fi + (foCL) x VDD 2 fi = input freq. (MHz) 15 20 000 fi + (foCL) x VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger Fig.6 Typical drain current as a function of input voltage; VDD = 5 V; Tamb = 25 C. Fig.8 Typical drain current as a function of input voltage; VDD = 15 V; Tamb = 25 C. January 1995 Fig.7 5 Typical drain current as a function of input voltage; VDD =10 V; Tamb = 25 C. Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb = 25 C. Fig.10 Schmitt trigger driven via a high impedance (R > 1 k). If a Schmitt trigger is driven via a high impedance (R > 1 k) then it is necessary to incorporate a capacitor C of such C V DD - V SS value that: ------- > --------------------------- , otherwise oscillation can occur on the edges of a pulse. VH Cp Cp is the external parasitic capacitance between input and output; the value depends on the circuit board layout. January 1995 6 Philips Semiconductors Product specification HEF40106B gates Hex inverting Schmitt trigger APPLICATION INFORMATION Some examples of applications for the HEF40106B are: * Wave and pulse shapers * Astable multivibrators * Monostable multivibrators. Fig.11 The HEF40106B used as an astable multivibrator. January 1995 7