The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
©
2002
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD23C64340, 23C64380
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Document No. M16335EJ1V0DS00 (1st edition)
Date Published July 2002 NS CP(K)
Printed in Japan
D ATA SHEET
Description
The
µ
PD23C64340 and
µ
PD23C64380 are 67,108,864 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
µ
PD23C64340 and
µ
PD23C64380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.
Features
• Pin compatible with NOR Flash Memory
• Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
• Page access mode
BYTE mode :8 byte random page access (
µ
PD23C64340)
16 byte random page access (
µ
PD23C64380)
WORD mode :4 word random page access (
µ
PD23C64340)
8 word random page access (
µ
PD23C64380)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating suppl y Access t ime / Power supply current Standby c urrent
voltage Page access time (Active mode) (CMOS level input )
VCC ns (MAX.) mA (MAX.)
µ
A (MAX.)
µ
PD23C64340
µ
PD23C64380
3.0 V ± 0.3 V 100 / 25 40 60 30
3.3 V ± 0.3 V 90 / 25 55 75
2
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Ordering Information
Part Number Package
µ
PD23C64340GZ-xxx-MJHNote 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
µ
PD23C64340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)
µ
PD23C64380GZ-xxx-MJHNote 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
µ
PD23C64380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6)
Note Under development
(xxx : ROM code suffix No.)
Marking Image
Part Number Marking ( )
µ
PD23C64340F9-xxx-BC3 B
µ
PD23C64380F9-xxx-BC3 C
J
R64 -xxx
INDEX MARK Lot No.
ROM code suffix No.
3
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Pin Configurations (Marking Side)
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
[
µ
µµ
µ
PD23C64340GZ-xxx-MJH ]
[
µ
µµ
µ
PD23C64380GZ-xxx-MJH ]
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
WORD, /BYTE
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
O11
O3
O10
O2
O9
O1
O8
O0
/OE, OE, DC
GND
/CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 - A21 : Address inputs
O0 - O7, O8 - O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE, OE : Output Enable
VCC : Supply voltage
GND : Ground
NC Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
48-pin TAPE FBGA (8 x 6)
[
µ
µµ
µ
PD23C64340F9-xxx-BC3 ]
[
µ
µµ
µ
PD23C64380F9-xxx-BC3 ]
6
5
4
3
2
1
ABCDEFGHHGFEDCBA
Top View Bottom View
ABCDEFGH HGFEDCBA
6 A13 A12 A14 A15 A16 WORD, O15, GND 6 GND O15, WORD, A16 A15 A14 A12 A13
/BYTE A–1 A–1 /BYTE
5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9
4 NC NC A21 A19 O5 O12 VCC O4 4 O4 VCC O12O5A19A21NCNC
3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC
2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7
1 A3 A4 A2 A1 A0 /CE /OE, OE GND 1 GND /OE, OE /CE A0 A1 A2 A4 A3
A0 - A21 : Address inputs
O0 - O7, O8 - O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE, OE : Output Enable
VCC : Supply voltage
GND : Ground
NC Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
5
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Input / Output Pin Functions
Pin name Input / Output Function
WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.
High level : WORD mode (4M-word by 16-bit)
Low level : BYTE mode (8M-word by 8-bit )
A0 to A21
(Address inputs )
Input Address input pins.
A0 to A21 are used differently in the WORD mode and the BYTE m ode.
WORD mode (4M-word by 16-bit)
A0 to A21 are used as 22 bits address signals.
BYTE mode (8M-word by 8-bit)
A0 to A21 are used as the upper 22 bits of total 23 bits of address signal.
(The least signific ant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output Data output pins.
O0 to O7, O8 to O14 are used diff erently i n the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (8M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
(Data output 15,
LSB Address input)
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The most significant output dat a bus (O15).
BYTE mode (8M-word by 8-bit)
The least significant address bus (A−1).
/CE
(Chip Enable)
Input Chip activati ng si gnal .
When the OE is active, output stat es are foll owing.
High level : High impedance
Low level : Data out
/OE, OE, DC
(Output Enable, Don't care)
Input Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low act i ve and Don’t care at order.
VCC −Supply volt age
GND −Ground
NC −Not internall y connect ed. (The signal can be connected.)
6
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
O15, A−1
WORD, /BYTE
/OE, OE, DC
/CE
Output Buffer
Y-Selector
Memory Cell Matrix
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
Address Input Buffer
X-Decoder
Logic/InputInput Buffer
Y-Decoder
A19
O14O13
O12O11
O10O9
O8
O0 O1 O2 O3 O4 O5 O6 O7
A20
A21
7
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Mask Option
The active levels of output enable pin (/OE, OE, DC) are mask programmable and optional, and can be selected from
among " 0 " " 1 " " x " shown in the table below.
Option /OE, OE, DC OE active level
0/OE L
1OE H
x DC Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE /OE Mode Output state
L L Active Data out
H High impedance
H H or L Standby High impedance
Operation mode (Option : 1)
/CE OE Mode Output state
L L Act i ve High impedance
H Data out
H H or L Standby High impedance
Operation mode (Option : x)
/CE DC Mode Output state
L H or L Active Data out
H H or L Standby High impedance
Remark L : Low level input
H : High level input
8
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply volt age VCC –0.3 to +4.6 V
Input volt age VI–0.3 to VCC+0.3 V
Output voltage VO–0.3 to VCC+0.3 V
Operating ambient t emperature TA–10 to +70 °C
Storage temperature Tstg –65 t o +150 °C
Caution Expos ing t he devi ce to stre ss abo ve thos e list ed in Abso lute Maximum Rati ngs co uld caus e
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CIf = 1 MHz 10 pF
Output capacitance CO12 pF
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test conditions MIN. TYP. MAX. Uni t
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL VCC = 3.0 V ± 0.3 V –0.3 +0. 5 V
VCC = 3.3 V ± 0.3 V –0.3 +0. 8
High level output voltage V OH IOH = –100
µ
A2.4V
Low level output volt age VOL IOL = 2.1 mA 0.4 V
Input leakage current ILI VI = 0 V to VCC –10 +10
µ
A
Output leakage current ILO VO = 0 V to VCC, Chi p deselect ed –10 +10
µ
A
Power supply current ICC1 /CE = VIL
µ
PD23C64340 VCC = 3.0 V ± 0.3 V 40 mA
(Active mode), VCC = 3.3 V ± 0.3 V 55
IO = 0 mA
µ
PD23C64380 VCC = 3.0 V ± 0.3 V 60
VCC = 3.3 V ± 0.3 V 75
Standby cu rrent ICC3 /CE = VCC – 0.2 V (Standby mode) 30
µ
A
9
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Address acc ess tim e tACC 100 90 ns
Page access time tPAC 25 25 ns
Chip enable access time tCE 100 90 ns
Output enable access t ime tOE 25 25 ns
Output hold time tOH 00ns
Output disable time tDF 0 25 0 25 ns
W ORD, /B YTE access time tWB 100 90 ns
Remark tDF is the time from inactivation of /CE or /OE, OE to high-impedance state output.
AC Test Conditions
Input waveform (Rise / Fall time ≤
≤≤
≤ 5 ns)
Test points1.4 V 1.4 V
Output waveform
Test points1.4 V 1.4 V
Output load
1TTL + 100 pF
10
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Read Cycle Timing Chart 1
A0 to A21,
A−1
Note 1
(Input)
O0 to O7,
O8 to O15
Note 3
(Output)
/CE (Input)
/OE, OE (Input)
tACC
tCE
tOE
tDF
Note 2
tOH
Data Out
High impedance
Notes 1. During WORD mode, A–1 is O15.
2. tDF is specified when one of /CE, /OE, OE is inactivated.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
11
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Read Cycle Timing Chart 2 (Page Access Mode)
(Input)
/CE (Input)
/OE, OE (Input)
t
ACC
Data Out
t
CE
t
OE
t
PAC
Note 5
t
PAC
Note 5
O0 to O7,
O8 to O15Note 4
(Input)
(Output) Data Out Data Out
High impedance High
impedance
t
OH
t
OH
t
OH
t
DF
Note 3
A2 to A21
A3 to A21
Upper addressNote 1
A–1Note 2, A0, A1
A–1Note 2, A0, A1, A2
Page addressNote 1
Notes 1. The address differs depending on the product as follows.
Part Number Upper address P age address
µ
PD23C64340 A2 to A21 A–1, A0, A1
µ
PD23C64380 A3 to A21 A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. tDF is specified when one of /CE, /OE, OE is inactivated.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[
µ
µµ
µ
PD23C64340 ]
Page access time Upper address (A 2 to A21) /CE input condition /OE, OE input condition
inputs conditi on
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1)
[
µ
µµ
µ
PD23C64380 ]
Page access time Upper address (A 3 to A21) /CE input condition /OE, OE input condition
inputs conditi on
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1, A2)
12
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
WORD, /BYTE Switch Timing Chart
Data Out
A−1 (Input)
WORD, /BYTE (Input)
Data Out Data Out
High impedance
O0 to O7 (Output)
O8 to O15 (Output)
t
OH
t
ACC
t
OH
t
WB
Data Out Data Out
t
DF
High impedanceHigh impedance
Remark /OE, OE and /CE : Active.
13
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Package Drawings
NOTES
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
48-PIN PLASTIC TSOP (I) (12x20)
ITEM MILLIMETERS
A
B
C
E
I
12.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
18.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1)
"A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)2)
C
R
S
D
KM
M
L
1.0±0.05G
L 0.5
0.10N
P 20.0±0.2
Q3°+5°
−3°
0.25R
S48GZ-50-MJH-1
S 0.60±0.15
J 0.8±0.2
S
Q
N
B
E
G
F
J
detail of lead end
1
24
48
25
S
A
I
P
14
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
ITEM MILLIMETERS
D
E
w
e
A
A1
A2
b
x
y
y1
ZD
ZE
6.0±0.1
8.0±0.1
0.80
0.08
0.1
0.2
1.00
1.20
0.2
0.27±0.05
0.97±0.10
0.45±0.05
0.70
SwB
y1 S
SwA
A
ZD ZE
A1
A2
S
ye
SxbAB
M
φφ
P48F9-80-BC3
48-PIN TAPE FBGA(8x6)
E
D
INDEX MARK INDEX MARK
B
S
A6
5
4
3
2
1
ABCDEFGH
15
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD23C64340 and
µ
PD23C64380.
Types of Surface Mount Device
µ
PD23C64340GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
µ
PD23C64340F9-BC3 : 48-pin TAPE FBGA (8 x 6)
µ
PD23C64380GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
µ
PD23C64380F9-BC3 : 48-pin TAPE FBGA (8 x 6)
16
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
[MEMO]
17
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
[MEMO]
18
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
[MEMO]
19
µ
µµ
µ
PD23C64340, 23C64380
Data Sheet M16335EJ1V0DS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD23C64340, 23C64380
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
M8E 00. 4
The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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•
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•
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