DATA SHEET MOS INTEGRATED CIRCUIT PD23C64340, 23C64380 64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE Description The PD23C64340 and PD23C64380 are 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits). The active levels of OE (Output Enable Input) can be selected with mask-option. The PD23C64340 and PD23C64380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA. Features * Pin compatible with NOR Flash Memory * Word organization 8,388,608 words by 8 bits (BYTE mode) 4,194,304 words by 16 bits (WORD mode) * Page access mode BYTE mode : 8 byte random page access (PD23C64340) 16 byte random page access (PD23C64380) WORD mode : 4 word random page access (PD23C64340) 8 word random page access (PD23C64380) * Operating supply voltage : VCC = 2.7 V to 3.6 V Operating supply Access time / Power supply current Standby current voltage Page access time (Active mode) (CMOS level input) VCC ns (MAX.) mA (MAX.) A (MAX.) PD23C64340 PD23C64380 3.0 V 0.3 V 100 / 25 40 60 3.3 V 0.3 V 90 / 25 55 75 30 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M16335EJ1V0DS00 (1st edition) Date Published July 2002 NS CP(K) Printed in Japan (c) 2002 PD23C64340, 23C64380 Ordering Information Part Number Package PD23C64340GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) PD23C64340F9-xxx-BC3 48-pin TAPE FBGA (8 x 6) Note PD23C64380GZ-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) PD23C64380F9-xxx-BC3 48-pin TAPE FBGA (8 x 6) Note Note Under development (xxx : ROM code suffix No.) Marking Image Part Number Marking ( PD23C64340F9-xxx-BC3 B PD23C64380F9-xxx-BC3 C ) J R64 -xxx ROM code suffix No. INDEX MARK 2 Lot No. Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 Pin Configurations (Marking Side) /xxx indicates active low signal. 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) [ PD23C64340GZ-xxx-MJH ] [ PD23C64380GZ-xxx-MJH ] A15 1 48 A16 A14 2 47 WORD, /BYTE A13 3 46 GND A12 4 45 O15, A-1 A11 5 44 O7 A10 6 43 O14 A9 7 42 O6 A8 8 41 O13 A19 9 40 O5 A20 10 39 O12 NC 11 38 O4 NC 12 37 VCC A21 13 36 O11 NC 14 35 O3 NC 15 34 O10 A18 16 33 O2 A17 17 32 O9 A7 18 31 O1 A6 19 30 O8 A5 20 29 O0 A4 21 28 /OE, OE, DC A3 22 27 GND A2 23 26 /CE A1 24 25 A0 A0 - A21 : Address inputs O0 - O7, O8 - O14 : Data outputs O15, A-1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE, OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don't Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M16335EJ1V0DS 3 PD23C64340, 23C64380 48-pin TAPE FBGA (8 x 6) [ PD23C64340F9-xxx-BC3 ] [ PD23C64380F9-xxx-BC3 ] Top View Bottom View 6 5 4 3 2 1 A 6 B C D E F G H H A B C D E F G H A13 A12 A14 A15 A16 WORD, O15, GND /BYTE A-1 6 G F E D C B A H G F E D C B A GND O15, WORD, A16 A15 A14 A12 A13 A-1 /BYTE 5 A9 A8 A10 A11 O7 O14 O13 O6 5 O6 O13 O14 O7 A11 A10 A8 A9 4 NC NC A21 A19 O5 O12 VCC O4 4 O4 VCC O12 O5 A19 A21 NC NC 3 NC NC A18 A20 O2 O10 O11 O3 3 O3 O11 O10 O2 A20 A18 NC NC 2 A7 A17 A6 A5 O0 O8 O9 O1 2 O1 O9 O8 O0 A5 A6 A17 A7 1 A3 A4 A2 A1 A0 /CE /OE, OE GND 1 GND /OE, OE /CE A0 A1 A2 A4 A3 A0 - A21 : Address inputs O0 - O7, O8 - O14 : Data outputs O15, A-1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE, OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don't Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the index mark. 4 Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 Input / Output Pin Functions Pin name WORD, /BYTE Input / Output Input Function The pin for switching WORD mode and BYTE mode. High level : WORD mode (4M-word by 16-bit) Low level : BYTE mode (8M-word by 8-bit) A0 to A21 Input (Address inputs) Address input pins. A0 to A21 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) A0 to A21 are used as 22 bits address signals. BYTE mode (8M-word by 8-bit) A0 to A21 are used as the upper 22 bits of total 23 bits of address signal. (The least significant bit (A-1) is combined to O15.) O0 to O7, O8 to O14 Output (Data outputs) Data output pins. O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) The lower 15 bits of 16 bits data outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode (8M-word by 8-bit) 8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. O15, A-1 Output, Input O15, A-1 are used differently in the WORD mode and the BYTE mode. WORD mode (4M-word by 16-bit) (Data output 15, LSB Address input) The most significant output data bus (O15). BYTE mode (8M-word by 8-bit) The least significant address bus (A-1). /CE Input (Chip Enable) Chip activating signal. When the OE is active, output states are following. High level : High impedance Low level : Data out /OE, OE, DC Input (Output Enable, Don't care) Output enable signal. The active level of OE is mask option. The active level of OE can be selected from high active, low active and Don't care at order. VCC - Supply voltage GND - Ground NC - Not internally connected. (The signal can be connected.) Data Sheet M16335EJ1V0DS 5 PD23C64340, 23C64380 Block Diagram O9 O8 O0 A0 O1 O10 O2 O11 O3 O13 O12 O4 O5 O6 O14 O15, A-1 O7 A2 A3 Y-Selector A4 Logic/Input Y-Decoder Output Buffer A1 WORD, /BYTE /OE, OE, DC A5 A9 A10 A11 A12 A13 Memory Cell Matrix 4,194,304 words by 16 bits / 8,388,608 words by 8 bits A14 A15 A16 A17 A18 A19 A20 A21 6 Data Sheet M16335EJ1V0DS Input Buffer A8 X-Decoder A7 Address Input Buffer A6 /CE PD23C64340, 23C64380 Mask Option The active levels of output enable pin (/OE, OE, DC) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. Option /OE, OE, DC OE active level 0 /OE L 1 OE H x DC Don't care Operation modes for each option are shown in the tables below. Operation mode (Option : 0) /CE /OE Mode Output state L L Active Data out H H H or L High impedance Standby High impedance Operation mode (Option : 1) /CE OE Mode Output state L L Active High impedance H H H or L Data out Standby High impedance Operation mode (Option : x) /CE DC Mode Output state L H or L Active Data out H H or L Standby High impedance Remark L : Low level input H : High level input Data Sheet M16335EJ1V0DS 7 PD23C64340, 23C64380 Electrical Specifications Absolute Maximum Ratings Parameter Symbol Rating Unit VCC -0.3 to +4.6 V Input voltage VI -0.3 to VCC+0.3 V Output voltage VO -0.3 to VCC+0.3 V Operating ambient temperature TA -10 to +70 C Storage temperature Tstg -65 to +150 C Supply voltage Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 C) Parameter Symbol MAX. Unit 10 pF 12 pF MAX. Unit 2.0 VCC + 0.3 V VCC = 3.0 V 0.3 V -0.3 +0.5 V VCC = 3.3 V 0.3 V -0.3 +0.8 2.4 Input capacitance CI Output capacitance CO Test condition MIN. TYP. f = 1 MHz DC Characteristics (TA = -10 to +70 C, VCC = 2.7 to 3.6 V) Parameter Symbol High level input voltage VIH Low level input voltage VIL Test conditions High level output voltage VOH IOH = -100 A Low level output voltage VOL IOL = 2.1 mA MIN. TYP. V 0.4 V Input leakage current ILI VI = 0 V to VCC -10 +10 A Output leakage current ILO VO = 0 V to VCC, Chip deselected -10 +10 A Power supply current ICC1 /CE = VIL PD23C64340 VCC = 3.0 V 0.3 V 40 mA VCC = 3.3 V 0.3 V 55 PD23C64380 VCC = 3.0 V 0.3 V 60 VCC = 3.3 V 0.3 V 75 (Active mode), IO = 0 mA Standby current 8 ICC3 /CE = VCC - 0.2 V (Standby mode) Data Sheet M16335EJ1V0DS 30 A PD23C64340, 23C64380 AC Characteristics (TA = -10 to +70 C, VCC = 2.7 to 3.6 V) Parameter Symbol Test condition VCC = 3.0 V 0.3 V MIN. TYP. MAX. VCC = 3.3 V 0.3 V MIN. TYP. Unit MAX. Address access time tACC 100 90 ns Page access time tPAC 25 25 ns Chip enable access time tCE 100 90 ns Output enable access time tOE 25 25 ns Output hold time tOH 0 Output disable time tDF 0 WORD, /BYTE access time tWB Remark 0 25 0 100 ns 25 ns 90 ns tDF is the time from inactivation of /CE or /OE, OE to high-impedance state output. AC Test Conditions Input waveform (Rise / Fall time 5 ns) 1.4 V Test points 1.4 V 1.4 V Test points 1.4 V Output waveform Output load 1TTL + 100 pF Data Sheet M16335EJ1V0DS 9 PD23C64340, 23C64380 Read Cycle Timing Chart 1 A0 to A21, (Input) A-1 Note 1 tACC /CE (Input) tDF Note 2 tCE /OE, OE (Input) tOE O0 to O7, (Output) O8 to O15 Note 3 High impedance tOH Data Out Notes 1. During WORD mode, A-1 is O15. 2. tDF is specified when one of /CE, /OE, OE is inactivated. 3. During BYTE mode, O8 to O14 are high impedance and O15 is A-1. 10 Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 Read Cycle Timing Chart 2 (Page Access Mode) Upper addressNote 1 (Input) A2 to A21 A3 to A21 tACC /CE (Input) tCE /OE, OE (Input) tOE Page addressNote 1 (Input) A-1Note 2, A0, A1 A-1Note 2, A0, A1, A2 tPAC Note 5 tPAC Note 5 tDF Note 3 tOH tOH O0 to O7, (Output) O8 to O15Note 4 tOH High impedance High impedance Data Out Data Out Data Out Notes 1. The address differs depending on the product as follows. Part Number Upper address Page address PD23C64340 A2 to A21 A-1, A0, A1 PD23C64380 A3 to A21 A-1, A0, A1, A2 2. During WORD mode, A-1 is O15. 3. tDF is specified when one of /CE, /OE, OE is inactivated. 4. During BYTE mode, O8 to O14 are high impedance and O15 is A-1. 5. The definition of page access time is as follows. [ PD23C64340 ] Page access time Upper address (A2 to A21) /CE input condition /OE, OE input condition Before tCE - tPAC Before stabilizing of page inputs condition tPAC Before tACC - tPAC address (A-1, A0, A1) [ PD23C64380 ] Page access time Upper address (A3 to A21) /CE input condition /OE, OE input condition Before tCE - tPAC Before stabilizing of page inputs condition tPAC Before tACC - tPAC address (A-1, A0, A1, A2) Data Sheet M16335EJ1V0DS 11 PD23C64340, 23C64380 WORD, /BYTE Switch Timing Chart A-1 (Input) High impedance High impedance WORD, /BYTE (Input) tOH O0 to O7 (Output) Data Out tACC tOH Data Out tWB Data Out tDF O8 to O15 (Output) Data Out High impedance Remark /OE, OE and /CE : Active. 12 Data Sheet M16335EJ1V0DS Data Out PD23C64340, 23C64380 Package Drawings 48-PIN PLASTIC TSOP (I) (12x20) detail of lead end 1 48 F G R Q 24 L 25 S E P I A J C S K N S NOTES 1) Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2) "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) B D M M ITEM A MILLIMETERS 12.00.1 B 0.45 MAX. C 0.5 (T.P.) D 0.220.05 E 0.10.05 F 1.2 MAX. G 1.00.05 I 18.40.1 J 0.80.2 K 0.1450.05 L 0.5 M 0.10 N 0.10 P 20.00.2 Q 3 +5 -3 R 0.25 S 0.600.15 S48GZ-50-MJH-1 Data Sheet M16335EJ1V0DS 13 PD23C64340, 23C64380 48-PIN TAPE FBGA(8x6) ZD w S B E ZE B 6 5 4 3 2 1 A D H G F E D C B A INDEX MARK w S A INDEX MARK A y1 A2 S S y e S b x A1 M S AB ITEM D MILLIMETERS 6.00.1 E 8.00.1 w 0.2 e 0.80 A 0.970.10 A1 0.270.05 A2 0.70 b 0.450.05 x 0.08 y 0.1 y1 0.2 ZD 1.00 ZE 1.20 P48F9-80-BC3 14 Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the PD23C64340 and PD23C64380. Types of Surface Mount Device PD23C64340GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) PD23C64340F9-BC3 : 48-pin TAPE FBGA (8 x 6) PD23C64380GZ-MJH : 48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent) PD23C64380F9-BC3 : 48-pin TAPE FBGA (8 x 6) Data Sheet M16335EJ1V0DS 15 PD23C64340, 23C64380 [MEMO] 16 Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 [MEMO] Data Sheet M16335EJ1V0DS 17 PD23C64340, 23C64380 [MEMO] 18 Data Sheet M16335EJ1V0DS PD23C64340, 23C64380 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M16335EJ1V0DS 19 PD23C64340, 23C64380 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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