LTC2228/LTC2227/LTC2226
1
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TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
12-Bit, 65/40/25Msps
Low Power 3V ADCs
The LTC
®
2228/LTC2227/LTC2226 are 12-bit 65Msps/
40Msps/25Msps, low power 3V A/D converters designed
for digitizing high frequency, wide dynamic range signals.
The LTC2228/LTC2227/LTC2226 are perfect for demand-
ing imaging and communications applications with AC
performance that includes 71.3dB SNR and 90dB SFDR
for signals at the Nyquist frequency.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance
at full speed for a wide range of clock duty cycles.
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
n Sample Rate: 65Msps/40Msps/25Msps
n Single 3V Supply (2.7V to 3.4V)
n Low Power: 205mW/120mW/75mW
n 71.3dB SNR
n 90dB SFDR
n No Missing Codes
n Flexible Input: 1VP-P to 2VP-P Range
n 575MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
n 32-Pin (5mm × 5mm) QFN Package
n Wireless and Wired Broadband Communication
n Imaging Systems
n Ultrasound
n Spectral Analysis
n Portable Instrumentation
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
–
+
INPUT
S/H
CORRECTION
LOGIC OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D11
•
•
•
D0
CLK
REFH
REFL
ANALOG
INPUT
222876 TA01
OVDD
OGND
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
71
200
2228 G09
69
68 50 100 150
72
LTC2228/LTC2227/LTC2226
2
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PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage ......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range
LTC2228C, LTC2227C, LTC2226C............. 0°C to 70°C
LTC2228I, LTC2227I, LTC2226I ............ –40°C to 85°C
Storage Temperature Range ................... –65°C to 125°C
OVDD = VDD (Notes 1, 2)
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1AIN+
AIN–
REFH
REFH
REFL
REFL
VDD
GND
D8
D7
D6
OVDD
OGND
D5
D4
D3
VDD
VCM
SENSE
MODE
OF
D11
D10
D9
CLK
SHDN
OE
NC
NC
D0
D1
D2
33
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2228CUH#PBF LTC2228CUH#TRPBF 2228 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2228IUH#PBF LTC2228IUH#TRPBF 2228 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC2227CUH#PBF LTC2227CUH#TRPBF 2227 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2227IUH#PBF LTC2227IUH#TRPBF 2227 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC2226CUH#PBF LTC2226CUH#TRPBF 2226 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2226IUH#PBF LTC2226IUH#TRPBF 2226 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2228CUH LTC2228CUH#TR 2228 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2228IUH LTC2228IUH#TR 2228 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC2227CUH LTC2227CUH#TR 2227 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2227IUH LTC2227IUH#TR 2227 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC2226CUH LTC2226CUH#TR 2226 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C
LTC2226IUH LTC2226IUH#TR 2226 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
LTC2228/LTC2227/LTC2226
3
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CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS
LTC2228 LTC2227 LTC2226
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution
(No Missing Codes)
l12 12 12 Bits
Integral
Linearity Error
Differential Analog Input (Note 5) l–1.1 ±0.3 1.1 –1 ±0.3 1 –1 ±0.3 1 LSB
Differential
Linearity Error
Differential Analog Input l–0.8 ±0.15 0.8 –0.7 ±0.15 0.7 –0.7 ±0.15 0.7 LSB
Offset Error (Note 6) l–12 ±2 12 –12 ±2 12 –12 ±2 12 mV
Gain Error External Reference l–2.5 ±0.5 2.5 –2.5 ±0.5 2.5 –2.5 ±0.5 2.5 %FS
Offset Drift ±10 ±10 ±10 μV/°C
Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C
External Reference ±5 ±5 ±5 ppm/°C
Transition Noise SENSE = 1V 0.25 0.25 0.25 LSBRMS
ANALOG INPUT
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 2.7V < VDD < 3.4V (Note 7) l±0.5V to ±1V V
VIN,CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7)
Single-Ended Input (Note 7)
l
l
1
0.5
1.5
1.5
1.9
2
V
V
IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD l–1 1 μA
ISENSE SENSE Input Leakage 0V < SENSE < 1V l–3 3 μA
IMODE MODE Pin Leakage l–3 3 μA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
Full Power Bandwidth Figure 8 Test Circuit 575 MHz
DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS
LTC2228 LTC2227 LTC2226
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 5MHz Input 71.3 71.4 71.4 dB
12.5MHz Input l70.2 71.2 dB
20MHz Input l70.1 71.3 dB
30MHz Input l70 71.3 dB
70MHz Input 71.3 71.1 70.9 dB
140MHz Input 71 70.7 70.6 dB
SFDR Spurious Free
Dynamic Range
2nd or 3rd
Harmonic
5MHz Input 90 90 90 dB
12.5MHz Input l76 90 dB
20MHz Input l76 90 dB
30MHz Input l75 90 dB
70MHz Input 85 85 85 dB
140MHz Input 80 80 80 dB
LTC2228/LTC2227/LTC2226
4
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DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS
LTC2228 LTC2227 LTC2226
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
SFDR Spurious Free
Dynamic Range
4th Harmonic
or Higher
5MHz Input 95 95 95 dB
12.5MHz Input l82 95 dB
20MHz Input l82 95 dB
30MHz Input l82 95 dB
70MHz Input 95 95 95 dB
140MHz Input 90 90 90 dB
S/(N+D) Signal-to-Noise
Plus Distortion
Ratio
5MHz Input 71.3 71.4 71.4 dB
12.5MHz Input l69.8 71.2 dB
20MHz Input l69.7 71.2 dB
30MHz Input l69.6 71.2 dB
70MHz Input 71.1 70.9 70.8 dB
140MHz Input 69.9 69.9 69.8 dB
IMD Intermodulation
Distortion
fIN1 = 28.2MHz,
fIN2 = 26.8MHz
90 90 90 dB
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V
VCM Output Tempco ±25 ppm/°C
VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V
VCM Output Resistance –1mA < IOUT < 1mA 4 Ω
INTERNAL REFERENCE CHARACTERISTICS
(Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
VIH High Level Input Voltage VDD = 3V l2V
VIL Low Level Input Voltage VDD = 3V l0.8 V
IIN Input Current VIN = 0V to VDD l–10 10 μA
CIN Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS
OVDD = 3V
COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF
ISOURCE Output Source Current VOUT = 0V 50 mA
ISINK Output Sink Current VOUT = 3V 50 mA
VOH High Level Output Voltage IO = –10μA
IO = –200μA l2.7
2.995
2.99
V
V
VOL Low Level Output Voltage IO = 10μA
IO = 1.6mA l
0.005
0.09 0.4
V
V
OVDD = 2.5V
VOH High Level Output Voltage IO = –200μA 2.49 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V
OVDD = 1.8V
VOH High Level Output Voltage IO = –200μA 1.79 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V
LTC2228/LTC2227/LTC2226
5
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POWER REQUIREMENTS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS
LTC2228 LTC2227 LTC2226
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
VDD Analog Supply Voltage (Note 9) l2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 V
OVDD Output Supply Voltage (Note 9) l0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 V
IVDD Supply Current l68.3 80 40 48 25 30 mA
PDISS Power Dissipation l205 240 120 144 75 90 mW
PSHDN Shutdown Power SHDN = H, OE = H,
No CLK
222mW
PNAP Nap Mode Power SHDN = H, OE = L,
No CLK
15 15 15 mW
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS
LTC2228 LTC2227 LTC2226
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
fSSampling Frequency (Note 9) l1 65 1 40 1 25 MHz
tLCLK Low Time Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
7.3
5
7.7
7.7
500
500
11.8
5
12.5 500
500
18.9
5
20
20
500
500
ns
ns
tHCLK High Time Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
l
l
7.3
5
7.7
7.7
500
500
11.8
5
12.5
12.5
500
500
18.9
5
20
20
500
500
ns
ns
tAP Sample-and-Hold
Aperture Delay
000ns
tDCLK to DATA Delay CL = 5pF (Note 7) l1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns
Data Access Time
After OE↓
CL = 5pF (Note 7) l4.3 10 4.3 10 4.3 10 ns
BUS Relinquish Time (Note 7) l3.3 8.5 3.3 8.5 3.3 8.5 ns
Pipeline
Latency
5 5 5 Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 2VP-P with differential drive, unless
otherwise noted.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code fl ickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 65MHz (LTC2228), 40MHz (LTC2227), or
25MHz (LTC2226), input range = 1VP-P with differential drive.
Note 9: Recommend operating conditions.
LTC2228/LTC2227/LTC2226
6
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC2228: Typical INL, 2V Range,
65Msps
LTC2228: Typical DNL, 2V Range,
65Msps
LTC2228: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
65Msps
LTC2228: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
65Msps
LTC2228: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range, 65Msps
LTC2228: Grounded Input
Histogram, 65Msps
LTC2228: SNR vs Input Frequency,
–1dB, 2V Range, 65Msps
CODE
0
INL ERROR (LSB)
3072
2228 G01
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
CODE
0
DNL ERROR (LSB)
3072
2228 G02
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
FREQUENCY (MHz)
0
2228 G03
51015
AMPLITUDE (dB)
20 25 30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
LTC2228: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
65Msps
LTC2228: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
65Msps
FREQUENCY (MHz)
0
2228 G04
51015
AMPLITUDE (dB)
20 25 30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
2228 G05
51015
AMPLITUDE (dB)
20 25 30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
2228 G06
51015
AMPLITUDE (dB)
20 25 30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
2228 G07
51015
AMPLITUDE (dB)
20 25 30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
CODE
70000
60000
50000
40000
30000
20000
10000
02043
61496
2044
2228 G08
2042
2123
COUNT
1910
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
71
200
2228 G09
69
68 50 100 150
72
LTC2228/LTC2227/LTC2226
7
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC2228: SFDR vs Input Frequency,
–1dB, 2V Range, 65Msps
LTC2228: SNR and SFDR vs Clock
Duty Cycle, 65Msps
LTC2228: SNR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
LTC2228: SFDR vs Input Level,
fIN = 30MHz, 2V Range, 65Msps
LTC2228: IVDD vs Sample Rate,
5mHz Sine Wave Input, –1dB
LTC2228: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2228: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
INPUT FREQUENCY (MHz)
0
100
95
90
85
80
75
70
65 150
2228 G10
50 100 200
SFDR (dBFS)
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
110
100
90
80
70
60 80
2228 G11
20 40 60 100
SNR
SFDR
CLOCK DUTY CYCLE (%)
30
SNR AND SFDR (dBFS)
60
2228 G12
40 50 70
100
95
90
85
80
75
70
65 35 45 55 65
SFDR: DCS ON
SFDR: DCS OFF
SNR: DCS ON
SNR: DCS OFF
INPUT LEVEL (dBFS)
–60 –50
SNR (dBc AND dBFS)
–40 –20–30 –10 0
2228 G13
80
70
60
50
40
30
20
10
0
dBFS
dBc
INPUT LEVEL (dBFS)
–60 –50 –40 –20–30 –10 0
SFDR (dBc AND dBFS)
2228 G14
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
SAMPLE RATE (Msps)
0
80
75
70
65
60
55
50 60
2228 G15
20 40 805010 30 70
IVDD (mA)
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
IOVDD (mA)
2228 G16
6
5
4
3
2
1
0020 40 50
10 30 60 70 80
LTC2228/LTC2227/LTC2226
8
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC2227: Typical INL, 2V Range,
40Msps
LTC2227: Typical DNL, 2V Range,
40Msps
LTC2227: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
40Msps
LTC2228: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
40Msps
LTC2227: 8192 Point 2-Tone FFT,
fIN = 21.6MHz and 23.6MHz,
–1dB, 2V Range, 40Msps
LTC2227: Grounded Input
Histogram, 40Msps
LTC2227: SNR vs Input Frequency,
–1dB, 2V Range, 40Msps
LTC2227: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
40Msps
LTC2227: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
40Msps
CODE
0
INL ERROR (LSB)
3072
2227 G01
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
CODE
0
DNL ERROR (LSB)
3072
2227 G02
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2227 G03
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2227 G04
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2227 G05
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2227 G06
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2227 G07
5101520
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
CODE
2050
COUNT
2227 G08
2051 2052
70000
60000
50000
40000
30000
20000
10000
0
1424
61538
2558
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
71
200
2227 G09
69
68 50 100 150
72
LTC2228/LTC2227/LTC2226
9
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TYPICAL PERFORMANCE CHARACTERISTICS
LTC2227: SFDR vs Input Frequency,
–1dB, 2V Range, 40Msps
LTC2227: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
LTC2227: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2227: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
INPUT FREQUENCY (MHz)
0
100
95
90
85
80
75
70
65 150
2227 G10
50 100 200
SFDR (dBFS)
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
110
100
90
80
70
60
2227 G11
4020 60 80
SNR
SFDR
LTC2227: SNR vs Input Level,
fIN = 5MHz, 2V Range, 40Msps
INPUT LEVEL (dBFS)
–60 –50
SNR (dBc AND dBFS)
–40 –20–30 –10 0
2227 G12
80
70
60
50
40
30
20
10
0
dBFS
dBc
2227 G13
INPUT LEVEL (dBFS)
–60 –50 –40 –20–30 –10 0
SNR (dBc AND dBFS)
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
2227 G14
SAMPLE RATE (Msps)
0
50
45
40
35
30 20 40 5010 30
IVDD (mA)
2V RANGE
1V RANGE
LTC2227: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
2227 G15
SAMPLE RATE (Msps)
IOVDD (mA)
4
3
2
1
0020 40 50
10 30
LTC2228/LTC2227/LTC2226
10
222876fb
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2226: Typical INL, 2V Range,
25Msps
LTC2226: Typical DNL, 2V Range,
25Msps
LTC2226: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
25Msps
LTC2226: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
25Msps
LTC2226: 8192 Point 2-Tone FFT,
fIN = 10.9MHz and 13.8MHz,
–1dB, 2V Range, 25Msps
LTC2226: Grounded Input
Histogram, 25Msps
LTC2226: SNR vs Input Frequency,
–1dB, 2V Range, 25Msps
LTC2226: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
25Msps
LTC2226: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
25Msps
CODE
0
INL ERROR (LSB)
3072
2226 G01
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
CODE
0
DNL ERROR (LSB)
3072
2226 G02
1024 2048 4096
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226 G03
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226 G04
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226 G05
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226 G06
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FREQUENCY (MHz)
0
AMPLITUDE (dB)
2226 G07
24 6810
12
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
CODE
COUNT
2050
2226 G08
2048 2049
70000
60000
50000
40000
30000
20000
10000
0
61758
1607
2155
INPUT FREQUENCY (MHz)
0
SNR (dBFS)
70
71
200
2226 G09
69
68 50 100 150
72
LTC2228/LTC2227/LTC2226
11
222876fb
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2226: SFDR vs Input Frequency,
–1dB, 2V Range, 25Msps
LTC2226: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
LTC2226: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2226: SNR and SFDR vs Sample
Rate, 2V Range,fIN = 5MHz, –1dB
LTC2226: SNR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
LTC2226: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
INPUT FREQUENCY (MHz)
0
100
95
90
85
80
75
70
65 150
2226 G10
50 100 200
SFDR (dBFS)
SAMPLE RATE (Msps)
0
SNR AND SFDR (dBFS)
110
100
90
80
70
60 40 50
2226 G11
10 20 30
SNR
SFDR
INPUT LEVEL (dBFS)
–60 –50
SNR (dBc AND dBFS)
–40 –20–30 –10 0
2227 G12
80
70
60
50
40
30
20
10
0
dBFS
dBc
INPUT LEVEL (dBFS)
–60 –50 –40 –20–30 –10 0
SFDR (dBc AND dBFS)
2226 G13
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
SAMPLE RATE (Msps)
0
35
30
25
20
15 30
2226 G14
10 20 25515 35
IVDD (mA)
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
IOVDD (mA)
2226 G15
3
2
1
0020 30515 35
10 25
LTC2228/LTC2227/LTC2226
12
222876fb
PIN FUNCTIONS
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to Pins 5, 6 with a 0.1μF ceramic chip capacitor as
close to the pin as possible. Also bypass to Pins 5, 6 with
an additional 2.2μF ceramic chip capacitor and to ground
with a 1μF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to Pins 3, 4 with a 0.1μF ceramic chip capacitor as
close to the pin as possible. Also bypass to Pins 3, 4 with
an additional 2.2μF ceramic chip capacitor and to ground
with a 1μF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1μF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
NC (Pins 12, 13): Do Not Connect These Pins.
D0-D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1μF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under fl ow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
Exposed Pad (Pin 33): ADC Power Ground. The Exposed
Pad on the bottom of the package needs to be soldered
to ground.
LTC2228/LTC2227/LTC2226
13
222876fb
FUNCTIONAL BLOCK DIAGRAM
DIFF
REF
AMP
REF
BUF
2.2μF
1μF 1μF
0.1μF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH REFL
CLK
SHIFT REGISTER
AND CORRECTION
OEM0DE
OGND
OVDD
222876 F01
INPUT
S/H
SENSE
VCM
AIN–
AIN+
2.2μF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D11
D0
•
•
•
Figure 1. Functional Block Diagram
LTC2228/LTC2227/LTC2226
14
222876fb
TIMING DIAGRAM
tAP
N + 1
N + 2 N + 4
N + 3 N + 5
N
ANALOG
INPUT
tH
tD
tL
N – 4 N – 3 N – 2 N – 1
CLK
D0-D11, OF
222876 TD01
N – 5 N
Timing Diagram
LTC2228/LTC2227/LTC2226
15
222876fb
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the fi rst fi ve harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fi fth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defi ned as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spuri-
ous noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full-scale input signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full-scale input signal.
Aperture Delay Time
The time from when CLK reaches mid-supply to the in-
stant that the input signal is held by the sample-and-hold
circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
LTC2228/LTC2227/LTC2226
16
222876fb
APPLICATIONS INFORMATION
CONVERTER OPERATION
As shown in Figure 1, the LTC2228/LTC2227/LTC2226
is a CMOS pipelined multi-step converter. The converter
has six pipelined ADC stages; a sampled analog input will
result in a digitized value fi ve cycles later (see the Timing
Diagram section). For optimal AC performance the analog
inputs should be driven differentially. For cost sensitive
applications, the analog inputs can be driven single-ended
with slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2228/LTC2227/LTC2226 has two
phases of operation, determined by the state of the CLK
input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifi er.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifi er which drives the fi rst pipelined ADC
stage. The fi rst stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
fi rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fi fth stages, resulting in a fi fth stage residue
that is sent to the sixth stage ADC for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2228/
LTC2227/LTC2226 CMOS differential sample-and-hold.
The analog inputs are connected to the sampling capaci-
tors (CSAMPLE) through NMOS transistors. The capacitors
shown attached to each input (CPARASITIC) are the summa-
tion of all other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small, the charging glitch seen at the input will
be small. If the input change is large, such as the change
seen with input frequencies near Nyquist, then a larger
charging glitch will be seen.
VDD
VDD
VDD
15Ω
15Ω
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
4pF
CSAMPLE
4pF
LTC2228/27/26
AIN+
AIN–
CLK
222876 F02
Figure 2. Equivalent Input Circuit
LTC2228/LTC2227/LTC2226
17
222876fb
APPLICATIONS INFORMATION
Single-Ended Input
For cost-sensitive applications, the analog inputs can be
driven single ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be driven
differentially. Each input should swing ±0.5V for the 2V
range or ±0.25V for the 1V range, around a common mode
voltage of 1.5V. The VCM output pin (Pin 31) may be used
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2228/LTC2227/LTC2226 can
be infl uenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can infl uence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 4pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when CLK rises, holding the
sampled input on the sampling capacitor. Ideally the input
circuitry should be fast enough to fully charge the sam-
pling capacitor during the sampling period 1/(2FENCODE);
however, this is not always possible and the incomplete
settling may degrade the SFDR. The sampling glitch has
been designed to be as linear as possible to minimize the
effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2228/LTC2227/LTC2226 being
driven by an RF transformer with a center tapped sec-
ondary. The secondary center tap is DC biased with VCM,
setting the ADC input signal at its optimum DC level.
Terminating on the transformer secondary is desirable,
as this provides a common mode path for charging
glitches caused by the sample and hold. Figure 3 shows
a 1:1 turns ratio transformer. Other turns ratios can be
used if the source impedance seen by the ADC does not
exceed 100Ω for each ADC input. A disadvantage of us-
ing a transformer is the loss of low frequency response.
Most small RF transformers have poor performance at
frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifi er to
convert a single-ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
25Ω
25Ω 25Ω
25Ω
0.1μF
AIN+
AIN–
12pF
2.2μF
VCM
LTC2228/27/26
ANALOG
INPUT
0.1μF T1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222876 F03
Figure 3. Single-Ended to Differential Conversion Using a Transformer
LTC2228/LTC2227/LTC2226
18
222876fb
APPLICATIONS INFORMATION
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
25Ω
25Ω
12pF
2.2μF
VCM
LTC2228/27/26
222876 F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER AIN+
AIN–
Figure 4. Differential Drive with an Amplifi er
25Ω
0.1μF
ANALOG
INPUT
VCM
AIN+
AIN–
1k
12pF
222876 F05
2.2μF
1k
25Ω
0.1μF
LTC2228/27/26
Figure 5. Single-Ended Drive
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer
gives better high frequency response than a fl ux coupled
center tapped transformer. The coupling capacitors allow
the analog inputs to be DC biased at 1.5V. In Figure 8, the
series inductors are impedance matching elements that
maximize the ADC bandwidth.
25Ω
25Ω 12Ω
12Ω
0.1μF
AIN+
AIN–
8pF
2.2μF
VCM
LTC2228/27/26
ANALOG
INPUT
0.1μF
0.1μF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222876 F06
Figure 6. Recommended Front-End Circuit for
Input Frequencies Between 70MHz and 170MHz
25Ω
25Ω
0.1μF
AIN+
AIN–
2.2μF
VCM
LTC2228/27/26
ANALOG
INPUT
0.1μF
0.1μF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
222876 F07
Figure 7. Recommended Front-End Circuit for
Input Frequencies Between 170MHz and 300MHz
25Ω
25Ω
0.1μF
AIN+
AIN–
2.2μF
VCM
LTC2228/27/26
ANALOG
INPUT
0.1μF
0.1μF
T1
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
222876 F08
6.8nH
6.8nH
Figure 8. Recommended Front-End Circuit for
Input Frequencies Above 300MHz
LTC2228/LTC2227/LTC2226
19
222876fb
TYPICAL APPLICATIONS
Reference Operation
Figure 9 shows the LTC2228/LTC2227/LTC2226 refer-
ence circuitry consisting of a 1.5V bandgap reference,
a difference amplifi er and switching and control circuit.
The internal voltage reference can be confi gured for two
pin selectable input ranges of 2V (±1V differential) or 1V
(±0.5V differential). Tying the SENSE pin to VDD selects
the 2V range; tying the SENSE pin to VCM selects the 1V
range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifi er to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
The difference amplifi er generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by ap-
plying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1μF
ceramic capacitor.
VCM
REFH
SENSE
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
1.5V
REFL
2.2μF
2.2μF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1μF
222876 F09
LTC2228/27/26
4Ω
DIFF AMP
1μF
1μF
INTERNAL ADC
LOW REFERENCE
1.5V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
Figure 9. Equivalent Reference Circuit
VCM
SENSE
1.5V
0.75V
2.2μF
12k
1μF
12k
222876 F10
LTC2228/27/26
Figure 10. 1.5V Range ADC
LTC2228/LTC2227/LTC2226
20
222876fb
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB. See the Typical Performance
Characteristics section.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
The noise performance of the LTC2228/LTC2227/LTC2226
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digi-
tizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, fi lter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass fi lter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for refl ections.
APPLICATIONS INFORMATION
CLK
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
222876 F11
LTC2228/
LTC2227/
LTC2226
0.1μF
0.1μF
SINUSOIDAL
CLOCK INPUT
4.7μF
NC7SVU04
50Ω
Figure 11. Single-Ended CLK Drive
CLK
100Ω
0.1μF
4.7μF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
223876 F12
LTC2238/
LTC2237/
LTC2236
CLK
5pF-30pF
ETC1-1T
0.1μF
VCM
FERRITE
BEAD
DIFFERENTIAL
CLOCK
INPUT
223876 F13
LTC2238/
LTC2237/
LTC2236
Figure 13. LVDS or PECL CLK Drive Using a Transformer
Figure 12. CLK Drive Using an LVDS or PECL-to-CMOS Converter
LTC2228/LTC2227/LTC2226
21
222876fb
APPLICATIONS INFORMATION
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2228/LTC2227/
LTC2226 is 65Msps (LTC2228), 40Msps (LTC2227), and
25Msps (LTC2226). For the ADC to operate properly, the
CLK signal should have a 50% (±5%) duty cycle. Each
half cycle must have at least 7.3ns (LTC2228), 11.8ns
(LTC2227), and 18.9ns (LTC2226) for the ADC internal cir-
cuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary from 40% to 60% and the clock
duty cycle stabilizer will maintain a constant 50% internal
duty cycle. If the clock is turned off for a long period of
time, the duty cycle stabilizer circuit will require a hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2228/LTC2227/LTC2226 sample
rate is determined by droop of the sample-and-hold circuits.
The pipelined architecture of this ADC relies on storing
analog signals on small-valued capacitors. Junction leak-
age will discharge the capacitors. The specifi ed minimum
operating frequency for the LTC2228/LTC2227/LTC2226
is 1Msps.
LTC2228/27/26
222876 F14
OVDD
VDD VDD
0.1μF
43Ω TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 14. Digital Output Buffer
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overfl ow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE) OF
D11-D0
(OFFSET BINARY)
D11-D0
(2’s COMPLEMENT)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
LTC2228/LTC2227/LTC2226
22
222876fb
APPLICATIONS INFORMATION
digital outputs of the LTC2228/LTC2227/LTC2226 should
drive a minimal capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2228/LTC2227/LTC2226
parallel digital output can be selected for offset binary
or 2’s complement format. Connecting MODE to GND or
1/3VDD selects offset binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 2 shows the logic
states for the MODE pin.
Table 2. MODE Pin Function
MODE PIN OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0 Offset Binary Off
1/3VDD Offset Binary On
2/3VDD 2’s Complement On
VDD 2’s Complement Off
Overfl ow Bit
When OF outputs a logic high the converter is either over-
ranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to VDD
and OE to GND results in nap mode, which typically dis-
sipates 15mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap modes, all digital outputs are disabled
and enter the Hi-Z state.
Grounding and Bypassing
The LTC2228/LTC2227/LTC2226 require a printed circuit
board with a clean, unbroken ground plane. A multilayer
board with an internal ground plane is recommended.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much
as possible. In particular, care should be taken not to
run any digital track alongside an analog signal track or
underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1μF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2μF capacitor be-
tween REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
LTC2228/LTC2227/LTC2226
23
222876fb
TYPICAL APPLICATIONS
The LTC2228/LTC2227/LTC2226 differential inputs should
run parallel and close to each other. The input traces should
be as short as possible to minimize capacitance and to
minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTC2228/LTC2227/
LTC2226 is transferred from the die through the bottom-
side Exposed Pad and package leads onto the printed
circuit board. For good electrical and thermal performance,
the exposed pad should be soldered to a large grounded
pad on the PC board. It is critical that all ground pins are
connected to a ground plane of suffi cient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix
or Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable.
You must not allow the clock to overshoot the supplies or
performance will suffer. Do not fi lter the clock signal with
a narrow band fi lter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a fi lter
close to the ADC may be benefi cial. This fi lter should be
close to the ADC to both reduce roundtrip refl ection times,
as well as reduce the susceptibility of the traces between
the fi lter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing fl ip-fl op as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together, and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
LTC2228/LTC2227/LTC2226
24
222876fb
APPLICATIONS INFORMATION
1
2
C8
0.1μF
C11
0.1μF
3
4
5
VDD 7
VDD
VDD GND
9
32
VCM 31
30
29
33
JP2
OE
10
11
8
C7
2.2μF
C6
1μF
C9
1μF
C4
0.1μF
C2
12pF
VDD
VDD
VDD GND
JP1
SHDN
C15
2.2μF C16
0.1μF
C18
0.1μF
C25
4.7μF
E2
VDD
3V
E4
PWR
GND
VDD VCC
222876 TA02
C17 0.1μF
C20
0.1μF
C19
0.1μF
C14
0.1μF
R10
33Ω
E1
EXT REF
R14
1k
R15
1k
R16
1k
R7
1k
R8
49.9Ω
R3
24.9Ω
R2
24.9Ω
R6
24.9Ω
R1
OPT
R4
24.9Ω
R5
50Ω
T1
ETC1-1T
C1
0.1μF
C3
0.1μF
J3
CLOCK
INPUT
NC7SVU04
NC7SVU04
C13
0.1μF
C10
0.1μF
C5
4.7μF
6.3V
L1
BEAD
VDD
C12
0.1μF
R9
1k
J1
ANALOG
INPUT
AIN+
AIN–
REFH
REFH
6REFL
REFL
VDD
CLK
SHDN
VDD
VCM
SENSE
MODE
GND
LTC2228/LTC2227/
LTC2226
OE
D11
GND
D0
NC
NC
D1
D2
D3
D5
D4
D6
D8
D9
OF
OVDD VCC
OGND
D10
D7
26
25
12
13
14
15
17
16
18
22
23
27
28
21
20
24
19
OE1
I0
OE2
LE1
LE2
VCC
VCC
VCC
GND
GND
GND
I1
I2
I4
I3
I5
I7
I8
I12
I11
I10
I13
I14
I15
I9
O11
O10
I6
VCC
O0
GND
GND
GND
VCC
VCC
GND
34
45
39
42
25
48
24
1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
VCC
28
74VCX16373MTD
31
21
15
18
10
4
7
RN1C 33Ω
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
O1
O2
O4
O3
O5
O7
O8
O12
O13
O14
O15
O9
O6
25
23
27
29
31
33
35
37
39
21
19
15
17
13
9
7
1
3
5
2
4
11
26
24
30
28
34
32
38
40
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
3201S-40G1
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
36
A3
A2
A1
A0
SDA
WP
VCC
1
2
3
4
8
24LC025
7
6
5
SCL
22
20
16
18
14
10
8
6
12
1
2
3
5
••
4
VCM
12
VDD
VDD
34
2/3VDD
56
1/3VDD
78
GND
JP4 MODE
12
VDD
34
VCM
VDD
VCM
56
EXT REF
JP3 SENSE
RN1B 33Ω
RN1A 33Ω
RN2D 33Ω
RN2C 33Ω
RN2B 33Ω
RN2A 33Ω
RN3D 33Ω
RN3C 33Ω
RN3B 33Ω
RN3A 33Ω
RN4D 33Ω
RN4B 33Ω
RN4A 33Ω
R13
10k
R11
10k
R12
10k
RN4C 33Ω
RN1D 33Ω
C28
1μF
C27
0.01μF
VCC
VDD
NC7SV86P5X
BYP
GND
ADJ
OUT
SHDN
GND
IN
1
2
3
4
8
LT1763
7
6
5
GND
R18
100k
R17
105k
C26
10μF
6.3V
E3
GND C21
0.1μF
C22
0.1μF
C23
0.1μF
C24
0.1μF
LTC2228/LTC2227/LTC2226
25
222876fb
APPLICATIONS INFORMATION
Silkscreen Top Topside
Inner Layer 2 GND
LTC2228/LTC2227/LTC2226
26
222876fb
APPLICATIONS INFORMATION
Inner Layer 3 Power Bottomside
Silkscreen Bottom
LTC2228/LTC2227/LTC2226
27
222876fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 p0.05
3.50 REF
(4 SIDES)
4.10 p0.05
5.50 p0.05
0.25 p 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
R = 0.05
TYP
3.45 p 0.05
3.45 p 0.05
LTC2228/LTC2227/LTC2226
28
222876fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0608 REV B • PRINTED IN USA
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