Description
The A6280 is a 3 bit constant current LED driver that has a wide
range of output currents. The A6280 controls LED luminance
with a pulse width modulation (PWM) scheme that gives the
application the capability of displaying a billion colors. The
overall maximum current is set by an external resistor.
The LED luminance is controlled by performing PWM control
on the outputs. The luminance data of the PWM signal for each
LED is stored in three 10 bit registers. Each LED can be dot
corrected by a 7 bit scalar register that scales the maximum
current from 100% down to 36.5%. All the internal latched
registers are loaded by a 31 bit serial shift register. One bit is used
to control the type of data loaded into the registers, either dot
correction / clock divider ratio or luminance data. The remaining
30 bits are used for the data. This helps reduce the pin count
of the A6280. To further lower the A6280 pin count, the PWM
clock and the serial bus clock share the same pin and work
concurrently to control LED luminance and to load data.
The A6280 is designed to minimize the number of components
needed to drive LEDs with large pixel spacing. Several A6280s
can be daisy chained together and controlled by just four control
signals (Clock, Serial Data, Latch, and Output Enable). Each
of these inputs has buffered outputs on chip. Also, the VIN pin
A6280-DS, Rev. 1
Features and Benefits
▪ 5 to 17 V operation
▪ Wide output current range (10 to 150 mA per output)
▪ 3 × 7 bit Dot Correction current settings
▪ 31 bit shift register
▪ 3 ×10 bit PWM luminance settings
▪ Buffered output control pins
▪ Up to 5 MHz serial / PWM clock frequency
▪ Thermal Shutdown / UVLO
3 Bit Constant Current LED Driver with PWM Control
Continued on the next page…
Packages: 16 pin DIP (suffix A), and
16 pin QFN/MLP (suffix ES)
Application Diagram
ES, approximate scale 1:1
A6280
Clock
Data
Strobe
Output Enable
Microprocessor
Control Board
Clock Out
Data Out
Strobe Out
OE Out
Clock In
Data In
Strobe In
OE In
VLED
OutB
OutG
OutR
VIN
Power Supply Bus
A6280
Pixel Board #1
REXT
VREG
Clock Out
Data Out
Strobe Out
OE Out
Clock In
Data In
Strobe In
OE In
VLED
OutB
OutG
OutR
VIN
A6280
Pixel Board #2
REXT
VREG
Pixel Board #N
Cat5 UTP Cat5 UTP Cat5 UTP
Figure 1. Functional drawing of daisy chained display application. Additional pixel boards
with A6280 ICs can be applied.
3 Bit Constant Current LED Driver with PWM Control
A6280
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Part Number Packing* Mounting
A6280EA-T 25 pieces/tube 16 pin DIP
A6280EESTR-T 1500 pieces/reel 16 pin QFN/MLP
*Contact Allegro for additional packing options.
Selection Guide
can be tied to the LED voltage supply bus, thus eliminating the need
for a separate chip supply bus or an external linear regulator.
The A6280 is supplied in a 16 pin dual in line (DIP) package (suffix
‘A’) package and in a 16 lead QFN/MLP (suffix ‘ES’) package. The
packages are lead (Pb) free with 100% matte-tin leadframe plating.
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Supply Voltage VIN 17 V
Output Voltage VO–0.5 to 17 V
Output Current IO170 mA
Ground Current IGND 600 mA
Logic Input Voltage Range VI–0.3 to 7 V
Operating Ambient Temperature TARange E –40 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –40 to 150 ºC
Description (continued)
Thermal Characteristics
Characteristic Symbol Test Conditions* Rating Units
Package Thermal Resistance RθJA
Package A, 4 layer PCB 38 ºC/W
Package ES, 4 layer PCB 40 ºC/W
Package ES, 1 layer PCB with 1 in2
. Cu area 70 ºC/W
*For additional information, refer to the Allegro website.
0 255075100125150
Temperature (°C)
Power Dissipation, P
D
(mW)
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
Power Dissipation versus Ambient Temperature
(R
QJA
= 38 ºC/W)
Package A, 4 layer PCB
(R
QJA
= 40 ºC/W)
Package ES, 4 layer PCB
(R
QJA
= 70 ºC/W)
Package ES, 1 layer PCB
3 Bit Constant Current LED Driver with PWM Control
A6280
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal List Table
Name Number Description
A Package ES Package
OUT1 1 11 Sinking output terminal
OUT0 2 12 Sinking output terminal
SDO 3 13 Buffered serial data output after shift registers
LO 4 14 Buffered latch output
OEO 5 15 Buffered output enable output
CO 6 16 Buffered clock output
REXT 7 1 An external resistor at this terminal establishes overall output current
VREG 8 2 Regulator decoupling
LGND 9 3 Logic ground
VIN 10 4 Chip power supply voltage
CI 11 5 Serial and PWM clock input
OEI 12 6 Output enable input; when low (active), the output drivers are enabled;
when high (inactive), all output drivers are turned off (blanked)
LI 13 7 Latch input terminal; serial data is latched with high-level input
SDI 14 8 Serial data input to shift registers
OUT2 15 9 Sinking output terminal
PGND 16 10 Power ground
Pin-out Drawings
Package A
Package ES
OUT2OUT1OUT0
Regulator
Current
Regulator 0
Current
Regulator 1
Current
Regulator 2
Shift Registers
Latched Registers
LI
SDI
REXT
R
EXT
LGNDPGND
CI
LO
SDO
CO
OEO
OEI
VIN
VREG
Functional Block Diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
OUT2
SDI
LI
OEI
CI
VIN
LGND
OUT1
OUT0
SDO
LO
OEO
CO
REXT
VREG
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
CO
OEO
LO
SDO
CI
OEI
LI
SDI
OUT0
OUT1
PGND
OUT2
REXT
VREG
LGND
VIN
3 Bit Constant Current LED Driver with PWM Control
A6280
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
OPERATING CHARACTERISTICS, valid at TA = 25°C, VIN = 4.75 to 17.0 V, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ. Max. Units
ELECTRICAL CHARACTERISTICS
Quiescent Supply Current IDD fCLKIN = 0.0 Hz – – 5.0 mA
Operating Supply Current IDD fCLKIN = 5 Mhz – – 15.0 mA
Undervoltage Lockout VIN(UV)
VIN rising 3.5 – 4.5 V
VIN falling 3.0 – 4.0 V
VREG Voltage Range VREG IO =15 mA, VIN = 17 V 4.6 – 5.4 V
VREG Dropout Voltage VDO IO =15 mA, VIN = 4.75 V – 200 600 mV
Output Current (any single output) IO
REXT = 5 k, scalar = 100% 135 150.0 165 mA
REXT = 15 k44 – 54 mA
Output to Output Matching Error* Err Output to output variation—all outputs on, REXT = 5 k7– 7%
Output Voltage Range VDS(min) 1.0 – 3.0 V
Load Regulation I%Diff / VDS –±1±3%
Output Leakage Current IDSX VOH = 17 V – – 1.0 A
Logic Input Voltage VIH 2.0 – – V
VIL – – 0.8 V
Logic Input Voltage Hysteresis All digital inputs – 150 – mV
Logic Input Current IIN VIN = 0 to 5 V –20 – 20 A
Logic Output Voltage VOL VIN 5.0 V, IO = ±2 mA – – 0.4 V
VOH 3.8 – – V
Input Resistance RI
OEI pin, pull-up 150 300 600 k
LI pin, pull-down 100 200 400 k
Output Dot Correction Error REXT = 5 k; LSB – ±1 – bit
Thermal Shutdown Temperature TJTSD Temperature increasing – 165 – °C
Thermal Shutdown Hysteresis TJhys –15–°C
SWITCHING CHARACTERISTICS
Clock Hold Time tH(CLK) 20 – – ns
Data Setup Time tSU(D) 20 – – ns
Data Hold Time tH(D) 20 – – ns
Latch Setup Time tSU(LE) 20 – – ns
Latch Hold Time tH(LE) 20 – – ns
Output Enable Set Up Time tSU(OE) 40 – – ns
Output Enable Falling to Outputs Turning ON
Propagation Delay Time tP(OE)2 – 200 – ns
Clock to Output Propagation Delay Time tP(OUT) VDS = 1.0 V, IO = 150 mA – 200 – ns
Logic Output Fall Time tBF COB = 50 pF, 4.5 to 0.5 V – 50 100 ns
Logic Output Rise Time tBR COB = 50 pF, 0.5 to 4.5 V – 30 60 ns
Output Fall Time (Turn Off) tf
CO = 10 pF, 90% to 10% of IO = 10 mA – 10 – ns
CO = 10 pF, 90% to 10% of IO = 10 mA – 10 – ns
Output Rise Time (Turn On) tr
CO = 10 pF, 90% to 10% of IO = 10 mA – 50 – ns
CO = 10 pF, 90% to 10% of IO = 10 mA – 100 – ns
Clock Falling Edge to Serial Data Out
Propagation Delay Time tP(SDO) – 50 100 ns
Output Enable In to Output Enable Out
Propagation Delay tP(OE) – 50 100 ns
Latch In to Latch Out Propagation Delay tP(LE) – 50 100 ns
Clock In to Clock Out Propagation Delay tP(CLK) – 50 100 ns
Clock Out Pulse Duration tw(CLK) 70 100 130 ns
Maximum CLKIN Frequency fCLKIN – – 6 MHz
*Err = [IO
(min or max) – IO(av)] / IO(av).
3 Bit Constant Current LED Driver with PWM Control
A6280
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
15 16 30
Clock
Serial Data In
Serial Data Out
Latch Enable In
Latch Enable Out
D30 D28 D27 D26 D25 D24 D23 D22 D8 D7 D0
D30Don’t Care
t
w(CLK)
t
SU(D )
t
H( D)
t
P(SD O )
t
SU(L E )
t
H(LE)
t
P( LE)
D29
PWM Counter
Output Enable In
Output Enable Out
OUT0
Luminance Data= 0
OUT1
Luminance Data= 2
OUT2
Luminance Data= 1023
t
P(O E )
t
w(OE)
t
P(OUT)
Clock IN
t
0
0 1 2 1023 0 0X
T
1
T
2
T
N
t
P( OU T)
1 2
t
P(OUT)
t
P(OUT)
012345678
Figure 2. Shift Register Timing
Figure 3. PWM Counter and Output Timing
Timing Diagram
3 Bit Constant Current LED Driver with PWM Control
A6280
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Description
Cur
Reg2
Cur
Reg1
Latch In
Output
Enable In
Clock In
OutRext
0
Out
1
Out
2
Serial
Data Out
Output
Enable Out
Clock Out
Serial
Data In
Latch Out
GND
Cur
Reg0
Shift Registers
GND
Bit 30
“1”
“0”
La tc he d R e gisters
29 300 …….. 9 10 …….. 19 20 ……..
Current
Scalar 0
7bits
PWM Counter2
10bits
PWM Counter1
10 bits
PWM Counter0
10 bits
Clock
Divider
2bits
Unused
1bit
Current
Scalar 1
7bits
Unused
3bit
Vin
Regulator
Vreg
Current
Scalar2
7bits
Test
Bit
1bit
Test
Bit
1bit
Unused
1bit
Figure 4. Functional Diagram
Shift Registers
The A6280 has a 31 bit shift register that loads data through the
Serial Data In (SDI) pin. The shift registers operate by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 30)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of
the Clock In (CI) pin. The Serial Data Out (SDO) pin is updated
to the state of bit 30 on the falling edge of the CI pin. This will
prevent any race conditions and erroneous data that might occur
while propagating information through multiple A6280 that are
daisy chained together. The contents of the shift registers will
continue to propagate on every rising edge of the CI pin. The
information in the shift registers is latched on a rising edge of the
Latch In (LI) pin. The latched data remains latched on a rising
Output Enable In (OEI) signal.
Output Buffers
The A6280 is designed to allow daisy chaining many A6280s
together. It has the ability to pass the clock, data, latch, and out-
put enable signals from one A6820 to the next without any loss of
data due to duty cycle skewing or signal degradation.
The A6820 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6280s
without the need for extra driving hardware. The A6280 drives
these signals to TTL levels. Each of the A6280 inputs have a cor-
responding buffered output:
• Clock In (CI) pin to Clock Out (CO) pin
• Latch In (LI) pin to Latch Out (LO) pin
• Output Enable In (OEI) pin to Output Enable Out (OEO) pin
• Serial Data In (SDI) pin to Serial Data Out (SDO) pin
3 Bit Constant Current LED Driver with PWM Control
A6280
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
PWM Luminance Control
The A6280 controls the intensity of each LED by PWMing the
current of each output. The A6280 has three 10 bit luminance
registers, one for each output. These luminance registers set the
PWM count value at which the outputs switch off during each
PWM cycle. Each 10 bit luminance register gives 1023 levels of
light intensity. The duty cycle, DC (%), can be determined by the
following equation:
DC = [(PWMn + 1) / 1024] ×100 ,
where PWMn is the PWM value greater than zero that is stored
in the luminance register. When the luminance register is set to
zero, the outputs remain off for the duration of the PWM cycle
for a 0% DC. When a luminance register is set to 1023, the LED
for that output remains on (100% DC) when OEI is active and
begins the PWM cycle. The output remains on when the PWM
counter rolls over and begins a new count.
The PWM counter begins counting at zero and increments only
when the OEI pin is held low. When the PWM counter reaches
the count of 1023, the counter resets to zero and continues
incrementing. The counter resets back to zero either on a rising
edge of OEI, upon recovery from UVLO, or when powering up.
Latching new data into the luminance registers will not reset the
PWM counter.
There is a programmable clock divider that attenuates the
clock input of the CI pin. See table 1 for bit assignments of the
programmable clock divider. The PWM counter is incremented
on every rising edge of the CI pin divided by the clock divider
count value when the OEI pin is low. For example, if the clock
divider is programmed to divide the CI by 2, then the PWM
counter will increment once every 2 CI cycles. Given a 5 MHz
CI frequency, the clock period would be 200 ns.
The clock divider data in the shift registers is latched on a rising
edge of the Latch In (LI) pin. The latched clock divider data
remains latched on a rising OEI signal.
The total number of possible colors of an RGB pixel is over
1 billion. Refer to figure 6 for the mapping of shift register bits
to latches.
Output Current Selection
The overall maximum current is set by the external resistor,
REXT , connected between REXT and LGND. Once set, the
maximum current remains constant regardless of the LED volt-
age variation, supply voltage variation, temperature, or other
circuit parameters that could otherwise affect LED current. The
maximum output current can be calculated using the following
equation:
IO(max) = 753.12 / REXT.
The relationship of the value selected for REXT and IO is shown
in figure 5.
Internal Linear Regulator
The A6280 has a built-in linear regulator. The regulator oper-
ates from 5 to 17 V, and is intended to allow the VIN pin of the
A6280 to connect to the same supply as the LEDs. This will
simplify board design by eliminating the need for a chip supply
bus and external voltage regulators.
The V
REG pin is used by the internal liner regulator as an
energy reservoir. This pin is for internal use only and is not
intended as an external power source. The V
REG pin should
have a 1.0 μF, 10 V ceramic capacitor connected between the
V
REG pin and LGND. The capacitor should be located as close
to the V
REG pin as possible.
Table 1. Clock Divider Configurations
Bits Divide By Count
78
0 0 ×1 (no division)
10 ×2
01 ×4
11 ×8
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
515253545556575
REXT (kΩ)
IO (mA)
Figure 5. Output Current versus External Resistor, REXT
3 Bit Constant Current LED Driver with PWM Control
A6280
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Dot Correction Control
The A6280 can further control the maximum output current for
each output by setting the three 7 bit dot correction registers with
scale data that ranges from 36.5% to 100% of the overall maxi-
mum output current that is set by the REXT resistor. This feature
is useful because not every type of LED (red, green, or blue, for
example) has the same level of brightness or intensity for any
given current, and the brightness could be different even from
LED to LED of the same type. By scaling the output currents so
that all the LEDs have matched intensities, the application will
have full color depth when using the PWM counters. The dot
correction current can be calculated by the following equation:
IOn = IOn(max) × (Scalen / 2 + 36.5)
Refer to figure 6 for the bit configurations for the scalar registers.
The dot correction data in the shift registers is latched on a rising
edge of the Latch In (LI) pin. The latched dot correction data
remains latched on a rising OEI signal. The default output cur-
rent when the A6280 is powered up or recovers from a UVLO is
36.5% of the current set by the REXT resistor.
Package Power Dissipation
The maximum allowable package power dissipation is deter-
mined as:
PD(max) = (150 – TA) / RθJA .
The actual package power dissipation is:
PD(act) = DC0 × VDS0 × IOUT0
+ DC1 × VDS1 × IOUT1
+ DC2 × VDS2 × IOUT2 + VIN × IIN .
When calculating power dissipation, the total number of avail-
able device outputs is usually used for the worst-case situation
(i.e., displaying all 3 LEDs at 100% DC).
Thermal Shutdown (TSD)
When the junction temperature of the A6280 reaches the thermal
shutdown temperature threshold, TJTSD (165°C typical), the
outputs will shut off until the junction temperature cools down
below the recovery threshold, –TJTSD –∆TJ ( 15°C typical). The
shift registers and output latches will remain active during the
TSD event. Therefore there is no need to reset the data in the
output latches.
Undervoltage Lockout
The A6280 includes an internal undervoltage lockout (UVLO)
circuit that disables the driver outputs in the event of the logic
supply voltage dropping below a minimum acceptable level.
This prevents the display of erroneous information, a necessary
function for some critical applications. The shift registers will
not shift any data in a UVLO condition. Upon recovery of the
logic supply voltage and on power up, all internal shift registers
and latches will be set to zero.
Ballast Resistors
The voltage on the outputs should be kept in the range 1 to 3 V.
If the voltage goes below 1V, the current will begin to rolloff
as the driver runs out of headroom. At VO above 3 V, the power
dissipation may become a problem, as each output contributes
VO × ILED of power loss in the output sink driver. Typically the
power supply nominal voltage is chosen to keep the output volt-
age in this range. Alternatively, series resistors can be added to
dissipate the extra power and keep the output voltage within the
recommended range.
Bits
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PWM Counter 0 PWM Counter 1 PWM Counter 2 0
Dot Correction
Register 0
Clock
Divider 0Dot Correction
Register 1 000 Dot Correction
Register 2 0 ATB* ATB* 1
*Allegro Test Bit (ATB). Reserved for Allegro internal testing. Always set to zero (0) in the application.
Figure 6. Register Configuration
3 Bit Constant Current LED Driver with PWM Control
A6280
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Clock
Data
Strobe
Output Enable
System Logic
CO
OEO
LO
SDO
A6280
ES A6280
ES
Maximum of
250 LEDs
Clock
Data
Strobe
Output Enable
System Logic
CO
OEO
LO
SDO
A6280
ES A6280
ES
Maximum of
250 LEDs
16
15
14
13
5
9
Tie LGND and PGND
to PAD externally
8.5 V
10 11 12
10 kΩ
1 μF
X5R
10 μF
VOn
1 to 3 V
432 1
6
7
8
CI
OEI
LI
PAD
SDI
Red
LEDs
Green
LEDs
Blue
LEDs
OUT2
PGND
OUT1
OUT0
REXT
VREG
LGND
VIN
16
15
14
13
5
9
10 V
10 11 12
5 kΩ
1 μF
10 V
10 μF
75 V
2 Ω
0.5 W
VOn
1 to 3 V
432 1
6
7
8
CI
OEI
LI
PAD
SDI
OUT2
PGND
OUT1
OUT0
REXT
VREG
LGND
VIN
Tie LGND and PGND
to PAD externally
+
–
+
–
Applications Drawings
Figure 7. Application Driving 3 RGB LEDs at 75 mA Peak
Figure 8. Application Driving High Power LED at 450 mA
3 Bit Constant Current LED Driver with PWM Control
A6280
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A Package, 16 Pin DIP
.070
.045 1.78
1.14
.150
.115 3.81
2.92
.195
.115 4.95
2.92
.014
.008 0.36
0.20
.430
MAX 10.92
.015
MIN 0.38
.005
MIN 0.13
.280
.240 7.11
6.10
.775
.735 19.69
18.67 AB
C
SEATING
PLANE
.022
.014 .056
.036
16X
.010 [0.25] M C
.100 .2.54
.300 .7.62
.210
MAX 5.33
21
16
A
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 BB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
3 Bit Constant Current LED Driver with PWM Control
A6280
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ES Package, 16 Pin QFN/MLP
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright©2006 Allegr oMicrosystems, Inc.
0.30
0.18
.012
.007
0.50
0.30
.020
.012
0.80
0.70
.031
.028
0.05
0.00
.002
.000
3.15
2.85
.124
.112
3.15
2.85
.124
.112
0.20
REF
.008
A
B
C
SEATING
PLANE
C0.08 [.003]
16X
16X
0.10 [.004] M C A B
0.05 [.002] M C
0.50 .020
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
Preliminary dimensions, for reference only
(reference JEDEC MO-220WEED-4)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M); adjust as necessary to
meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
16
2
1
A
16
1
2
B
1.70
NOM
.067
1.70
NOM
.067
0.23 x 0.23
REF
.009 x .009
1.70
NOM
.067
1.70
NOM
.067
0.30
NOM
.012
1
16
4X
12X 0.20
MIN
.008
16X 0.20
MIN
.008
0.50
NOM
.020
0.90
NOM
.035
0.20
MIN
.008
3.10
NOM
.122
3.10
NOM
.122
C
