DESCRIPTION
Demonstration circuit DC1513 is an evaluation board
featuring Linear Technology Corporation’s LTM9004 14-
Bit Direct Conversion Receiver Subsystem. DC1513
demonstrates good circuit layout techniques and rec-
ommended external circuitry for optimal system per-
formance.
DC1513 comes with Linear Technology’s 14-bit
LTM9004 receiver subsystem installed. The board in-
cludes output CMOS buffers.
DC1513 plugs into the
DC890 Data Acquisition demo board and the output can
be easily analyzed with Linear Technology’s PScope data
processing software, which is available for no charge on
our website at http://www.linear.com.
Design files for this circuit board are available. Call
the LTC factory.
L
, LTC, LTM, LT, Burst Mode, OPTI-LOOP, Over-The-Top and PolyPhase are registered
trademarks of Linear Technology Corporation. Adaptive Power, C-Load, DirectSense, Easy
Drive, FilterCAD, Hot Swap, LinearView, µModule, Micropower SwitcherCAD, Multimode
Dimming, No Latency ∆Σ, No Latency Delta-Sigma, No R
SENSE
, Operational Filter, PanelProtect,
PowerPath, PowerSOT, SmartStart, SoftSpan, Stage Shedding, SwitcherCAD, ThinSOT,
UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product names
may be trademarks of the companies that manufacture the products.
QUICK START PROCEDURE
Validating the performance of the LTM9004 is simple
with DC1513, and requires only two input sources, a
clock source, a computer, and a lab power supply. Refer
to Figure 1 for proper board evaluation equipment setup
and follow the procedure below:
1.
Connect the power supply as shown in Figure 1.
There are on-board low-noise voltage regulators
that provide the two supply voltages for the
DC1513. The entire board and all components
share a common ground. The power supply should
still be a low-noise lab power supply capable of
supplying at least 0.5 Amp @ 5.0VDC, and 1 Amp
@ 3.0VDC.
2.
Provide an encode clock to the ADC via SMA con-
nector J7. Use a low-phase-noise clock source
such as a filtered RF signal generator or a high-
quality clock oscillator.
NOTE.
Similar to having a noisy input, a high-jitter (phase noise) encode
clock will degrade the signal-to-noise ratio (SNR) of the system.
Table 1: DC1513 Connectors and Jumpers
REFERENCE FUNCTION
J3 (SHDN) Enables/disables the ADC. Default is ON.
J4 (MODE) Output Format and Clock Duty Stabilizer pin.
Default is VDD.
J5 (SHDN_AMP) Enables/disables the Amplifers. Default is ON.
J6 (LO) Board LO Signal Input. Impedance-matched to
50
Ω
for use with lab signal generators.
J7 (CLK) Board Clock Input. Impedance-matched to
50
Ω.
Drive with a low-phase-noise clock oscil-
lator or filtered sine wave signal source.
J8 (MIXER
ENABLE)
Enables/disables the RF mixer. Default is ON.
J11 (RF) Board RF Signal Input. Impedance-matched to
50
Ω
for use with lab signal generators.
TP1 (SENSE_I) Reference input to adjust the full-scale range of
the DC1513, I Channel. Default is VDD.
TP2 (GND) DC ground.
TP4 (GND) DC ground.
TP5 (+3V) DC Supply input (3VDC).
TP7 (+5V) DC Supply input (5VDC).
TP8 (GND) DC ground.
TP12 (SENSE_Q) Reference input to adjust the full-scale range of
the DC1513, Q Channel. Default is VDD.
3.
Apply an RF input signal to the board. For best
results, use a low distortion, low noise signal
LTM9004 14 Bit D
Conversion Receiver Subsys