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L9333
March 2001
■WIDE OP ERATING SUPPLY VOLTAG E
RANGE FROM 4.5V UP TO 32V FOR
TRANSIENT 45V
■VERY LOW STANDBY QUIESCENT
CURRENT TYPICALLY < 2µA
■INPU T T O O U TPUT SIG N AL TRAN S FER
FUNC TION PROGR A M M AB LE
■HIGH SIGNAL RANGE FROM -14V UP TO 45V
FOR ALL INPUTS
■3.3V CMOS COMPATIBLE INPUTS
■DEFINED OUTPUT OFF STATE FOR OPEN
INPUTS
■FOUR OPEN DRAIN DMOS OUTPUTS, WITH
RDSon = 1.5Ω FOR VS > 6V AT 25°C
■OUTPUT CURRENT LIMITATION
■
CONTROLLED OUTPUT SLOPE FOR LOW EMI
■OVERTEMPERATUR E PR O TECTION FOR
EACH CHANNEL
■
INTEGRATED OUTPUT CLAMPING FOR FAST
INDUCTIVE RECIRCULATIO N V
FB
> 45V
■STATUS MONITORING FOR
- OVER TEM PER AT U RE
- DISCONNECTED GROUND OR SUPPLY
VOLTAGE
DESCRIPTION
The L9333 is a monolithic integrated quad low side
driver. It is intended to drive lines, lamps or relais in
automotive or industrial applications.
SO20 (12+4+4) DIE
ORDER ING NUMB ERS :
L9333MD (SO20 12+4+4)
L9333DIE1 (DIE)
QUAD LOW SIDE DRIVER
BLOCK DIAGRAM
THERMAL
SHUT-
DOWN
DIAG-
NOSTIC
LOGIC
CHANNEL1
CHANNEL4
REFERENCE Vlogic
Vint
IN 4
EN
VS
GND
OUT 4
OUT 1
DIAG
4
PRG
=&
REN
IN 1 RIN
VS
PRG
RIN
MULTIPOWER BCD T ECH NOLOGY
L9333
2/13
PIN CONNECTION
(Top view)
PIN FUNCTION
Pin
N° Pin Name Description
1 IN 1 Input 1
2 IN 2 Input 2
3 DIAG Diagnostic
4, 5, 6, 7,
14, 15,
16, 17
GND Ground
8 VS Supply Voltage
9 IN 3 Input 3
10 IN 4 Input 4
11 EN Enable
12 OUT4 OUTPUT4
13 OUT 3 OUTPUT 3
18 OUT 2 OUTPUT 2
19 OUT 1 OUTPUT 1
20 PRG Programming
1
2
3
4
5
6
7
813
14
15
16
17
18
19
20
9
10 11
12
IN1
IN2
DIAG
GND
GND
GND
GND
VS
IN3
IN4
PRG
OUT1
OUT2
GND
GND
GND
GND
OUT3
OUT4
EN
So 12+4+4
Med. Power
3/13
L9333
ABSOLUTE MAXIMUM RATINGS
No te 1) : I n flyback phase th e output v ol t age can reach 60V .
ESD - PROTECTION
Note: Human-Body-Model according to MIL 883C. The device widthstand ST1 class level.
THERMAL DATA
Note 2) : With 6cm2 on board heat sink area.
LIFE TIME
Symbol Parameter Value Unit
VSSupply voltage DC
Supply voltage Pulse (T = 400ms) -0.3 to 32
-0.3 to 45 V
V
dVS/dt Supply voltage transient -10 to +10 V/µs
VIN, VEN,
VPRG Input, Enable, Programming
Pin voltage -14 to 45 V
VOUT Output voltage -0.3 to 45 1) V
VDIAG Diagnostic outpu t volta ge -0.3 to 45 V
Parameter Value
against GND Unit
Supply pins and signal pins ± 2 KV
Output pins ± 4 KV
Symbol Parameter Min Typ Max Unit
TJSD Temperature shutdown threshold 175 220 °C
TJSDhys Temperature shutdown hysteresis 20 K
SO 12+4+4
Rth (j-p) Thermal resistance junction to pins 15 °C/W
Rth (j-a) Thermal resistance junction to ambient 2) 50 °C/W
Symbol Parameter Condition Value Unit
tBuseful life time VS ≤ 14V
EN = low 20 years
tboperating life time 4.5V ≤ VS ≤ 32V
EN = high 5000 hours
L9333
4/13
OPERATING RANGE:
Within the operating range the IC operates as des cribed i n the circuit descr iption, includ ing the diagnos tic table.
ELECTRICAL CHARACTERISTCS
The electrical characteristics are valid within the defined Operating Conditions, unless otherwise specified.
The function is guaranteed by design until T
JSDon
switch-on-threshold.
Symbol Parameter Condition Min Max Unit
VSSupply voltage 4.5 32 V
VIN, VEN,
VPRG Input voltage -14 45 V
VOUT Output voltage Voltage will be limited by internal Z-
Diode clamping -0.3 60 V
VDIAG Diagnostic output voltage -0.3 45 V
TJJunction temperature -40 150 °C
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY
IQQuiescent current VS ≤ 14V; VEN ≤ 0.3V
Tamb 85 °C < 2 10 µA
VS ≤ 14V; VEN ≤ 0.3V
Ta 150°C 50 µA
VS ≤ 14V; EN = high, Output = off
EN = high, Output = on 12
3.5 mA
mA
Inputs, IN1 - IN4; Programming, PRG
VINlow Input voltage LOW -14 1 V
VINhigh I nput voltage HIGH 2 45 V
IIN Input curren t 0V ≤ VIN ≤ 45V 3) -25 50 µA
RIN I nput imped ance V IN < 0V; VIN > VS10 60 kΩ
Note 3) : Cu rrent direct i on d epends on the program m ing s etting (P RG=hi gh l eads i nto a posit i ve current see also Block di agram pa ge 1)
Enable EN
VENlow I nput voltage LOW -14 1 V
VENhigh I nput voltage HIGH 2 45 V
REN Input impedance -14V < VEN < 1.5V 5 kΩ
IEN Input current 1.5V < VEN < 45V 5 80 µA
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L9333
No te : All pa ram eters are meas ured at 125°C.
N ote 4) : See al so Fig.3 Ti m i ng Cha racter i stics
Outputs OUT1- OUT4
RDSon Output ON-resistor VS > 6V, IO = 0.3A 1.7 3.8 Ω
IOLeak Leakage current VO = VS = 14V; Ta < 125°C 1 5 µA
VO = VS = 14V; Ta < 150°C 25 µA
VOClamp Output voltage during clamping EFB ≤ 2mJ; 10 mA < IO < 0.3A 45 52 60 V
IOSC Short-circuit current VS > 6V 400 700 1000 mA
COinternal output capacities VO > 4.5V 100 pF
Diagnostic Output DIAG
VDlow Output voltage LOW IDL = 0.6mA 0.8 V
IDmax Max. output current internal current limitation; VD =
14V 1515mA
I
DLeak Leakage current VD = VS = 14 V; Ta < 125 °C 0.1 1 µA
VD = VS = 14 V; Ta < 150 °C 5 µA
Timing Characteristics 4)
td,on On delay time VS = 14V
Cext = 0F; Lext = 0H
only testing condition
10mA ≤ I0 ≤ 200mA
23.5µs
t
d,off Off delay time 3 4.5 µs
tset Enable settling time 20 µs
td,DIAG ON or OFF Diagnostic delay time 10 µs
Sout Output voltage slopes 2.5 9 16 V/µs
Symbol Parameter Test Condition Min. Typ. Max. Unit
ELECTRICAL CHARACTERISTCS
(continued)
L9333
6/13
Figu re 1. Ti m in g Characte ri st ic s
Note 5) : Output voltage slope not controlled for enable low!
t
VS
VOUT
VIN
t
VEN
Non-Invertin
g
Mode Inve rtin
g
Mode
tset td,off td,on
Active
t
t
5)
VPRG
S
0.8 V
S
0.2 V
tset
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L9333
FU NCTIONAL DESCRIPTION
The L9333 is a quad low side driver for l ines, lamps or i nductive loads in automoti ve and i ndustrial applicati ons.
The logic input levels are 3.3V CMOS compatible. This allows the device to be dr iven directly by a microcon-
troller. For the noise immunity, all input thresholds have a hysteresis of typ. 100mV. Each input (IN, EN and
PRG) is protected to withstand vol tages from -14V to 45V. The devi ce is activ ated with a 'high' signal on E Nable.
ENable 'low' switches the device into the sleep mode. In this mode the quiescent current is typically less than
2µA. A high si gnal on PRoGramming input c hanges the signal transfer pol arity from noninv erting to the inver ting
mode. This pin can be connected either to V
S
or GND. If these pins are not connected, the forced status of the
PRG and EN pin is low. For packaged applications it is still recommended to connect all input pins to ground
respective VS to avoid EMC influence. The forced condition leads to a mode change if the PRG pin was high
before the inte rruption. Independent of the PRoGramming input, the OU Tput switches off, i f the s ignal INput pin
is not connected. This function is verified using a leakage current of 5µA (sink for PRG=high; source for
PRG=low) during circuit test.
Each output driver has a current limitation of min 0.4A and an independent thermal shut-down. The thermal
shut- down deactivates that output, which exceeds temperature s witc h off lev el. When the juncti on temperatur e
decreases 20K below this temper ature threshold the output will be activated again. This 20K is the hysteresis
of the thermal shutdown function. The Gates, of the output DMOS transistors are charged and discharged with
a current source. Ther efore the output slope is limited. This reduces the electromagnetic radiation. For induc-
tive loads an output voltage clamp of typically 52V is implemented.
The DIAGnostic is an open drain output. The logic status depends on the PRoGramming pin. If the PRG pin is
'low' the DIAG output becomes low, if the device works correctly. At thermal shut-down of one channel or if the
ground is disconnected the DIAGnostic output becomes high. If the PRG pin is 'high' this output is switched off
at normal function and s witched on at overtemper ature. For the fault conditi on of inter rupted ground, the poten-
tial of VS and Diagnostic should be equal.
DIAGNO STIC TABLE
X = not relevant
* selective for each channel at overtemperature
Pins EN PRG IN OUT DIAG
Normal function H L L L (on) L (on)
H L H H (off) L (on)
H H L H (off) H (off)
H H H L (on) H (off)
L X X H (off) H (off)
Overtemperature,
disconnected ground or
supply voltage
HLX
H (off) *H (off)
Overtemperature H H X H(off) *L(on)
L9333
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Figure 2. Application for Inverting Transfer Pol arity
Figure 3. Application for non Inverting Transfer Polarity
No te W e recommend to use the dev ice for driving induc tive l oads with fly back ener gy EFB ≤ 2mJ.
IN
OUT 1
OUT 2
OUT 3
OUT 4
IN 1
IN 2
IN 3
IN 4
GND
VS
PRG
EN DIAG
AdressdecoderA 0:8
D 0
D 1
D 2
D 3
8
VCC = 5V or 3.3V
VCC
GND
MICROCONTROLLER
INT
BOARD VOLTAGE 14 V
2 W 12 mH 250 mA
50 kHz
VCC
GND
VCC = 5V
33µF
240Ω
50pF
10µH
L9333
M
IN
BOARD VOLTAGE 14 V
2 W 12 mH 250 m A
10µH
VCC
GND
VCC = 5V
OUT 1
OUT 2
OUT 3
OUT 4
IN 1
IN 2
IN 3
IN 4
GND
VS
PRG
EN
DIAG
L9333
240Ω
50pF
M
33µF
9/13
L9333
EMC SPECIFICA TION
EMS (electromagnetic susceptibility)
Measurement setup:
DUT mounted on a specific application board is driven in a typical application circuit (see below). Two devices
are stimulated by a generator to read and write bus signals. They will be monitored externally to ensure proper
function.
Measurement method:
a) The two bus lines are transferred 2m under a terminated stripline. That's where they were exposed to the
RF-field. Stripline setup and measurement method is described in D IN 40839-4 or ISO 11452-5.
b) DUT mounted on the same application board is exposed to RF through the tophole of a TEM-cell. Mea-
surement method according SAE J1752.
c) The two bus lines are transferred into a BCI current injection probe. Setup and measurement method is
described in ISO 11452-4.
Failur e criteria:
Failure monitoring is done by envelope measurement of the logic signals with a LeCroy oscilloscope with ac-
ceptance levels of 20% in amplitude and 2% time.
Limits:
The device is measured within the described setup and limits without fail function.
The Electromagnetic Susceptivity is not tested in production.
a) Field strength under stripline of > 250V/m in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
b) Field strength in TEM-cell of > 500V/m in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.
c) RF-currents with BCI of > 100mA in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.
Measured Circuit
The EMS of the device was verified in the below described setup.
L9333
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Figure 4.
2m
Stripline
f
2
16
7
8
13
9
1
11
125Hz
250Hz
500Hz
17
4
5
1kHz
f
2
f
2
+
-
14
U(t)
14V
Flat cable
ANECHOIC CHAMBER
Jumper
SMBYW01-200
SM6T39A
33µF
10nF
10kΩ
4.7nF 4.7nF
10kΩ20kΩ
4 ∗ 4.7n 4.7nF 4 ∗ 1nF
optional
VS EN PRG
DIAG
OUT1
OUT2
OUT3
OUT4
IN1
IN2
IN3
IN4
GND
L9333
4 ∗ 10k Ω
4 ∗ 100 Ω
optional
1
16
17
4
5
9
11
19
14
13
8
7
Jumper
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L9333
110
1120
A
e
B
D
E
L
KH
A1 C
SO20MEC
h x 45˚
SO20 (12+4+4)
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.1 0.3 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.6 13 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
K 0˚ (min.)8˚ (max.)
OUTLINE AND
MECHANICAL DATA
PAD
L9333
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L9333
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
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L9333
