TDA1060 TDA1060A TDA1060B purple binder, tab 4 CONTROL CIRCUIT FOR SWITCHED-MODE POWER SUPPLY GENERAL DESCRIPTION The TDA1060 is a bipolar integrated circuit intended for the control of a switched-mode power supply. It incorporates a/l the control functions likely to be required in switched-mode power supplies for professional equipment. The circuit features: Suitability for a wide range of supply voltages Built-in stabilized power supply for external circuitry Built-in temperature-compensated voltage reference Adjustable frequency Adjustable control loop sensitivity Adjustable pulse width Adjustable maximum duty factor Adjustable overcurrent protection limit Low supply voltage protection with hysteresis Loop fault protection Slow-start facility Feed-forward facility Core saturation protection facility Overvoltage protection facility Remote ON/OFF switching facility QUICK REFERENCE DATA Supply voltage {voltage source) Vec Supply current (current source) lec Output current 114; 15 Stabilized voltage Vz Reference voltage Vref Output pulse repetition frequency range fo Operating ambient temperature range TDA1060 Tamb TDA1060A Tamb TDA1060B Tamb max. - 18 max. 30 max. 40 typ. 8,4 typ. 3,72 50 Hz to 100 25 to +125 Oto+70 55 to +150 Vv mA mA kHz C C oC PACKAGE OUTLINES TDA1060, TDATO60A: 16-lead DIL; plastic (SOT-38). TDAI060B: 16-lead DIL; ceramic (SOT-74). c Mullard ) August 1982TDA1060 TDA1060A TDA1060B ~~ ~ FW RX CX SYN SAT 16|7 {8 [9 3 TDA1060 O6V REFERENCE SAWTOOTH VOLTAGE GENERATOR | +7 [ LE ac 3 E> PULSE WIDTH FB MODULATOR 4 | LIN Lis a GA - 14 tL" OF mop / AD r O6Vv - + $s 6 R DEM ri, & O6V > 1k2 roo lower t r sawtooth o4ev level STABILIZED 2 " ee cE 2 cM rn > SUPPLY V2 06V P ry ]10 1 12 EN Vec VEE 7274489.1 Fig. 1 Block diagram. Vec CY v2 [2 FB 4 ca [4 | MOD [e] oem [6 | RX 7 cx [a | TDA1060 TDA1060A TDA1060B Fig. 2 Pinning diagram. positive supply connection stabilized voltage output feedback input gain adjustment output modulation input maximum duty factor input exterrial resistor connection external capacitor connection synchronization input ENABLE input overcurrent protection input common core saturation and overvoltage protection emitter output collector output PINNING 1 Vee 16) FW 2 V2 hs] 3 FB 15] oc 4 GA 14] QE 5 MOD 13| SAT 6 DFM 72] Ver 7 RX 8 CX 11] cm fH 9 SYN fio] ew 10 EN y2 | syn 41. CM 12 VEE FZBOTT4 13 SAT input 14 OE 15 Qe 16 FW feed-forward input 2 August 1982 ( Mullard 7TDA1060 Control circuit for SMPS TDAIO60A TDA1060B FUNCTIONAL DESCRIPTION The TDA1060 contains the control loop for a fixed-frequency pulse-duration regulated SMPS. The device works as follows. The output voltage VQ of the SMPS is sensed via a feedback network and compared with an internal reference voltage Vye. Any difference between Vo ard V rez is amplified and fed to a pulse-width modulator (PWM), where it is compared with the instantaneous level of a ramp waveform (sawtooth} from an oscillator. The output from the PWM is a rectangular waveform synchronized with the oscillator waveform; its duty factor depends on the difference between VQ and Vref. This signal drives the base of the SMPS power switching transistor so that its conduction period and hence the amount of energy transferred from the input to the output of the SMPS is controlled, resulting in a constant output voltage, Stabilized power supply: Voc and Vz (pins 1 and 2) The circuit contains a voltage/cuirrent regulator and may be supplied either by a current source (e.g. a series resistor connected to the high voltage input of the SMPS), or a voltage source (e.g. a 12 V battery). The stabilized voltage, typically 8,4 V, is also available at Vz, pin 2 for supplying external circuitry, e.g. a potentiometer to adjust the maximum duty factor. This supply output is protected against short- circuits. The current drawn frorn this output increases the total 1C supp'y current by the same amount. When the supply voltage Voc becomes tao low, i.e. Vac < Vz + 0,2 V, the circuit is automatically switched off. As soon as the supply voltage exceeds this threshold value by more than 0,2 V the circuit starts the SMPS via the slow start procedure. Operating frequency: RX and CX (pins 7 and 8) The frequency of the sawtooth generator, and hence of the output pulses, is set by an externa! resistor R7 at RX, pin 7, and an external capacitor C8 at CX, pin 8. The frequency will be 1,2/R7C8. It may be set between 50 Hz and 100 kHz and is virtually independent of the supply voltage. Maximum duty factor and slow start: DFM (pin 6) The maximum duty factor is set by the valtage on the duty factor input DFM (see Fig. 4). This voltage usually is derived from the stabilized power supply Vz, pin 2, by an external voltage divider, see Fig. 6. As the upper and lower levels of the sawtooth waveform are set by an internal voltage divider, the accuracy of the maximum duty factor setting is determined by resistor ratios rather than by absolute values. In case of a short-circuited feedback loop (V3.4 less than typ. 600 mV) the duty factor input is internally biased to the lower level of the sawtooth waveform via a resistor of typ. 1 KQ. The maximum duty factor permitted in that case sets a maximum limit to the impedance level of the external voltage divider at pin 6. During the flyback of the sawtooth the output pulse is inhibited. For a 1 nF capacitor C8 at pin 8 this flyback time is 1 us. This sets a natural limit to the duty factor. The time constant for the slow start is determined by an external capacitor connected between the maximum duty factor input DFM and Veg, pin 12, together with the impedance of the voltage divider at pin 6. This capacitor also deterrnines the dead time before the slow start procedure for remote ON/OFF or when the current sensing voltage has exceeded 600 rnV, see below. [f the DFM input is not used it should be connected to V7 via a resistor of 5 k&2. Uv Mullard ) August 1982TDA1060 TDA1060A TDA1060B _/ FUNCTIONAL DESCRIPTION (continued) Control loop sensitivity, stability, and feedback loop fault protection, FB and GA (pins 3 and 4} The device contains a control loop error amplifier, i.e. a differential amplifier that compares the voltage on the feedback input FB, pin 3, with the internal reference voltage. This reference voltage is a temperature-compensated voltage source based on the band-gap energy of silicon. The control loop sensizivity is determined by the closed-loop gain Af of the error amplifier. Normally the output from the SMPS is connected to the feedback input FB via a voltage divider and a series resistor. The closed-loop gain of the error amplifier is set by applying feedback from the gain adjustment output GA, pin 4, to the feedback input FB by a resistor R3-4, see Fig. 6. To avoid instability a capacitor should be connected between the gain output GA and Vee, pin 12. A 22 nF capacitor will cause the frequency response to fall off above 600 Hz. The feedback input FB is internally biased to the HIGH level, this gives a protection against a feedback loop fault: an open feedback loop will make the duty factor zero. A shorted feedback loop (feedback voltage less than typ. 600 mV) causes the maximum duty factor input DFM to be internally biased to the lower level of the sawtooth waveform via a resistor of typ. 1 kQ2, thus substantially reducing the maximum duty factor. This duty factor will then be determined by the impedance of the external voltage divider at DFM, pin 6, and the internal biasing resistor. Overcurrent protection input CM (pin 11) There are two current limits, corresponding with voltages on the overcurrent protection input CM of typ. 480 mV and 600 mV. As soon as the voltage on this input exceeds 480 mV, the running output pulse is immediately terminated; the next pulse starts normally at the next period. If the voltage exceeds 600 mV, the output pulses are inhibited for a certain dead time, during which the slow start capacitor at pin 6 is unloaded. After this the circuit starts again with the slow start procedure. \f the overcurrent protection input CM is not used, it should be connected to Ver, pin 12. Feed-forward input FW (pin 16) The feed-forward input FW can be connected to an external voltage divider from the input voltage of the SMPS, see Fig. 6. It has the effect of varying the supply voltage of the sawtooth generator with respect to the stabilized voltage. When the voltage on the feed-forward input increases, the upper level of the sawtooth is also increased. Since neither the voltage level that sets the maximum duty factor nor the feedback voltage are influenced by the feed-forward, the duty factor reduces (see Fig. 5). This can therefore compensate for mains voltage variations. If feed-forward is not required the feed-forward input FW should be connected to Veg, pin 12. Synchronization input SYN (pin 9) The frequency of the sawtooth waveform, and hence of the output pulses, can be synchronized via the TTL compatible synchronization input SYN. The synchronizing frequency must be lower than the oscillator free-running frequency. When the synchronization input is LOW the sawtooth generator is stopped; it starts again when the input goes HIGH. Synchronization pulses do not influence the slope of the sawtooth, and hence not the width of the output pulses, they only change their separation in time. For free-running operation it is advisable to connect the synchronization input SYN to Vz, pin 2. August 1982 ( Mullard TDA1060 Control circuit for SMPS TDA1060A TDA1060B Core saturation and overvoltage protection input SAT (pin 13) To obtain a protection against core saturation, especially during transient conditions, the output transformer of the SMPS has to be fitted with a winding serving as a current sensor. Its output voltage is rectified and fed to the SAT input. This core saturation protection may be combined with an overvoltage protection. To this end a portion of the SMPS output voltage is alsa fed to the SAT input either via a voltage divider or via a suitable regulator diode {zener diode). The output pulses are inhibited as Song as the voltage on this input exceeds the threshold voltage, typ. 600 mV. The voltage at the SAT input does not influence the frequency of the sawtooth cenerator and hence not of the output pulses. If none of these protection facilities are used, the SAT input should be corinected to Veg, pin 12. Remote ON/OFF switching: ENABLE input EN (pin 10) The output pulses can be switched on and off by applying logic levels to the TTL. compatible ENABLE input. A LOW level causes immediate inhibition of the output pulses, a subsequent HIGH level switches the circuit on with the slow-start procedure. If this facility is not required, E:N should be connected to V7, pin 2. Modulation input MOD (pin 5) The duty factor of the output pulses may be reduced below the value resulting from the voltages on the maximum duty factor input DFM and the gain adjust output GA by applying a lower voltage to the modulation input MOD. This input may be used with an external control loop, e.g. for constant- current control, or to obtain a fold-back characteristic. If the modulation input is not used, it should be connected to Vz, pin 2. Outputs QC and QE (pins 13 and 14) To avoid double pulses that might occur at an excessively low mains voltage or an excessively high output current the output is preceded by a latch. The two outputs offer a choice of output current polarity, QC giving a positive current, i.e. a current flowing into the output, and OE giving a negative current, a current flowing out of the output. The two connections have the additional advantage that the relatively large output currents do not flow through the Vcc and Veg connections, where they could induce noise. 0 Mullard ) ~ nus 1982TDA1060 TDA1060A TDA1060B RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Supply voltage range (voltege source) Vec 0,5 to +18 V Supply current (current source} lec max. 30 mA Feed-forward input voltage range Vec <24V V16-12 OtoVec V Vec> 24V V16-12 Oto 24VvV Input voltage range (all other inputs) V| Oto Vz Vv Emitter output voltage range V14-12 Oto 5V Collector output voltage range 45-12 OtoVcc V Output current d.c. (see Figs 3a, c arid e) 44; 115 max. 40 mA peak; t = max. 1 ws; duty factor d << 10% --144:145 max. 200 mA Storage temperature range TDA1060 Tstg 40 to +125 C TDA1060A Tstg 40 to +125 9C TDA1060B T stg 40 to +125 C Operating ambient temperature range TDA1060 Tamb 25 to +125 C TDA1060A Tamb Oto +70 C TDA1060B Tamb 65 to +150 C Power dissipation (see Figs 3b, d and f) Prot max. 1W 6 August 1982 ( Mullard &Control circuit for SMPS TDA1060 TDA1060A TDA1060B 40 7289777 lo Prot (mA) (w) 30 1 NN 20 | TDAIO60 7 TDAIO60 105 0 T so tT T 0 T ae t+ ?T ~50 c 50 100 150 -50 0 50 100 150 Tamb (C) Tamb (C) 404 7289776 fo | Prot {mA) (Ww) 30 1 204 TDA TOA q 1060A 7 1060A 107 70 65}|70 0 T T y T T T 0 T T T T T TT T -50 Q 50 100 150 -50 Q 50 100 150 Tamb (C) Tamb (C) 40-4 7289779 lo Prot (mA) (Ww) 30 1 ~~ 4 NN 20-4 167 7 TDA1060B 1 TDA1060B 104 55 ~55 07~T ToT Tot 0 on a Ta? -50 0 50 100 150 -50 0 50 100 150 Tamt (C) Tamb (C) Fig. 3 Output current and power dissipation derating curves. c Mullard a August 1982TDA1060 TDAIO60A TDA1060B CHARACTERISTICS Vec = 12 V; Tamb = Operating ambient temperature range, uriless otherwise specified. symbol min. typ. max. unit Operating ambient temperature range TDA1060 Tamb 25 - 125 oC TDA1TO060A Tamb 0 _ 70 C TDA1060B Tamb 55 _ 150 o Supply Vc (pin 1) Supply voltage aticg = 15 mA TDA1060 Vec 18,5 23 27 Vv TOAIQ60A Vec 18,5 23 27 Vv TDA1060B Vec 18 23 27,5 Vv atlcc =30mA TDA1060 Vec 19,5 24 29 Vv TDA1060A Vec 19,5 24 29 Vv TDA1060B Vec 19 24 29,5 Vv Supply current; R7 = 25 ki; duty factor d = 50%; I; = 0; at Tamb = 25 C lec 2,5 10 mA over ambient temperature range lec 2,5 _ 15 mA Threshold voltage of low supply voltage protection at Tamb = 25 C Vcc 8,85 10,8 Vv Variation with temperature AVec/AT; 7,5 - mV/K Hysteresis of low supply voltage protection AVcc - 500 _ mV Stabilized supply output Vz (pin 2) Output voltage Vz 7,5 8,4 9 Vv Variation with temperature AV2/AT -1,5 - +1,5 mV/K Output current IZ _ _ 5 mA Feedback input FB (pin 3) Input voltage, feedback operation V3-12 2 - Vz-1 Vv input current at V3.49=2V \3 15 12 35 HA Internal reference voltage, measured at pin 3; pins 3 and 4 interconnected and grounded via a 100 nF capacitor Vref 3,42 3,72 4,03; V AVret/V Variation with temperature se - 0,01 - %/K ae : AV ref Variation with supply voltage _ 08 - mvV/V AVcc August 1982 ( Mullard YTDA1060 Control circuit for SMPS TDAIOQ60A TDA1060B symbol min. typ. max. unit Long-term variation with time tAVeeg/At} 2 - uV/h Threshold voltage of feedback loop short-circuit protection V3-12 460 600 720 mV AV3.49/V3- Variation with temperature 3 2 312) 0,01 _ %/1K Gain adjustment output GA {pin 4) Open-loop gain, pin 3 toe pin 4 Ao _ 60 _ dB External feedback resistor R3.4 10 _ kQ Modulator input MOD (pin 5) Input current at V5.49 = 2V; V46-12 > 2V |5 _- - 5 BA Maximum duty factor input DFM (pin 6) Input voltage for limiting the duty factor to 50%; fg = 10 to 100 kHz; Vig.49=O0V V6-12 _ 04VZ7 Vv Input current at Vg.42=2V l6 - - 6 BA Capacitor discharge current during fault condition Ig 2,5 _ _ mA Minimum output OFF time at C7 = 1,8 nF toff _ 1 us Variation of max. duty factor with ternpera- ture at fg = 20 kHz and dingy = 50% Admax/AT| -- 002 IK Internal biasing resistor to Veg at V3.12=0V R6-12 0,75 1 1,25 kQ Synchronization input SYN (pin 9) Input voltage, sawtooth ON ViH 2 - Vz Vv sawtooth OFF: TDA1060; TDA1Q60A VIL 0 - 08 Vv TDA1060B Vin 0 - 06 Vv Input current at Vg.79= OV le 20 _ 120 LA ~F External resistor connection RX. (pin 7) External frequency adjustment resistor R7 5 40 kQ External capacitor connection CX (pin 8) Sawtooth, upper level at V1g.42 = OV Vg.12 _ 5,7 - Vv lower level Vg.12 ~ 1,3 - Vv Output pulse repetition frequency fo 0,05 - 100 kHz Afo/fo Variation with temperature _ 0,01 - %/K 7 Mullard August 1982TDA1060 TDA1060A TDA1060B CHARACTERISTICS (continued) symbol min. typ. max. unit Feed-forward input FW (pin 16) Input voltage for Veco < 24V V16-12 0 ~ Vec Vv for Vcc > 24V V16-12 0 - 24 v Input current at V7@.12 = 16 V; Vec = 18 V; Tamb = 25 9G l16 = _ 60 BA Frequency verianon with input voltage Afo/to solv at V16-12 AVi642 _ o Overcurrent protection input CM (pin 11) Input voltage V11-12 0 - Vz Vv Input threshold voltage for single pulse inhibit (current limit moce) VT 370 48) 575 mV Ratio of threshold voltages tor shut down/ slow start and for single pulse inhibit VT2/VT1 1,25 - Threshold variation with temperature AV/AT _ 60 ~ BV/K Input current at V41.72 = 250 mV '14 _ - 10 HA Turn-off delay, 145 = 30 nA; V4q1-12=12xV7q td _ _ 0,8 BS Core saturation and overvoltage protection input SAT (pin 13) Input voltage V 43-12 0 - V2 Vv Input threshold voltage V13-12 460 600 720 mV Threshold variation with temperature AV/AT _ 60 - uVv/K Input current at V13.42 = 250 mV I43 - ~ 7 HA ENABLE input EN (pin 10) Input voltage ON VIN 2 - V2 Vv OFF: TDA1060; TDA1060A VIL 0 - 0,8 Vv TDA1060B VIL 0 - 0,6 Vv Input current at V19.42 = OV Hy 20 - 120 uA Outputs QC and OE (pins 14 and 15) Output current lyailqg| - - 30 mA Emitter output voltage V14-12 - - 5 Vv Collector output voltage at V14.42 = OV: 145 = 30mA V 15-14 ~ _ 400 mV 10 August 1982 ( Mullard oControl circuit for SMPS TDA1060 TDAIO60A TDA1060B 7289775 dnax 0,8 06 o1 62 O38 O04 OF O06 O07 Re-12 Re -12 + Re-2 Fig. 4 Maximum duty factor dyygx as a function of the voltage divider ratio at the duty factor input DFM. 7289776 d/do 0,8 0,6 0,4 0,2 0 06 1 14 18 22 26 3 Vig-12/ Vz Fig. & Feed-forward regulation characteristic. Duty factor d as a function of the voltage V4g_1 on the feed-forward input FW. do is the duty factor for V16-12'S Vz. Mullard ) (es 1982 1| S TDA1060 TDAtO60A TDA1060B afiexjoa 4ndino SdlWS Aiddns jamod apou-paysums & Ui O9OLVWGL 84} 03 SuCIIIaUUOD 9g BIy4 C8L68ZL de ZL-9y TT a oT] L deo Sf] | aes | on - aBel|oa +4 eo) Lo indjno T io id bey SdWS } Ct al ol cf al a 33, 49 3H VO Jane 4019918 A 84 8 abr] )OAa00 A josuas, 4 Md aL Wand uoljesnzes 3109 ivs l 150 W2 vi ogolval bh ah 90 Na Of J40/U0 a10Wa2 SdWS Wid = 9 [ cowie] fy a g z-3y joes Fr zy wasted UL A 6 a i | Ld _ Ajddns -o'p SA Ayddns -o:p azejnBauun pare AlddNS WAMOd sujeus oe dalvino3yNn NOILVWYOINI NOILVOIIdd u August | ( MullardTDA1060 Control circuit for SMPS TDAIOGOA TDA1060B 7Z89784 ai do co {f 42 6 {3 4 = =H T a * 3 i }f -~ 426 2 KH }+- Fig. 7 Application of the TDA1060 in a 24 V, 12 W SMPS with flyback converter. y Mullard ) ( sm 1982 13TDA1060 TDA1060A TDA1060B _/ BYV96D BYW3C-150 220V ac. START-UP BYW30 SUPPLY 150 + BYV95B BYV95B BYV96D BD230 4+20V 7Z89785 Fig. 8 Application of the TDA1060 in a 24 V, 240 W SMPS with forward converter. 24V/108 August oe | ( Mullard C7TDA1060 TDA1060A TDA1060B Control circuit for SMPS \ / GP 220V | [ . ) < START-UP b : . i! . |. ev) arc 3, i @ 8] x opt! | L | Bq) = | 0] , j}-4 oe ; LY NS x 84 t ToT] Ly BC637 16 15 14 13 12 #11 #10 9 J TDA1060 +] 1.2 3 4 5 6 7 8 TAL | = 1 @ we aot | [ T cnve2 fo +L = Z +H. pl | reeores Fig. 9 Application of the TDA1060 in a 5 V, 30 W SMPS with forward converter and with an optocoupler CNY62 for valtage separation. APPLICATION INFORMATION SUPPLIED UPON REQUEST. U Mullard | ( August 1982 15TDA1060 TDA1060A TDA1060B 16-LEAD DUAL IN-LINE; PLASTIC (SOT-38) 22 max + 8,25max _e seating plane 76 7255041.7 16 15 OQ Positional accuracy. 4+- @ Maximum Material Condition. 1 2 3 4 5 6 7 8 (1) Centre-lines of all leads are TAO TL, within 0,127 mm of the nominal JU, Ly position shown; in the worst case, : the spacing between any two leads may deviate from nominal by +0,254 rom. top view (2) Lead spacing tolerances apply from seating plane to the line indicated. Dimensions in mm SOLDERING 1. By hand Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C it must not be in contact for more than 10 seconds; if between 300 C and 400 C, for not more than 5 seconds. 2. By dip or wave The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for mare than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the perrnis- sible limit. 3. Repairing soldered joints The same precautions and limits apply as in (1) above. 1 August ve | ( Mullard vyTDA1060 Control circuit for SMPS TDAIO60A TDA1060B NL 16-LEAD DUAL IN-LINE; CERAMIC (SOT-74) +} _---_-~ 19,94 tax ----_ -# 8,25 max -: 2 \ | S t T 2 | 2 <== 5,08 1 L. 3 max I & 0,38 | ; | Y - , A a min 4 | } _ -to7 | 3,4 i 2,9 14x 0,38 io) | l= feTozse | | | j E84] | | __ _/J 4,27 10,0 ___ max 7,6 yreseens "| 1,5 [ PM Ae) 6 #1 14 61306612)~COMN 10 9 top view ? @ Positional accuracy. 3 8 @ Maximum Material Condition. LL! LJ LY Le L LJ Ll LU (1) Centre-lines of all leads are within 0,127 mm of the nominal position shown; in the worst case, the spacing between any two leads may deviate from nominal by +0,254 mm. (2) Lead spacing tolerances apply from seating plane to the line indicated. Dimensions in mm Remarks 1, Leads are given positive misalignment so that they grip after insertion. 2. Leads are Ni-Fe, pure tin plated. _ u Mullard (wm