CDC1607F-E
Automotive Controller
Edition May 26, 2004
6251-608-1PD
PRELIMINARY DATA SHEET
MICRONAS
MICRONAS
CDC1607F-E PRELIMINARY DATA SHEET
2May 26, 2004; 6251-608-1PD Micronas
Contents
Page Section Title
3 1. Introduction
31.1.Features
7 1.2. Abbreviations
9 2. Package and Pins
9 2.1. Package Outline Dimensions
10 2.2. Pin Assignment
11 2.3. External Components
12 3. Electrical Data
12 3.1. Absolute Maximum Ratings
13 3.2. Recommended Operating Conditions
14 3.3. Characteristics
15 3.4. Recommended Quartz Crystal Characteristics
16 4. CPU, RAM, ROM and Banking
17 5. Core Logic
17 5.1. Control Register CR
19 6. Hardware Options
19 6.1. Functional Description
20 7. Differences
22 8. Data Sheet History
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 3
1. Introduction
Release Note: Revision bars indicate significant changes to the previous edition.
The IC is a single-chip controller for use in automotive applications. The CPU on the chip is an upgrade of the 65C02 with 16-bit internal data and 24-bit address
bus. The chip consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, CAN interfaces and PWM outputs.
This document provides MCM Flash hardware-specific information. General information on operating the IC can be found in the document “CDC16xxF-E Auto-
motive Controller - Family User Manual, CDC1605F-E Automotive Controller Specification” (6251-606-1PD).
1.1. Features
Table 1–1: CDC16xxF Family Feature List
This Docu-
ment:
Item CDC1605F-E
EMU CDC1607F-E
MCM Flash CDC1631F-E
MASK ROM CDC1605F-C
EMU CDC1607F-C
MCM Flash CDC1641F-C
Mask ROM CDC1652F-C
Mask ROM CDC1672F-C
Mask ROM
Core
CPU 16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6500-series predecessors
CPU-Active Operation
Modes FAST, SLOW and DEEP SLOW FAST and SLOW
Power-Saving Modes
(CPU Inactive) WAKE and IDLE -
EMI Reduction Mode selectable in FAST mode
Oscillators 4 to 12 MHz Quartz and 20 to 57 kHz internal RC 4 MHz to 12 MHz Quartz
RAM 6 KB 2 KB 6 KB 2.75 KB 4 KB 6 KB
ROM ROMless,
external pro-
gram storage
with up to
16 MB, internal
2KB Boot
ROM
256 KB Flash,
bottom boot
configuration,
internal 2 KB
Boot ROM
64 KB ROMless,
external pro-
gram storage
with up to
16 MB, internal
2 KB Boot
ROM
256 KB Flash,
bottom boot
configuration,
internal 2 KB
Boot ROM
90 KB 128 KB 216 KB
CDC1607F-E PRELIMINARY DATA SHEET
4May 26, 2004; 6251-608-1PD Micronas
Multiplier, 8 by 8 bit ✔-
Digital Watchdog ✔
Central Clock Divider ✔
Interrupt Controller
expanding NMI 16 inputs,15 priority levels
Port Interrupts including
Slope Selection 4 inputs
Port Wake-Up Inputs
including Slope / Level
Selection
10 -
Patch Module 10 ROM locations 5 ROM loca-
tions 10 ROM locations 5 ROM loca-
tions 6 ROM locations
Boot System allows in-system downloading of
code and data into RAM via serial
link
- allows in-system downloading of
code and data into RAM via serial
link
---
Analog
Reset/Alarm Combined Input for Regulator Input Supervision
Clock and Supply
Supervision
✔
10-bit ADC, charge
balance type 9 channels (5 channels selectable as digital input)
ADC Reference VREF Pin
Comparators P06COMP with 1/2 AVDD reference
LCD Internal processing of all analog voltages for the LCD driver
Table 1–1: CDC16xxF Family Feature List, continued
This Docu-
ment:
Item CDC1605F-E
EMU CDC1607F-E
MCM Flash CDC1631F-E
MASK ROM CDC1605F-C
EMU CDC1607F-C
MCM Flash CDC1641F-C
Mask ROM CDC1652F-C
Mask ROM CDC1672F-C
Mask ROM
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 5
Communication
DMA 1 DMA Channel for serving the
Graphics Bus interface - 1 DMA Channel for serving the
Graphics Bus interface - 1 DMA Channel for serving the
Graphics Bus interface
UART 3: UART0, UART1 and UART2 1: UART0 3: UART0, UART1 and UART2 1: UART0 3: UART0, UART1 and UART2
Synchronous Serial
Peripheral Interfaces 2: SPI0 and SPI1 1: SPI0 2: SPI0 and SPI1 1: SPI0 2: SPI0 and SPI1
Full CAN modules V2.0B 3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN000F)
1: CAN0 with
256-byte object
RAM
(LCAN000F)
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN0009)
1: CAN0 with
256-byte object
RAM
(LCAN0009)
2: CAN0 and CAN1 with 256-byte
object RAM each (LCAN0009)
DIGITbus 1 master module - 1 master module - 1 master module
Input & Output
Universal Ports select-
able as 4:1 mux LCD
Segment/Backplane lines
or Digital I/O Ports
up to 52 I/O or 48 LCD segment lines (=192 segments),
in groups of two, configurable as I/O or LCD
Universal Port Slew Rate HW preselectable
Stepper Motor Control
Modules with High-Cur-
rent Ports
5 Modules, 24 dI/dt controlled ports
8-bit PWM Modules 5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4 3 Modules:
PWM0, PWM1,
PWM2
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4 2 Modules:
PWM0, PWM1 5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
Audio Module with auto-
decay
✔
SW selectable Clock out-
puts 2
Table 1–1: CDC16xxF Family Feature List, continued
This Docu-
ment:
Item CDC1605F-E
EMU CDC1607F-E
MCM Flash CDC1631F-E
MASK ROM CDC1605F-C
EMU CDC1607F-C
MCM Flash CDC1641F-C
Mask ROM CDC1652F-C
Mask ROM CDC1672F-C
Mask ROM
CDC1607F-E PRELIMINARY DATA SHEET
6May 26, 2004; 6251-608-1PD Micronas
Polling / Flash Timer Out-
put 1 High-Current Port output operable in Power-Saving
Mode -
Timers & Counters
16-bit free running
counters with Capture/
Compare modules
CCC0 with 3CAPCOM
16-bit timers 1: T0
8-bit timers 2: T1 and T2
Real Time Clock, Deliver-
ing Hours, Minutes and
Seconds
✔-
Miscellaneous
Scalable layout in CAN,
RAM and ROM -✔-✔
Various randomly select-
able HW options Most options SW programmable,
copy from user program storage
during system start-up
Mask pro-
grammed
according to
user specifica-
tion
Most options SW programmable,
copy from user program storage
during system start-up
Core Bond-Out ✔-✔-
Supply Voltage 4.5 V to 5.5 V
Temperature Range Tcase: 0 °C to
+70 °C Tcase: −40 °C to +105 °C Tamb: −40 °C to +85 °C
Package
Typ e Ceramic
177PGA Plastic 100QFP
0.65mm pitch Ceramic
177PGA Plastic 100QFP
0.65mm pitch
Bonded Pins 176 100 176 100
Table 1–1: CDC16xxF Family Feature List, continued
This Docu-
ment:
Item CDC1605F-E
EMU CDC1607F-E
MCM Flash CDC1631F-E
MASK ROM CDC1605F-C
EMU CDC1607F-C
MCM Flash CDC1641F-C
Mask ROM CDC1652F-C
Mask ROM CDC1672F-C
Mask ROM
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 7
1.2. Abbreviations
AM Audio Module
CAN Controller Area Network Module
CAPCOM Capture/Compare Module
CPU Central Processing Unit
DMA Direct Memory Access Module
ERM EMI Reduction Module
IR Interrupt Controller
LCD Liquid Crystal Display Module
P06COMP P0.6 Alarm Comparator
PINT Port Interrupt Module
PSM Power-Saving Module
PWM 8-Bit Pulse Width Modulator Module
RTC Real-time Clock
SM Stepper Motor Control Module
SPI Serial Synchronous Peripheral Interface
T0 16-Bit Timer 0
T1, T2 8-Bit Timers 1 and 2
UART Universal Asynchronous Receiver Transmitter
CDC1607F-E PRELIMINARY DATA SHEET
8May 26, 2004; 6251-608-1PD Micronas
Fig. 1–1: Block diagram of CDC1607F-E
65C816
CPU
Flash
256k x 8
CAN 0
CAN 1
CAN 2
Banking
16-Bit Timer 0
10-Bit ADC
UART 0
8-Bit PWM 2
Audio Module
Power Saving
Module
8-Bit Timer 1
Watchdog
Clock
16 Inputs
Interrupt
Controller
16-Bit
CAPCOM 0
Stepper Motor
Control
SRAM
6k x 8
UART 1
UART 2
UPort1UPort2UPort3UPort4UPort5UPort6UPort7
HPort0HPort1HPort2HPort3
8-Bit Timer 2
16-Bit
CAPCOM 1
16-Bit
CAPCOM 2
8-Bit PWM 4
8-Bit PWM 0
PPort0
SPI 0
8-Bit PWM 1
8-Bit PWM 3
Clock Out 0
Clock Out 1
DMA Logic
4
6
8
9
8
8
8
8
8
6
6
6
XTAL1
XTAL2
TEST
RESETQ
VSS
VDD UVDD
UVSS
VREF
AVDD
AVSS
HVDD1
HVSS1
HVDD2
HVSS2
Reset/Alarm
Test Patch Module
Boot ROM
DIGITbus
ERM
RTC
RC Oscillator
Multiplier
8 by 8 bit
SPI 1
LCD Control
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 9
2. Package and Pins
2.1. Package Outline Dimensions
Fig. 2–1:
PMQFP100-1: Plastic Metric Quad Flat Package, 100 leads,
14 × 20 × 2.7 mm3
Ordering code: QB
Weight approximately 1.7 g
CDC1607F-E PRELIMINARY DATA SHEET
10 May 26, 2004; 6251-608-1PD Micronas
2.2. Pin Assignment
Fig. 2–2: Pin Assignment for PMQFP100-1 Package
Pin Functions Pin
No.
Bus
Mode
LCD
Mode
Port
Special Out
Port
Special In
Basic
Function
SEG7.3 GWRQ U7.3 91
SEG7.2 GRDQ U7.2 92
SEG7.1 U7.1 93
SEG7.0 U7.0 94
UVSS 95
UVDD 96
ADB7 SEG3.7 T2-OUT U3.7 97
ADB6 SEG3.6 CC1-OUT U3.6 98
ADB5 SEG3.5 SPI1-CLK-OUT SPI1-CLK-IN U3.5 99
ADB4 SEG3.4 T0-OUT WP0 U3.4 100
ADB3 SEG3.3 CC2-OUT U3.3 1
ADB2 SEG3.2 DIGIT-OUT DIGIT-IN U3.2 2
ADB1 SEG3.1 CO1 SPI1-D-IN U3.1 3
ADB0 SEG3.0 SPI1-D-OUT U3.0 4
SEG6.7 CAN0-TX MULTI-TEST-IN U6.7 5
SEG6.6 PINT1-OUT CAN0-RX/WP1 U6.6 6
SEG6.5 T1-OUT SPI0-D-IN U6.5 7
SEG6.4 SPI0-D-OUT U6.4 8
TEST 9
RESETQ 10
XTAL2 11
XTAL1 12
VSS 13
VDD 14
SEG6.3 SPI0-CLK-OUT SPI0-CLK-IN U6.3 15
SEG6.2 T1-OUT PINT2-IN/WP5 U6.2 16
SEG6.1 LCD-CLK-OUT PINT1-IN/WP4 U6.1 17
SEG6.0 LCD-SYNC-OUT PINT0-IN/WP3 U6.0 18
WEQ SEG1.7 CAN1-TX U1.7 19
CEQ SEG1.6 CAN1-RX/WP2 U1.6 20
ITSTOUT SEG1.5 LCD-CLK-OUT U1.5 21
RWQ SEG1.4 LCD-SYNC-OUT U1.4 22
PH2 BP3 U1.3 23
OEQ BP2 U1.2 24
BE BP1 U1.1 25
RDY BP0 ITSTOUT U1.0 26
STOPCLK SMB1+ H1.5 27
VPQ SMB1- H1.4 28
VPA SMB2+ H1.3 29
VDA SMB2- SMB-COMP H1.2 30
DB7 SME1+/PWM2 H1.1 31
DB6 SME1-/PWM0 H1.0 32
HVDD1 33
HVSS1 34
DB5 SME2+ H0.5 35
DB4 SME2- SME-COMP H0.4 36
DB3 SMA1+ H0.3 37
DB2 SMA1- H0.2 38
DB1 SMA2+ H0.1 39
DB0 SMA2- SMA-COMP H0.0 40
Pin
No.
Pin Functions
Basic
Function
Port
Special In
Port
Special Out
LCD
Mode
Bus
Mode
90 U4.0 CAN2-RX/WP7 SEG4.0 ADB8
89 U4.1 CAN2-TX SEG4.1 ADB9
88 U4.2 UART2-RX SEG4.2 ADB10
87 U4.3 UART2-TX SEG4.3 ADB11
86 U4.4 UART0-RX/WP8 SEG4.4 ADB12
85 U4.5 UART0-TX SEG4.5 ADB13
84 U4.6 CC2-IN CC1-OUT SEG4.6 ADB14
83 U4.7 CC1-IN SEG4.7 ADB15
82 U5.0 CC0-IN CO1 SEG5.0
81 U5.1 INT-TEST-IN CC0-OUT SEG5.1
80 U5.2 LCD-CLK-IN AM-PWM SEG5.2
79 U5.3 LCD-SYNC-IN AM-OUT SEG5.3
78 U5.4 IRQ UART1-TX SEG5.4
77 U5.5 ABORTQ CO0 SEG5.5
76 U5.6 PINT3/WP6 PWM2 SEG5.6
75 U5.7 PINT3/UART1-RX PINT0-OUT SEG5.7
74 U2.0/GD0 SEG2.0 ADB16
73 U2.1/GD1 SEG2.1 ADB17
72 U2.2/GD2 SEG2.2 ADB18
71 U2.3/GD3 SEG2.3 ADB19
70 U2.4/GD4 SEG2.4 ADB20
69 U2.5/GD5 SEG2.5 ADB21
68 U2.6/GD6 SEG2.6 ADB22
67 U2.7/GD7 SEG2.7 ADB23
66 AVSS
65 AVDD
64 VREF
63 P0.1 P0.1 digital input
62 P0.2 P0.2 digital input
61 P0.3 P0.3 digital input
60 P0.4 P0.4 digital input
59 P0.5 P0.5 digital input
58 P0.6 P0.6 Compar. inp.
57 P0.7
56 P0.8
55 P0.9
54 H2.0 SMC-COMP SMC2-
53 H2.1 SMC2+
52 H2.2 SMC1-
51 H2.3 SMC1+
50 H2.4 WP9 PWM0
49 H2.5/Pol PWM4
48 HVSS2
47 HVDD2
46 H3.0 PWM1
45 H3.1 PWM3
44 H3.2 SMD-COMP SMD2-
43 H3.3 SMD2+
42 H3.4 SMD1-
41 H3.5 SMD1+
1
30
80
51
31 50
81100 91 90
4140
NC = not connected,
leave vacant
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 11
2.3. External Components
Fig. 2–3: Recommended external supply and quartz connection for low electromagnetic interference (EMI)
To provide effective decoupling and to improve EMC behav-
ior, the small decoupling capacitors must be located as close
to the supply pins as possible. The self-inductance of these
capacitors and the parasitic inductance and capacitance of
the interconnecting traces determine the self-resonant fre-
quency of the decoupling network. A frequency too low will
reduce decoupling effectiveness, increase RF emissions and
may affect device operation adversely.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other PC board signals. It is
strongly recommended to place quartz and oscillation capac-
itors as close to the pins as possible and to shield the XTAL1
and XTAL2 traces from other signals by embedding them in
a VSS trace.
The RESETQ pin adjacent to XTAL2 should be supplied with
a 47 nF capacitor, to prevent fast RESETQ transients from
being coupled into XTAL2, to prevent XTAL2 from coupling
into RESETQ, and to guarantee a time constant of ≥200 µs,
sufficient for proper Wake Reset functionality.
C
18 p
18 p
UVDD
VDD
VSS
UVSS
XTAL1
XTAL2
IC
System
Ground
L
47 n
Resetq
+5 V
+5 V
4.7 k
AVSS
VREF
AVDD
HVSS 0 to 1
HVDD 0 to 1
RESETQ
C
C
2 * C
10 n
+5 V
+5 V Analog
System
Ground
Analog
Ground
C = 100 n to 150 n C = 100 n to 150 n
CDC1607F-E PRELIMINARY DATA SHEET
12 May 26, 2004; 6251-608-1PD Micronas
3. Electrical Data
3.1. Absolute Maximum Ratings
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings condi-
tions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated volt-
ages to this high-impedance circuit.
1) This condition represents the worst case load with regard to the intended application.
Table 3–1: All voltages listed are referenced to ground (UVSS=HVSSn=AVSS=0V), except where noted. All ground pins except
VSS must be connected to a low-resistive ground plane close to the IC.
Symbol Parameter Pin Name Min. Max. Unit
VSUP Core Supply Voltage
Port Supply Voltage
Analog Supply Voltage
SM Supply Voltage 1
SM Supply Voltage 2
VDD
UVDD
AVDD
HVDD1
HVDD2
−0.3 6.0 V
∆VDD Voltage Difference between VDD and
AVDD, resp. UVDD VDD, AVDD
UVDD −0.5 0.5 V
ISUP Core Supply Current
Port Supply Current VDD, VSS
UVDD, UVSS −100 100 mA
IASUP Analog Supply Current AVDD, AVSS −20 20 mA
IHSUP SM Supply Current
@Tj=105 °C, Duty Factor = 0.71 1) HVDD1, HVSS1
HVDD2, HVSS2 −380 380 mA
Vin Input Voltage U-Ports,
XTAL,RESETQ,
TEST
UVSS−0.5 UVDD+0.7 V
P0-Ports
VREF UVSS−0.5 AVDD+0.7 V
H-Ports HVSS−0.5 HVDD+0.7 V
Iin Input Current all Inputs 0 2 mA
IoOutput Current U-Ports −55 mA
H-Ports −60 60 mA
toshsl Duration of Short Circuit in Port SLOW
Mode to UVSS or UVDD U-Ports except
U3.2 in DP Mode indefinite s
TjJunction Temperature under Bias −45 115 °C
TsStorage Temperature −45 125 °C
Pmax Maximum Power Dissipation 0.8 W
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 13
3.2. Recommended Operating Conditions
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.
Keep UVDD=AVDD during all power-up and power-down sequences.
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteristics” is not
implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.
Table 3–2: All voltages listed are referenced to ground (UVSS=HVSSn=AVSS=0V), except where noted. All ground pins except
VSS must be connected to a low-resistive ground plane close to the IC .
Symbol Parameter Pin Name Min. Typ. Max. Unit
VDD Supply Voltage
Port Supply Voltage
Analog Supply Voltage
VDD
UVDD
AVDD
4.5 5 5.5 V
HVDD SM Supply Voltage 1
SM Supply Voltage 2 HVDD1
HVDD2 4.75 5 5.25 V
∆VDD Voltage Difference between VDD
and AVDD resp. UVDD VDD, AVDD
UVDD −0.2 0.2 V
dAVDD AVDD Ripple, Peak-to-Peak AVDD 200 mV
fXTAL XTAL Clock Frequency XTAL1 4 12 MHz
XTAL Clock Frequency
using ERM XTAL1 4 10 MHz
Vil Low Input Voltage U-Ports
H-Ports
P0-Ports
TEST
0.51*VDD V
Vih High Input Voltage U-Ports
H-Ports
P0-Ports
TEST
0.86*VDD V
RVil Reset Active Input Voltage RESETQ 0.9 V
WRVil Reset Active Input Voltage during
Power-Saving Modes and Wake
Reset
RESETQ 0.6 V
RVim Reset Inactive and Alarm Active
Input Voltage RESETQ 1.6 2.1 V
RVih Reset Inactive and Alarm Inactive
Input Voltage RESETQ 2.9 V
WRVih Reset Inactive during Power-Sav-
ing Modes RESETQ UVDD
− 0.4V V
VREFi ADC Reference Input Voltage VREF 2.56 AVDD V
P0ViP0 ADC Input Port Input Voltage P0-Ports 0 VREFi V
Clock Input from External Generator
XVil Clock Input Low Voltage XTAL1 0.2*VDD V
XVih Clock Input High Voltage XTAL1 0.8*VDD V
DXTAL Clock Input High-to-Low Ratio XTAL1 0.45 0.55
CDC1607F-E PRELIMINARY DATA SHEET
14 May 26, 2004; 6251-608-1PD Micronas
3.3. Characteristics
Listed are only those characteristics that differ from Chapter 3.3 of Document “CDC16xxF-E Automotive Controller - Family User
Manual, CDC1605F-E Automotive Controller Specification” (6251-606-1PD). All not differing characteristics, that are not listed
here, apply, but in a TCASE temperature range extended to −40 °C to +105 °C.
Table 3–3: UVSS = HVSS1 = HVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD < 5.5 V,
4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = −40 °C to +105 °C, fXTAL = 10 MHz
Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Package
Rthjc Thermal Resistance from
Junction to Case 9 C/W measured on Micronas
typical 2-layer board,
1s1p, described in docu-
ment “Integrated Circuits
- Thermal Characteriza-
tion of Packages” (6200-
266-1E) (modified
JESD-51.3)
Rthja Thermal Resistance from
Junction to Ambient 31 C/W
Supply Currents CMOS levels on all
Inputs,
no Loads on Outputs,
difference between any
two VDDs within ±0.2 V
IDDF VDD FAST Mode Supply
Current VDD 35 65 mA Flash Read 3)
45 85 mA Flash Write/Erase 3)
IDDS VDD SLOW Mode Supply
Current VDD 1.5 2.0 mA all Modules OFF 2), 3)
all clocks disabled by
hardware option settings
2.5 3.5 mA all Modules OFF 2), 3)
all hardware options set
to their RESET values
IDDD VDD DEEP SLOW Mode
Supply Current VDD 0.75 1.0 mA all Modules OFF 2), 3)
all hardware options set
to their RESET values
IDDI VDD IDLE Mode Supply
Current VDD 70 135 µAf
xtal = 4 MHz 3)
180 260 µAf
xtal = 10 MHz 3)
12 55 µA internal RC oscill.
IDDW VDD WAKE Mode Supply
Current VDD 1 50 µA
UIDDa UVDD Active Supply Cur-
rent UVDD 0.3 mA no Output Activity,
LCD Module ON
AIDDa AVDD Active Supply Cur-
rent AVDD 0.2 0.4 mA ADC ON, ERM OFF
1 2 mA ADC ON, ERM ON
2) Value may be exceeded with unusual Hardware Option setting
3) Measured with external clock. Add 100 µA at 4 MHz, 115 µA at 10 MHz for operation on typical quartz with SR3.XTAL = 0
(Oscillator RUN mode).
1) Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 15
3.4. Recommended Quartz Crystal Characteristics
See Chapter 3.4 of document “CDC16xxF-E Automotive Controller - Family User Manual, CDC1605F-E Automotive Controller
Specification” (6251-606-1PD).
AIDDq Quiescent Supply Current AVDD 1 10 µA ADC and ERM OFF
UIDDq UVDD 1 10 µA no Output Activity,
LCD Module OFF
EIDDq EVDD1
EVDD2 110µA no Output Activity
HIDDq Sum of all
HVDD1
HVDD2
120µA no Output Activity,
SM Module OFF
Table 3–3: UVSS = HVSS1 = HVSS2 = AVSS = 0 V, 4.5 V < VDD = AVDD = UVDD < 5.5 V,
4.75 V < HVDD1 = HVDD2 < 5.25 V, TCASE = −40 °C to +105 °C, fXTAL = 10 MHz
Symbol Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
1) Typical values describe typical behavior at room temperature (25 °C, unless otherwise noted), with typical
Recommended Operating Conditions applied, and are not 100% tested.
CDC1607F-E PRELIMINARY DATA SHEET
16 May 26, 2004; 6251-608-1PD Micronas
4. CPU, RAM, ROM and Banking
Fig. 4–1: Address Map
256 KB
Flash
EEPROM
mirrored
Flash
EEPROM
000000
001800
002000
042000
FFFFFF
MCM
008000
010000
018000
028000
030000
038000
040000
phys.addr.
020000
Bank 5
Bank 8
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
log.addr.
Alternative Native
log.addr.
000000
010000
00FFFF
020000
01FFFF
030000
02FFFF
040000
03FFFF
041FFF
7FFF
0000
FFFF
8000
8000
9FFF
PQFP100
Bank 0
004000
006000
Sector 0,
Sector 1,
Sector 2,
Sector 3,
Sector 4,
Sector 5,
Sector 6,
Sector 0,
001900
001A00
001B00
001C00
001D00
001E00
001F00
Bank 6
FFFF
8000
Bank 7
FFFF
8000
Bank 1
FFFF
8000
Bank 2
FFFF
8000
Bank 3
FFFF
8000
Bank 4
FFFF
8000
Reserved
CAN2-RAM
CAN1-RAM
CAN0-RAM
CAN-Regs
Ext. I/O
I/O-Reg1
I/O-Reg0
6K RAM
Bottom Boot Config.
F800
Boot ROM Boot ROM
The device contains a 256 KB Flash
EEPROM of the AMD Am29F200BT type
(bottom boot configuration). This device exhibits
electrical byte program and sector erase
functions. Refer to the AMD data sheet for
details.
upper 8 KB
8 KB
8 KB
32 KB
64 KB
64 KB
64 KB
lower 8 KB
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 17
5. Core Logic
5.1. Control Register CR
The Control Register CR serves to configure the ways by
which certain system resources are accessed during opera-
tion. The main purpose is to obtain a variable system config-
uration during IC test.
Upon each HIGH transition on the RESETQ pin, internal
hardware reads data from the address location 00FFF3h and
stores it to the CR. The state of the TEST and ESTOPCLK
pins at this timepoint specifies which program storage source
is accessed for this read:
The system will thus start up according to the configuration
defined in address location 00FFF3h, automatically copied to
register CR.
RESLNG Reset Pulse Length
r/w1: Pulse length is 16/FXTAL
r/w0: Pulse length is 4096/FXTAL
This bit specifies the length of the reset pulse which is output
at pin RESETQ following an internal reset. If pin TEST is 1
the first reset after power on is short. The following resets
are as programmed by RESLNG. If pin TEST is 0, all resets
are long.
TSTTOG TEST Pin Toggle (Tables 5–2 and 5–3)
This bit is used for test purposes only. If TSTTOG is true in
IC active mode, pin TEST can toggle the multifunction pins
between Bus mode and normal mode.
EBTRI Emulator Data Bus Tristate (Table 5–3)
MFM Multifunction Pin Mode
(Tables 5–2 and 5–3)
TSTROM TestROM (Table 5–4)
FLASH FLASH EEPROM (Table 5–5)
IROM Internal ROM (Tables 5–4 and 5–5)
Table 5–1: Control byte source
TEST Control byte source
0 or NC internal BOOT ROM
(standard for stand-alone operation)
1 external, via multifunction pins in Bus
mode (for test purposes only)
CR Control Register
76543210
r/w RESLNG TSTTOG x MFM TSTROM IROM IRAM ICPU ROM
r/w RESLNG TSTTOG EBTRI MFM FLASH IROM IRAM ICPU Emu
Value of 00FFF3h Res
Table 5–2: TSTTOG and MFM usage in mask ROM parts
TSTTOG MFM TEST pin Multifunction
Pins
00xBus mode
100Bus mode
1 normal mode
x1xnormal mode
Table 5–3: TSTTOG, EBTRI and MFM usage in Flash and
EMU parts
TST-
TOG EBT
RI MFM TEST
pin Multi-
function
Pins
Emula-
tor Bus
Pins
0x0xBus
mode Flash
mode
1x00Bus
mode Flash
mode
1 normal
mode
x 0 1 x normal
mode Emula-
tor mode
1 Flash
mode
Table 5–4: TSTROM and IROM usage in mask ROM parts
TSTROM IROM selected program storage
1 1 internal ROM
0 internal TestROM
x 0 external via Multifunction pins
in Bus mode
CDC1607F-E PRELIMINARY DATA SHEET
18 May 26, 2004; 6251-608-1PD Micronas
IRAM Internal RAM
r/w1: Enable internal RAM.
r/w0: Disable internal RAM.
ICPU Internal CPU
r/w1: Enable internal CPU.
r/w0: Disable internal CPU.
Table 5–5: FLASH and IROM usage in FLASH and EMU
parts
FLASH IROM selected program storage
1 1 internal FLASH EEPROM
resp. Emulator Bus
0 internal BOOT ROM
x 0 external via Multifunction pins
in Bus mode
Table 5–6: Some commonly used settings for address
location 00FFF3h. A copy is automatically transferred to the
CR during IC start-up.
Code TEST
Pin Operation Mode
FFh 0 Stand-alone with internal ROM or Flash
ABh 1 External program storage connected to
multifunction pins in Bus mode
DFh 0 Emulator mode (CPGA177 package)
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 19
6. Hardware Options
6.1. Functional Description
Hardware Options are available in several areas to
adapt the IC function to the host system requirements:
– clock signal selection for most of the peripheral
modules from fosc to fosc/217 plus some internal sig-
nals. (see table in Chapter Hardware Options of
document “CDC16xxF-E Automotive Controller - Family
User Manual, CDC1605F-E Automotive Controller Speci-
fication” (6251-606-1PD))
– interrupt source selection for interrupt inputs 5, 6, 7,
13, 14 and 15
– Special Out signal selection for some U and H-ports
– Rx/Tx polarity selection for SPI and UART modules
– U-port Port Slow Mode selection
Hardware Option setting requires two steps:
1. selection is done by programming dedicated
address locations with the desired options’ code
2. activation is done by a read access to these dedi-
cated address locations at least once after each reset.
Address locations 00FFB8h through 00FFBFh do not
allow random setting. Their respective Hardware
Options are hard-wired and can only be altered by
changing a production mask for this IC. By default, the
Port Slow Option is set for all U-Ports, with the excep-
tion of U1.0 to U1.3 (Port Fast Option is set). The
Watchdog and Clock Monitor are activated via soft-
ware by default.
Future mask ROM derivatives of this IC will not require
(but will tolerate) activation of option settings by read
accesses, as the ROM as well as the options will be
hard-wired. Instead, the manufacturer will automati-
cally process the setting of the dedicated address
locations, as given in the ROM code file, to set the
required mask changes.
To ensure compatible option settings in this IC and
mask ROM derivatives when run with the same ROM
code, it is recommended to always read locations
00FFA0h through 00FFC3h directly after reset. Please
note that the non-programmable locations 00FFB8h
through 00FFBFh may not be compatible within this IC
and the mask ROM derivative.
CDC1607F-E PRELIMINARY DATA SHEET
20 May 26, 2004; 6251-608-1PD Micronas
7. Differences
This chapter describes differences of this document to pre-
decessor document “CDC1607F-E Automotive Controller”,
of March 31, 2003, 6251-608-2AI.
#Section Description
1 1. Introduction 1.1. Features, Table 1–1: CDC16xxF Family Feature List, page 4:
Interrupt Controller expanding NMI: “16 priority levels” changed into “15 priority levels” and
no. of “Port Wake-Up Inputs including Slope / Level Selection” added.
1.1. Features, Table 1–1: CDC16xxF Family Feature List, page 6:
Temperature Range, CDC1605F-E EMU: “Tcase: −40 °C to +105 °C“ changed into “Tcase: 0
to +70 °C“.
2 2. Package and Pins 2.1. Package Outline Dimensions, Fig. 2–1: changed.
2.3. External Components: Fig. 2–3: “Recommended external supply and quartz connection
for low electromagnetic interference (EMI)” corrected.
3 3. Electrical Data 3.1. Absolute Maximum Ratings: Revised introduction.
3.2. Recommended Operating Conditions:
Revised Introduction; Tj removed.
3.3. Characteristics:
Heading revised and reference added,
Table 3–3: footnote 6 and some values revised,
Rthjc, Rthja: Test Conditions added,
AIDDa: Test Conditions changed.
3.4. Recommended Quartz Crystal Characteristics: Table 3-4 removed and reference
added instead.
4 6. Core Logic 5.1. Control Register CR:
The description of RESLNG corrected.
5 7. Differences Updated
PRELIMINARY DATA SHEET CDC1607F-E
Micronas May 26, 2004; 6251-608-1PD 21
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
CDC1607F-E PRELIMINARY DATA SHEET
22 May 26, 2004; 6251-608-1PD Micronas
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com
Printed in Germany
Order No. 6251-608-1PD
8. Data Sheet History
1. Advance Information: “CDC1607F-E Automotive Control-
ler Specification”, Feb. 17, 2003, 6251-608-1AI. First release
of the advance information. Originally created for the HW
version CDC1607F-E1.
2. Advance Information: “CDC1607F-E Automotive Control-
ler Specification”, March 31, 2003, 6251-608-2AI. Second
release of the advance information. Originally created for the
HW version CDC1607F-E2.
3. Preliminary Datasheet: “CDC1607F-E Automotive Con-
troller”, May 26, 2004, 6251-608-1PD. First release of the
preliminary datasheet. Originally created for the HW version
CDC1607F-E2.
