19-1908; Rev 0; 5/01 KIT ATION EVALU E L B A AVAIL Quad LVDS Line Receivers with Integrated Termination Features Integrated Termination Eliminates Four External Resistors (MAX9126) Pin Compatible with DS90LV032A Guaranteed 500Mbps Data Rate 300ps Pulse Skew (max) Conform to ANSI TIA/EIA-644 LVDS Standard Single +3.3V Supply Low 70A Shutdown Supply Current Fail-Safe Circuit Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX9125EUE -40C to +85C 16 TSSOP MAX9125ESE -40C to +85C 16 SO MAX9126EUE -40C to +85C 16 TSSOP MAX9126ESE -40C to +85C 16 SO Typical Application Circuit LVDS SIGNALS MAX9126 MAX9124 Applications TX 115 RX TX 115 RX Digital Copiers Laser Printers Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects LVTTL/LVCMOS DATA INPUT LVTTL/LVCMOS DATA OUTPUT DSLAMs Network Switches/Routers TX 115 RX TX 115 RX Backplane Interconnect Clock Distribution Pin Configuration appears at end of data sheet. 100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9125/MAX9126 General Description The MAX9125/MAX9126 quad low-voltage differential signaling (LVDS) line receivers are ideal for applications requiring high data rates, low power, and reduced noise. The MAX9125/MAX9126 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100. The transmission media may be printed circuit (PC) board traces or cables. The MAX9125/MAX9126 accept four LVDS differential inputs and translate them to 3.3V CMOS outputs. The MAX9126 features integrated parallel termination resistors (nominally 115), which eliminate the requirement for four discrete termination resistors and reduce stub length. The MAX9125 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices support a wide common-mode input range of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. The EN and EN inputs control the high-impedance output and are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The MAX9125/ MAX9126 operate from a single +3.3V supply, are specified for operation from -40C to +85C, and are available in 16-pin TSSOP and SO packages. Refer to the MAX9124 data sheet for a quad LVDS line driver. MAX9125/MAX9126 Quad LVDS Line Receivers with Integrated Termination ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-0.3V to (VCC + 0.3V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model) IN_+, IN_-, OUT_............7.5kV Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 100 mV LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold VTH Differential Input Low Threshold VTL -100 mV 0.1V VID 0.6V, -20 20 Input Current (MAX9125) IIN_+, IIN_- 0.6V <VID 1.0V -25 25 Power-Off Input Current (MAX9125) IIN_+, IIN_- 0.1V VID 0.6V, VCC = 0 -20 20 0.6V <VID 1.0V, VCC = 0 -25 25 Input Resistor 1 RIN1 VCC = +3.6V or 0, Figure 1 35 k Input Resistor 2 RIN2 VCC = +3.6V or 0, Figure 1 132 k Differential Input Resistance (MAX9126) RDIFF VCC = +3.6V or 0, Figure 1 90 115 Open, undriven short, or undriven 100 parallel termination 2.7 3.2 VID = +100mV 2.7 3.2 Open or undriven short 2.7 3.2 VID = +100mV 2.7 3.2 132 A A LVCMOS/LVTTL OUTPUTS (OUT_) IOH = -4.0mA (MAX9125) Output High Voltage VOH IOH = -4.0mA (MAX9126) 2 0.1 V Output Low Voltage VOL IOL = +4.0mA, VID = -100mV 0.25 V Output Short-Circuit Current IOS Enabled, VID = +100mV, VOUT_ = 0 (Note 2) -15 -120 mA Output High-Impedance Current IOZ Disabled, VOUT_ = 0 or VCC -10 +10 A _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination (VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS (EN, EN) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL 0 0.8 V Input Current IIN VIN = VCC or 0 -15 15 A Supply Current ICC Enabled, inputs open 9 15 mA Disabled Supply Current ICCZ Disabled, inputs open 70 500 A SUPPLY AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, CL = 10pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL MIN TYP MAX UNITS Figures 2 and 3 1.8 2.4 3.3 ns tPLHD Figures 2 and 3 1.8 2.3 3.3 ns Differential Pulse Skew [tPHLD - tPLHD] (Note 5) tSKD1 Figures 2 and 3 100 300 ps Differential Channel-to-Channel Skew (Note 6) tSKD2 Figures 2 and 3 400 ps Differential Part-to-Part Skew (Note 7) tSKD3 Figures 2 and 3 0.8 ns Differential Part-to-Part Skew (Note 8) tSKD4 Figures 2 and 3 1.5 ns Rise Time tTLH Figures 2 and 3 0.34 1.2 ns Fall Time tTHL Figures 2 and 3 0.32 1.2 ns Disable Time High to Z tPHZ RL = 2k, Figures 4 and 5 12 ns Disable Time Low to Z tPLZ RL = 2k, Figures 4 and 5 12 ns Enable Time Z to High tPZH RL = 2k, Figures 4 and 5 17 ns Enable Time Z to Low tPZL RL = 2k, Figures 4 and 5 17 ns Maximum Operating Frequency (Note 9) fMAX All channels switching Differential Propagation Delay High to Low tPHLD Differential Propagation Delay Low to High CONDITIONS 250 300 MHz _______________________________________________________________________________________ 3 MAX9125/MAX9126 DC ELECTRICAL CHARACTERISTICS (continued) AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, CL = 10pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH , VTL, and VID. Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSKD1 is the magnitude difference of differential propagation delays in a channel; tSKD1 = |tPHLD - tPLHD|. Note 6: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 7: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 8: tSKD4 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX generator output conditions: tR = tF < 1ns (0% to 100%), 50% duty cycle, VOL = 1.1V, VOH = 1.3V. Receiver output criteria: 60% to 40% duty cycle, VOL = 0.4V (max), VOH = 2.7V (min), load = 10pF. Typical Operating Characteristics (VCC = +3.3V, |VID| = 200mV, VCM = +1.2V, CL = 10pF, frequency = 10MHz, TA = +25C, unless otherwise noted.) (Figures 2 and 3) 70 60 VCC = +3.6V 50 40 VCC = +3.3V 30 20 10 tPHLD 2.4 tPLHD 2.2 VCC = +3V 0 0.1 1 10 100 SWITCHING FREQUENCY (MHz) 1000 MAX9125/6 toc03 2.7 2.6 2.5 tPLHD tPHLD 2.4 2.3 2.2 2.0 0.01 4 2.6 2.8 DIFFERENTIAL PROPAGATION DELAY (ns) 80 2.8 MAX9125/6 toc02 90 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9125/6 toc01 100 DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE SUPPLY CURRENT vs. SWITCHING FREQUENCY, FOUR CHANNELS SWITCHING SUPPLY CURRENT (mA) MAX9125/MAX9126 Quad LVDS Line Receivers with Integrated Termination -40 -15 10 35 TEMPERATURE (C) 60 85 100 500 900 1300 1700 2100 DIFFERENTIAL INPUT VOLTAGE (mV) _______________________________________________________________________________________ 2500 Quad LVDS Line Receivers with Integrated Termination DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE tPHLD 2.4 2.3 tPLHD 175 2.5 150 tPHLD SKEW (ps) DIFFERENTIAL PROPAGATION DELAY (ns) 2.5 PULSE SKEW vs. SUPPLY VOLTAGE 200 MAX9125/6 toc05 2.6 MAX9125/6 toc04 2.4 100 2.3 75 tPLHD 2.2 2.2 0 0.5 1.0 1.5 2.0 50 3.0 2.5 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 SUPPLY VOLTAGE (V) COMMON-MODE VOLTAGE (V) 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) TRANSITION TIME vs. CAPACITIVE LOAD PULSE SKEW vs. TEMPERATURE 1000 MAX9125/6 toc07 200 900 150 125 100 tTLH 800 TRANSITION TIME (ps) 175 SKEW (ps) 125 MAX9125/6 toc08 DIFFERENTIAL PROPAGATION DELAY (ns) 2.6 MAX9125/6 toc06 DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE 700 600 tTHL 500 400 300 200 75 100 50 0 -40 -15 10 35 60 85 TEMPERATURE (C) 5 10 15 20 25 CAPACITIVE LOAD (pF) Pin Description PIN NAME 1, 7, 9, 15 IN_- Inverting Differential Receiver Inputs FUNCTION 2, 6, 10, 14 IN_+ Noninverting Differential Receiver Inputs 3, 5, 11, 13 OUT_ LVCMOS/LVTTL Receiver Outputs 4, 12 EN, EN 8 GND Ground 16 VCC Power Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Receiver Enable Inputs. When EN = low and EN = high, the outputs are disabled and in high impedance. For other combinations of EN and EN, the outputs are active. _______________________________________________________________________________________ 5 MAX9125/MAX9126 Typical Operating Characteristics (continued) (VCC = +3.3V, |VID| = 200mV, VCM = +1.2V, CL = 10pF, frequency = 10MHz, TA = +25C, unless otherwise noted (Figures 2 and 3).) MAX9125/MAX9126 Quad LVDS Line Receivers with Integrated Termination Table 1. Input/Output Function Table ENABLES EN EN L H All other combinations of ENABLE inputs INPUTS OUTPUT (IN_+) - (IN_-) OUT_ X Z VID +100mV H VID -100mV L MAX9125 Open, undriven short, or undriven 100 parallel termination MAX9126 Open or undriven short VCC H VCC RIN2 RIN2 VCC - 0.3V VCC - 0.3V IN_+ IN_+ RIN1 RIN1 OUT_ OUT_ RDIFF RIN1 RIN1 IN_- IN_MAX9125 MAX9126 Figure 1. Inputs with Internal Fail-Safe Circuitry Detailed Description The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9125/MAX9126 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-power applications. Each channel accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver is capable of detecting differential signals as low as 100mV and as high as 1V within an 6 input voltage range of 0 to 2.4V. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a +1.2V offset. This offset, coupled with the receiver's 0 to 2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the transmitter and the receiver, the commonmode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to 2.4V referenced to receiver ground. The MAX9126 has an integrated termination resistor internally connected across each receiver input. The internal termination saves board space, eases layout, and reduces "stub length" compared to an external termination resistor. In other words, the transmission line is terminated on the IC. _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination MAX9125/MAX9126 IN_+ PULSE** GENERATOR OUT_ IN_50* 50* CL RECEIVER ENABLED 1/4 MAX9125/MAX9126 *50 REQUIRED FOR PULSE GENERATOR. **WHEN TESTING MAX9126, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR. Figure 2. Transition Time and Propagation Delay Test Circuit IN_VID O (DIFFERENTIAL) O (DIFFERENTIAL) IN_+ tPHLD tPLHD VOH 80% NOTE: VCM = 80% (VIN_- + VIN_+) 2 50% 50% 20% OUT_ 20% tTLH tTHL VOL Figure 3. Transition Time and Propagation Delay Timing Diagram VCC IN_+ GENERATOR EN 50 IN_- S1 RL DEVICE UNDER TEST OUT_ CL EN 1/4 MAX9125/MAX9126 CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS. Figure 4. High-Z Delay Test Circuit _______________________________________________________________________________________ 7 MAX9125/MAX9126 Quad LVDS Line Receivers with Integrated Termination EN WHEN EN = VCC 3V 1.5V 1.5V 0 3V 1.5V 1.5V 0 EN WHEN EN = GND tPZL VCC tPLZ OUTPUT WHEN VID = -100mV 50% 0.5V VOL tPZH tPHZ OUTPUT WHEN VID = +100mV VOH 0.5V 50% GND Figure 5. High-Z Delay Waveforms Fail-Safe The fail-safe feature of the MAX9125/MAX9126 sets the output high when: * Inputs are open. * Inputs are undriven and shorted. * Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the LVDS driver outputs are high impedance. A short condition can occur because of a cable failure. The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC 0.3V, activating the fail-safe circuit and forcing the output high. Applications Information Power-Supply Bypassing Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel, as close to the device as possible, with the smaller valued capacitor closest to VCC. Differential Traces Input trace characteristics affect the performance of the MAX9125/MAX9126. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and vias to further prevent impedance discontinuities. Cables and Connectors Transmission media typically have a controlled differential impedance of 100. Use cables and connectors 8 _______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination Termination The MAX9126 has an integrated termination resistor connected across the inputs of each receiver. The value of the integrated resistor is specified in the DC characteristics. The MAX9125 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values range between 90 and 132, depending on the characteristic impedance of the transmission medium. Board Layout Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. For LVDS applications, use a four-layer PC board that provides separate power, ground, LVDS signals, and output signals. Isolate the input LVDS signals from the output LVCMOS/LVTTL signals to prevent coupling. Separate the input LVDS signal plane from the LVCMOS/LVTTL output signal plane with the power and ground planes for best results. Chip Information TRANSISTOR COUNT: 940 PROCESS: CMOS When using the MAX9125, minimize the distance between the input termination resistors and the MAX9125 receiver inputs. Use 1% surface-mount resistors. _______________________________________________________________________________________ 9 MAX9125/MAX9126 that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. MAX9125/MAX9126 Quad LVDS Line Receivers with Integrated Termination Functional Diagram VCC VCC IN1+ IN1+ Rx OUT1 IN1- IN1- IN2+ IN2+ Rx OUT2 IN2- IN2- IN3+ IN3+ Rx OUT3 IN3- IN3- IN4+ IN4+ Rx OUT4 IN4- IN4- EN EN EN EN MAX9125 RDIFF Rx OUT1 RDIFF Rx OUT2 RDIFF Rx OUT3 RDIFF Rx OUT4 MAX9126 GND GND Pin Configuration TOP VIEW IN1- 1 16 VCC IN1+ 2 15 IN4- OUT1 3 14 IN4+ EN 4 OUT2 5 MAX9125 MAX9126 13 OUT4 12 EN IN2+ 6 11 OUT3 IN2- 7 10 IN3+ GND 8 9 IN3- TSSOP/SO 10 ______________________________________________________________________________________ Quad LVDS Line Receivers with Integrated Termination TSSOP,NO PADS.EPS ______________________________________________________________________________________ 11 MAX9125/MAX9126 Package Information Quad LVDS Line Receivers with Integrated Termination SOICN.EPS MAX9125/MAX9126 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.