350 mA, Low VIN, Low Quiescent Current,
CMOS Linear Regulator
Data Sheet ADP130
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
350 mA maximum output current
Input voltage supply range
VBIAS = 2.3 V to 5.5 V
VIN = 1.2 V to 3.6 V
2.3 V < VIN < 3.6 V, VIN can be tied to VBIAS
Very low dropout voltage: 17 mV @ 100 mA load
Low quiescent current: 25 µA @ no load
Low shutdown current: <1 µA
±1% accuracy @ 25°C
Excellent PSRR performance: 70 dB @ 10 kHz
Excellent load/line transient response
Optimized for small 1 F ceramic capacitors
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
APPLICATIONS
Mobile phones
Digital camera and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
TYPICAL APPLICATION CIRCUITS
06963-001
ADP130
1
VIN
2
GND
3
EN
5
VOUT
4
VBIAS
+
V
IN
= 1. 8V V
OUT
= 1.2V
1µF +1µF
V
BIAS
= 3. 6V
+1µF
OFF
ON
Figure 1.
06963-002
ADP130
1
VIN
2
GND
3
EN
5
VOUT
4
VBIAS
+
V
IN
= 2. 8V V
OUT
= 1.8V
1µF +1µF
V
BIAS
= 5V
+1µF
OFF
ON
Figure 2.
GENERAL DESCRIPTION
The ADP130 is a low quiescent current, low dropout linear regu-
lator. It is designed to operate in dual-supply mode with an input
voltage as low as 1.2 V to increase efficiency and provide up to
350 mA of output current. The low 17 mV dropout voltage at
a 100 mA load improves efficiency and allows operation over
a wider input voltage range.
A dual-supply power solution typically improves conversion
efficiency over a single-supply solution because the higher VBIAS
supply powers the part, and the lower VIN supply delivers current
to the load. The power dissipated in the device is thereby reduced.
The ADP130 is optimized for stable operation with small 1 μF
ceramic output capacitors. The ADP130 delivers good transient
performance with minimal board area.
The ADP130 is available in fixed output voltages ranging from :
0.80 V to 3.0 V.
The ADP130 has a typical internal soft start time of 200 μs. Short-
circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP130 is available
in a tiny 5-lead TSOT package for the smallest footprint solution to
meet a variety of portable power applications.
ADP130 Data Sheet
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor: Recommended Specifications.. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Capacitor Selection .................................................................... 13
Undervoltage Lockout ............................................................... 14
Enable Feature ............................................................................ 14
Current Limit and Thermal Overload Protection ................. 15
Thermal Considerations ............................................................ 15
Junction Temperature Calculations ......................................... 16
PCB Layout Considerations ...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/12—Rev. B to Rev. C
Changed EN to GND Absolute Maximum Rating from −0.3 V
to +6 V to −0.3 V to VBIAS. ........................................................... 5
Changes to Ordering Guide .......................................................... 18
5/10—Rev. A to Rev. B
Changes Figure 1 and Figure 2 ....................................................... 1
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
3/09—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Figure 18 to Figure 21 .................................................. 9
Changes to Figure 22 to 26 ............................................................ 10
7/08—Revision 0: Initial Version
Data Sheet ADP130
Rev. C | Page 3 of 20
SPECIFICATIONS
VIN = VOUT + 0.4 V, VBIAS = 5 V, IOUT = 10 mA, CIN = 1 F, COUT = 1 F, C BIAS = 1 F, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT VOLTAGE RANGE VIN T
J = −40°C to +125°C 1.2 3.6 V
BIAS VOLTAGE RANGE VBIAS T
J = −40°C to +125°C 2.3 5.5 V
OPERATING SUPPLY CURRENT IVIN1 I
OUT = 0 μA 25 μA
I
OUT = 0 μA, TJ = −40°C to +125°C 44 μA
I
OUT = 1 mA 40 μA
I
OUT = 1 mA, TJ = −40°C to +125°C 58 μA
I
OUT = 100 mA 100 μA
I
OUT = 100 mA, TJ = −40°C to +125°C 130 μA
I
OUT = 350 mA 160 μA
I
OUT = 350 mA, TJ = −40°C to +125°C 220 μA
BIAS OPERATING CURRENT IBIAS 16 μA
T
J = −40°C to +125°C 28 μA
SHUTDOWN CURRENT ISD-VIN EN = GND 0.1 μA
EN = GND, TJ = −40°C to +85°C 1.0 μA
EN = GND, TJ = +85°C to +125°C 20 μA
I
SD-VBIAS EN = GND 0.1 μA
EN = GND, TJ = −40°C to +125°C 1.0 μA
FIXED OUTPUT VOLTAGE ACCURACY VOUT I
OUT = 10 mA −1 +1 %
1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V −2 +2 %
1 mA < IOUT < 350 mA, VIN = (VOUT + 0.4 V) to 3.6 V,
TJ = −40°C to +125°C
−3 +3 %
LINE REGULATION ∆VOUT/∆VIN V
IN = (VOUT + 0.4 V) to 3.6 V, TJ = –40°C to +125°C −0.10 +0.10 %/ V
LOAD REGULATION2 ∆VOUT/∆IOUT I
OUT = 10 mA to 350 mA 0.001 %/mA
I
OUT = 10 mA to 350 mA, TJ = −40°C to +125°C 0.005 %/mA
DROPOUT VOLTAGE3 V
DROPOUT I
OUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V 2 mV
IOUT = 10 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
3.5 mV
I
OUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V 17 mV
IOUT = 100 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
28 mV
I
OUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V 70 mV
IOUT = 350 mA, VBIAS = 2.3 V, VOUT = 3 V,
TJ = −40°C to +125°C
100 mV
START-UP TIME4 T
START-UP V
OUT = 1.2 V 200 μs
CURRENT LIMIT THRESHOLD5 I
LIMIT 400 550 1000 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD T
J rising 150 C
Thermal Shutdown Hysteresis TSSD-HYS 15 C
EN INPUT
EN Input Logic High VIH 2.3 V ≤ VBIAS ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.3 V ≤ VBIAS ≤ 5.5 V 0.4 V
EN Input Leakage Current VI-LEAKAGE EN = BIAS or GND 0.1 μA
EN = BIAS or GND, TJ = −40°C to +125°C 1 μA
UNDERVOLTAGE LOCKOUT UVLO
Input Voltage Rising UVLORISE T
J = −40°C to +125°C 2.1 V
Input Voltage Falling UVLOFALL T
J = −40°C to +125°C 1.5 V
Hysteresis UVLOHYS 180 mV
ADP130 Data Sheet
Rev. C | Page 4 of 20
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 0.8 V 29 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 38 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.5 V 43 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 61 μV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 3.0 V 77 μV rms
POWER SUPPLY REJECTION RATIO PSRR Modulated bias, 10 kHz, VOUT = 3.0 V, VIN = 3.6 V,
VBIAS = 5 V
70 dB
Modulated bias, 100 kHz, VOUT = 3.0 V, VIN = 3.6 V,
VBIAS = 5 V
53 dB
Modulated VIN, 10 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V,
VBIAS = 5 V
70 dB
Modulated VIN, 100 kHz, VOUT = 1.2 V, VIN = VOUT + 1 V,
VBIAS = 5 V
54 dB
Modulated VIN, 10 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V,
VBIAS = 5 V
70 dB
Modulated VIN, 100 kHz, VOUT = 0.8 V, VIN = VOUT + 1 V,
VBIAS = 5 V
55 dB
1 IVIN = IGND − IBIAS, where IGND is the current flowing from the GND pin.
2 Based on an endpoint calculation using 1 mA and 350 mA loads.
3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.3 V.
4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 2.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 2.0 V, or 1.8 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 C
MIN T
A = −40°C to +125°C 0.70 1 μF
CAPACITOR ESR RESR T
A = −40°C to +125°C 0.001 1 Ω
1 The minimum input and output capacitance should be >0.70 μF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and
Z5U capacitors are not recommended for use with any LDO.
Data Sheet ADP130
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN to GND −0.3 V to +3.6 V
VBIAS to GND −0.3 V to +6 V
EN to GND −0.3 V to VBIAS
VOUT to GND −0.3 V to VIN
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Operating Junction Temperature 125°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in combi-
nation. The ADP130 may be damaged when junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient temperature
may need to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can exceed
the maximum limit as long as the junction temperature is within
specification limits. The junction temperature (TJ) of the device
is dependent on the ambient temperature (TA), the power
dissipation of the device (PD), and the junction-to-ambient thermal
resistance of the package (θJA). TJ is calculated using the
following formula:
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θJA are based on a four-layer, 4 in × 3 in circuit board.
For details about board construction, refer to JEDEC JESD51-7.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a four-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Package Thermal
Information, states that thermal characterization parameters are
not the same as thermal resistances. ΨJB measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θJB). Therefore, ΨJB thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD), using
the following formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Ψ
JB Unit
5-Lead TSOT 170 43 °C/W
ESD CAUTION
ADP130 Data Sheet
Rev. C | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP130
TOP VIEW
(Not to Scale)
1
VIN
2
GND
3
EN
5
VOUT
4
VBIAS
06963-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN Regulator Input Supply. Bypass VIN to GND with a capacitor of 1 μF or greater.
2 GND Ground.
3 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup,
connect EN to VBIAS
4 VBIAS Bias Input Supply. Connect a capacitor of 1 μF or greater between VBIAS and GND.
5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a capacitor of 1 μF or greater.
Data Sheet ADP130
Rev. C | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
VBIAS = 5 V, VIN = 2.2 V, VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = CBIAS = 1 µF, TA = 25°C, unless otherwise noted.
06963-004
VOUT (V)
JUNCTION TEMPERATURE (°C)
–40 –5 25 85 125
ILOAD = 10mA
ILOAD = 1mA
1.775
1.780
1.785
1.790
1.795
1.800
1.805
ILOAD = 350mA
ILOAD = 100mA
ILOAD = 50mA
ILOAD = 200mA
Figure 4. Output Voltage vs. Junction Temperature
06963-005
V
OUT
(V)
I
LOAD
(mA)
1 10 100 1000
1.795
1.797
1.799
1.801
1.803
1.805
Figure 5. Output Voltage vs. Load Current
06963-006
V
IN
(V)
V
OUT
(V)
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
1.803
1.804
1.805
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 350mA
Figure 6. Output Voltage vs. Input Voltage
–40 –5 25 85 125
06963-007
JUNCTION TEMPERATURE (°C)
I
VIN
CURRENT (µA)
0
200
20
40
60
80
100
120
140
160
180 I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 350mA
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
Figure 7. IVIN Current vs. Junction Temperature
–40 –5 25 85 125
06963-008
JUNCTION TEMPERATURE (°C)
BIAS CURRENT (µA)
0
5
10
15
20
25
30
I
LOAD
= 350mA
I
LOAD
= 200mA
I
LOAD
= 100mA
I
LOAD
= 50mA
I
LOAD
= 10mA
I
LOAD
= 1mA
Figure 8. Bias Current vs. Junction Temperature
06963-009
I
VIN
CURRENT (µA)
I
LOAD
(mA)
1 10 100 1000
0
20
40
60
80
100
120
140
160
180
Figure 9. IVIN Current vs. Load Current
ADP130 Data Sheet
Rev. C | Page 8 of 20
06963-010
BIAS CURRENT (µA)
I
LOAD
(mA)
1 10 100 1000
0
5
10
15
20
25
Figure 10. Bias Current vs. Load Current
0
20
40
60
80
100
120
140
160
180
200
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
I
LOAD
= 350mA
I
LOAD
= 200mA
06963-011
V
IN
(V)
GROUND CURRENT (µA)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
Figure 11. Ground Current vs. Input Voltage
0
5
10
15
20
25
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
06963-012
V
IN
(V)
BIAS CURRENT (µA)
I
LOAD
= 1mA
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 350mA
Figure 12. Bias Current vs. Input Voltage
06963-013
I
LOAD
(mA)
DROPOUT VOLTAGE (mV)
0
10
20
30
40
50
60
10 100 1000
V
OUT
= 3V
T
A
= 25°C
Figure 13. Dropout Voltage vs. Load Current, VOUT = 3 V
06963-014
I
LOAD
(mA)
DROPOUT VOLTAGE (mV)
10 100 1000
0
10
20
30
40
50
60
70
80
T
A
= 25°C
V
OUT
= 3.0V
V
OUT
= 1.8V
Figure 14. Dropout Voltage vs. Output Voltage and Load Current
06963-015
V
IN
(V)
V
OUT
(V)
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 350mA
Figure 15. Output Voltage vs. Input Voltage (in Dropout), VOUT = 3 V
Data Sheet ADP130
Rev. C | Page 9 of 20
06963-016
V
IN
(V)
GROUND CURRENT (µA)
2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20
0
100
200
300
400
500
600
I
LOAD
= 10mA
I
LOAD
= 50mA
I
LOAD
= 100mA
I
LOAD
= 200mA
I
LOAD
= 350mA
Figure 16. Ground Current vs. Input Voltage (in Dropout), VOUT = 3 V
06963-017
V
IN
(V)
BIAS CURRENT (µA)
2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20
13
14
15
16
17
18
I
LOAD
= 100mA
I
LOAD
= 50mA
I
LOAD
= 10mA
I
LOAD
= 350mA
I
LOAD
= 200mA
Figure 17. Bias Current vs. Input Voltage (in Dropout), VOUT = 3 V
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
V
RIPPLE
= 50mV
V
IN
= 3.6V
V
OUT
= 3.0V
C
OUT
= 1µF
V
BIAS
= 5V
06963-018
FREQUENCY (Hz)
PSRR (dB)
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
Figure 18. Power Supply Rejection Ratio vs. Frequency, VIN Input
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
V
RIPPLE
= 50mV
V
IN
= 2.8V
V
OUT
= 1.8V
C
OUT
= 1µF
V
BIAS
= 5V
06963-019
FREQUENCY (Hz)
PSRR (dB)
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
Figure 19. Power Supply Rejection Ratio vs. Frequency, VIN Input
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
V
RIPPLE
= 50mV
V
IN
= 2.2V
V
OUT
= 1.2V
C
OUT
= 1µF
V
BIAS
= 5V
06963-020
FREQUENCY (Hz)
PSRR (dB)
LOAD = 100mA
LOAD = 350mA
LOAD = 100µA
LOAD = 10mA
Figure 20. Power Supply Rejection Ratio vs. Frequency, VIN Input
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
V
RIPPLE
= 50mV
V
IN
= 1.8V
V
OUT
= 0.8V
C
OUT
= 1µF
V
BIAS
= 5V
06963-021
FREQUENCY (Hz)
PSRR (dB)
LOAD = 100µA
LOAD = 10mA
LOAD = 100mA
LOAD = 350mA
Figure 21. Power Supply Rejection Ratio vs. Frequency, VIN Input
ADP130 Data Sheet
Rev. C | Page 10 of 20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10 100 1k 10k 100k 1M 10M
06963-022
FREQUENCY (Hz)
PSRR (dB)
1V HEADROOM
0.5V HEADROOM
V
RIPPLE
= 50mV
V
OUT
= 1.8V
I
OUT
= 100mA
C
OUT
= 1µF
V
BIAS
= 5V
Figure 22. Power Supply Rejection Ratio vs. Headroom, VIN Input
10 100 1k 10k 100k 1M 10M
VRIPPLE = 50mV
VIN = 3.6V
VOUT = 3.0V
COUT = 1µF
VBIAS = 2.3V
0
6963-023
FREQUENCY (Hz)
PSRR (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
Figure 23. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
VRIPPLE = 50mV
VIN = 2.8V
VOUT = 1.8V
COUT = 1µF
VBIAS = 2.3V
0
6963-024
FREQUENCY (Hz)
PSRR (dB)
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
Figure 24. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
VRIPPLE = 50mV
VIN = 2.2V
VOUT = 1.2V
COUT = 1µF
VBIAS = 2.3V
06963-025
FREQUENCY (Hz)
PSRR (dB)
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
Figure 25. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
10 100 1k 10k 100k 1M 10M
VRIPPLE = 50mV
VIN = 1.8V
VOUT = 0.8V
COUT = 1µF
VBIAS = 2.3V
06963-026
FREQUENCY (Hz)
PSRR (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
LOAD = 350mA
LOAD = 100mA
LOAD = 10mA
LOAD = 100µA
Figure 26. Power Supply Rejection Ratio vs. Frequency, VBIAS Input
0.01
0.1
1
10
10 100 1k 10k 100k
06963-027
FREQUENCY (Hz)
NOISE (µV/√Hz)
0.8V
1.5V
3.0V
Figure 27. Noise Spectrum vs. VOUT
Data Sheet ADP130
Rev. C | Page 11 of 20
0
10
20
30
40
50
60
70
80
90
0.01 0.1 1 10 100 1000
06963-028
ILOAD (mA)
NOISE (µV rms)
0.8V
1.2V
1.5V
1.8V
2.5V
3.0V
Figure 28. Output Noise vs. Load Current and Output Voltage
06963-029
CH1 200mA CH2 50mV M40µs A CH1 92mA
2
1
T10.40%
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
I
LOAD
V
OUT
50mV/DIV
Figure 29. Load Transient Response
06963-030
CH1 500mV CH2 2mV M40µs A CH1 3.35V
2
1
1
T10.20%
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
500mV/DIV
V
BIAS
V
IN
= 3.6V
V
OUT
2mV/DIV
Figure 30. VBIAS Line Transient Response, VIN = 3.6 V, IOUT = 350 mA
06963-031
CH1 500mV CH2 5mV M20µs A CH1 3.37V
2
1
T10.20%
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
V
IN
V
OUT
5mV/DIV
Figure 31. VIN Line Transient Response, VBIAS = 5 V, IOUT = 1 mA
06963-032
CH1 500mV CH2 5mV M20µs A CH1 3.27V
2
1
T10.20%
3V TO 3.5V INPUT VOLTAGE STEP
2V/µs
V
IN
V
OUT
5mV/DIV
Figure 32. VIN Line Transient Response, VBIAS = 5 V, IOUT = 350 mA
ADP130 Data Sheet
Rev. C | Page 12 of 20
THEORY OF OPERATION
The ADP130 is a low dropout, linear regulator that uses an
advanced proprietary architecture to achieve low quiescent
current and high efficiency regulation. It also provides high
power supply rejection ratio (PSRR) and excellent line and load
transient response using a small 1 F ceramic output capacitor. The
device operates from a 2.3 V to 5.5 V bias rail and a 1.2 V to 3.6 V
input rail to provide up to 350 mA of output current. Supply
current in shutdown mode is typically less than 1 µA.
Internally, the ADP130 consists of a reference, an error ampli-
fier, a feedback voltage divider, and a pass device. The output
current is delivered via the pass device, which is controlled by
the error amplifier, forming a negative feedback system that
ideally drives the feedback voltage to equal the reference voltage.
If the feedback voltage is lower than the reference voltage, the
negative feedback drives more current, increasing the output
voltage. If the feedback voltage is higher than the reference voltage,
the negative feedback drives less current, decreasing the output
voltage. The VBIAS pin is the positive supply for all circuitry
except the pass device.
The ADP130 has an internal soft start that limits the output
voltage ramp period to approximately 200 µs. All internal devices
are controlled by the enable pin, EN. When EN is high, the
output is on; when EN is low, the output is off.
SHUTDOWN
VIN
GND
EN
VOUT
VBIAS
R1
R2
06963-033
SHORT-CIRCUIT,
UVLO, AND
THERMAL
PROTECT
0.5V
REF
Figure 33. Internal Block Diagram
The ADP130 is available in output voltages ranging from 0.8 V to
3.0 V. The ADP130 uses the EN pin to enable and disable the
VOUT pin under normal operating conditions. When EN is
high, VOUT turns on. When EN is low, VOUT turns off. For auto-
matic startup, EN can be tied to VBIAS.
Data Sheet ADP130
Rev. C | Page 13 of 20
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP130 is designed for operation with small, space-saving
ceramic capacitors, but it functions with most commonly used
capacitors as long as care is taken regarding the effective series
resistance (ESR) value. The ESR of the output capacitor affects
the stability of the LDO control loop. A minimum of 0.70 µF
capacitance with an ESR of 1 Ω or less is recommended to ensure
stability of the ADP130. Transient response to changes in load
current is also affected by output capacitance. Using a larger value
of output capacitance improves the transient response of the
ADP130 to large changes in load current. Figure 34 and Figure 35
show the transient responses for output capacitance values of
1 µF and 10 µF, respectively.
06963-034
CH1 200mA CH2 50mV M400ns A CH1 192mA
2
1
T14%
V
OUT
= 1.8V
C
IN
= C
OUT
= 1µF
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
I
LOAD
V
OUT
50mV/DIV
Figure 34. Output Transient Response, COUT = 1 μF
06963-035
CH1 200mA CH2 50mV M400ns A CH1 160mA
2
1
T13%
V
OUT
= 1.8V
C
IN
= C
OUT
= 10µF
1mA TO 350mA LOAD STEP
2.5A/µs
200mA/DIV
I
LOAD
V
OUT
50mV/DIV
Figure 35. Output Transient Response, COUT = 10 μF
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN to GND reduces the circuit
sensitivity to PCB layout, especially when long input traces or
high source impedance are encountered. If >1 µF of output
capacitance is required, the input capacitor should be increased
to match it.
Bias Capacitor
Connecting a 1 µF capacitor from VBIAS to GND reduces the
circuit sensitivity to PCB layout, especially when long input traces
or high source impedance are encountered.
Input, Bias, and Output Capacitor Properties
Any good quality ceramic capacitor can be used with the ADP130,
as long as it meets the minimum capacitance and maximum ESR
requirements. Ceramic capacitors are manufactured with a variety
of dielectrics, each with different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate to
ensure the minimum capacitance over the necessary temperature
range and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
are not recommended for use with any LDO, due to their poor
temperature and dc bias characteristics.
Figure 36 shows the capacitance vs. voltage bias characteristics
of the 0402 1µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40 to +85°C temperature
range and is not a function of the package or voltage rating.
0
0.2
0.4
0.6
0.8
1.0
1.2
0246810
06963-036
VOLTAGE (V)
CAPACITANCE (µF)
Figure 36. Capacitance vs. Voltage Characteristics
ADP130 Data Sheet
Rev. C | Page 14 of 20
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = COUT × (1 − TEMPCO) × (1 − TOL) (1)
where:
CEFF is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to be
15% for an X5R dielectric. TOL is assumed to be 10%, and COUT
= 0.94 F at 1.8 V, as shown in Figure 36.
Substituting these values in Equation 1 yields the following:
CEFF = 0.94 F × (1 − 0.15) × (1 − 0.1) = 0.719 F
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over tempera-
ture and tolerance at the chosen output voltage.
To guarantee the performance of the ADP130, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT
The ADP130 has an internal undervoltage lockout circuit that
disables all inputs and the output when the input voltage is less
than approximately 2.1 V. This ensures that the ADP130 inputs
and the output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP130 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 37,
when a rising voltage on EN crosses the active threshold, VOUT
turns on. When a falling voltage on EN crosses the inactive
threshold, VOUT turns off.
06963-037
CH1 500mV CH2 500mV M10ms A CH2 640mV
1
T30%
2
V
OUT
= 1.8V
C
IN
= C
OUT
= 1µF
V
OUT
500mV/DIV
EN
500mV/DIV
Figure 37. Typical EN Pin Operation
As shown in Figure 37, the EN pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
EN pin as it passes through the threshold points.
The EN pin active and inactive thresholds are derived from the
VIN voltage. Therefore, these thresholds vary with changing input
voltage. Figure 38 shows typical EN active and inactive thresholds
when the VBIAS voltage varies from 2.3 V to 5.5 V.
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
06963-038
VBIAS (V)
THRESHOLD (V)
EN ACTIVE
EN INACTIVE
Figure 38. Typical EN Pin Thresholds vs. Input
The ADP130 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the 0.8 V option
is approximately 180 µs from the time at which the EN active
threshold is crossed to when the output reaches 90% of its final
value. The start-up time depends somewhat on the output voltage
setting and increases slightly as the output voltage increases.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 100 200 300 400 500 600 700 800 900 1000
06963-039
TIME (µs)
VOLTAGE (V)
VBIAS = 2.3V
VIN = 3.6V
ILOAD = 10mA
ENABLE
3.0V
1.8V
1.2V
0.8V
Figure 39. Typical Start-Up Time for Various Output Voltages
Data Sheet ADP130
Rev. C | Page 15 of 20
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP130 is protected against damage due to excessive power
dissipation by current limit and thermal overload protection
circuits. The ADP130 is designed to current limit when the
output load reaches 550 mA (typical). When the output load
exceeds 550 mA, the output voltage is reduced to maintain
a constant current limit.
Thermal overload protection limits the junction temperature to
a maximum of 150°C typical. Under extreme conditions (that is,
high ambient temperature and power dissipation) when the
junction temperature starts to rise above 150°C, the output is
turned off, reducing output current to zero. When the junction
temperature drops below 135°C, the output is turned on again and
output current is restored to its nominal value.
Consider the case where a hard short from VOUT to GND occurs.
At first, the ADP130 current limits so that only 550 mA is con-
ducted into the short. If self-heating of the junction is great enough
to cause its temperature to rise above 150°C, thermal shutdown
activates, turning off the output and reducing the output current to
zero. As the junction temperature cools and drops below 135°C,
the output turns on and conducts 550 mA into the short, again
causing the junction temperature to rise above 150°C. This
thermal oscillation between 135°C and 150°C causes a current
oscillation between 550 mA and 0 mA that continues as long
as the short remains at the output.
Current limit and thermal overload protections protect the device
against accidental overload conditions. For reliable operation,
device power dissipation must be externally limited so that
junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
To guarantee reliable operation, the junction temperature of the
ADP130 must not exceed 125°C. To ensure that the junction tem-
perature stays below this maximum value, the user needs to be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The value of θJA is dependent on
the package assembly compounds used and the amount of copper
to which the GND pins of the package are soldered on the PCB.
Table 6 shows typical θJA values of the 5-lead TSOT package for
various PCB copper sizes.
Table 6. Typical θJA Values for Specified PCB Copper Sizes
Copper Size (mm2) θJA (°C/W)
01 170
50 152
100 146
300 134
500 131
1 Device soldered to minimum size pin traces.
The junction temperature of the ADP130 can be calculated from
the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND) (3)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can
be ignored. Therefore, the junction temperature equation can
be simplified as follows:
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature, input-
to-output voltage differential, and continuous load current,
a minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 40
through Figure 46 show junction temperature calculations for
different ambient temperatures, load currents, VIN to VOUT
differentials, and areas of PCB copper.
ADP130 Data Sheet
Rev. C | Page 16 of 20
JUNCTION TEMPERATURE CALCULATIONS
140
0
VIN – VOUT (V)
TJ (°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
(ILOAD)
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-040
0.4 0.8 1.2 1.6 2.0 2.4 2.8
Figure 40. 500 mm2 of PCB Copper, TA = 25°C, TSOT
140
0
VIN – VOUT (V)
TJ (°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-041
0.40.81.21.62.02.42.8
(ILOAD)
Figure 41. 100 mm2 of PCB Copper, TA = 25°C, TSOT
140
0
VIN – VOUT (V)
TJ (°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-042
0.4 0.8 1.2 1.6 2.0 2.4 2.8
(ILOAD)
Figure 42. 0 mm2 of PCB Copper, TA = 25°C, TSOT
140
0
VIN – VOUT (V)
TJ (°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-043
0.4 0.8 1.2 1.6 2.0 2.4 2.8
(ILOAD)
Figure 43. 500 mm2 of PCB Copper, TA = 50°C, TSOT
140
0
VIN – VOUT (V)
T
J
(°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-044
0.4 0.8 1.2 1.6 2.0 2.4 2.8
(ILOAD)
Figure 44. 100 mm2 of PCB Copper, TA = 50°C, TSOT
140
0
VIN – VOUT (V)
T
J
(°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX T
J
(DO NOT OPERATE ABOVE THIS POINT)
06963-045
0.4 0.8 1.2 1.6 2.0 2.4 2.8
(ILOAD)
Figure 45. 0 mm2 of PCB Copper, TA = 50°C, TSOT
Data Sheet ADP130
Rev. C | Page 17 of 20
In cases where board temperature is known, use the thermal char-
acterization parameter, ΨJB, to estimate the junction temperature
rise. Maximum junction temperature (TJ) is calculated from the
board temperature (TB) and power dissipation (PD), using the
following formula:
TJ = TB + (PD × ΨJB) (5)
The typical value of ΨJB is 42.8°C/W for the 5-lead TSOT package.
140
0
VIN – VOUT (V)
TJ (°C)
120
100
80
60
40
20
1mA
10mA
50mA
100mA
150mA
250mA
350mA
MAX TJ (DO NOT OPERATE ABOVE THIS POINT)
06963-046
0.4 0.8 1.2 1.6 2.0 2.4 2.8
(ILOAD)
Figure 46. TSOT, TA = 85°C
PCB LAYOUT CONSIDERATIONS
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP130.
However, as shown in Table 6, a point of diminishing return is
eventually reached, beyond which an increase in the copper size
does not yield significant heat dissipation benefits.
The input capacitor should be placed as close as possible to the
VIN and GND pins. The output capacitor should be placed as
close as possible to the VOUT and GND pins. Using 0402 or 0603
size capacitors and resistors achieves the smallest possible foot-
print solution on boards where the area is limited.
06963-047
VBIAS
J1
ANALOG DEVICES
ADP130-xx-EVALZ
VIN VOUT
GND
EN
GND
C1 C2
GND
GND
U1
C3
Figure 47. Example TSOT PCB Layout
ADP130 Data Sheet
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
100708-A
*COMP LI ANT T O JEDEC S TANDARDS MO-193- AB WITH
THE E X CE PTI ON OF PACKAG E HE IGHT AND THICKNESS .
1.60 BSC 2.80 BS C
1.90
BSC
0.95 BSC
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
0.50
0.30
0.10 MAX
*1.00 MAX
*0.90 MAX
0.70 MIN
2.90 BSC
54
123
SEATING
PLANE
Figure 48. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions show in millimeters
ORDERING GUIDE
Model1 Temperature Range
Output
Voltage (V)2 Package Description
Package
Option Branding
ADP130AUJZ-0.8-R7 −40°C to +125°C 0.8 5-Lead TSOT UJ-5 LCH
ADP130AUJZ-1.2-R7 −40°C to +125°C 1.2 5-Lead TSOT UJ-5 LCJ
ADP130AUJZ-1.5-R7 −40°C to +125°C 1.5 5-Lead TSOT UJ-5 LCK
ADP130AUJZ-1.8-R7 −40°C to +125°C 1.8 5-Lead TSOT UJ-5 LCL
ADP130AUJZ-2.5-R7 −40°C to +125°C 2.5 5-Lead TSOT UJ-5 LCM
ADP130-0.8-EVALZ −40°C to +125°C 0.8 Evaluation Board
ADP130-1.2-EVALZ −40°C to +125°C 1.2 Evaluation Board
ADP130-1.5-EVALZ −40°C to +125°C 1.5 Evaluation Board
ADP130-1.8-EVALZ −40°C to +125°C 1.8 Evaluation Board
ADP130-2.5-EVALZ −40°C to +125°C 2.5 Evaluation Board
ADP130UJZ-REDYKIT Evaluation Board Kit
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact your local Analog Devices, Inc., sales or distribution representative.
Data Sheet ADP130
Rev. C | Page 19 of 20
NOTES
ADP130 Data Sheet
Rev. C | Page 20 of 20
NOTES
©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06963-0-6/12(C)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Analog Devices Inc.:
ADP130UJZ-REDYKIT ADP130AUJZ-0.8-R7 ADP130AUJZ-1.8-R7 ADP130-1.2-EVALZ ADP130-0.8-EVALZ
ADP130-2.5-EVALZ ADP130AUJZ-1.5-R7 ADP130-1.8-EVALZ ADP130AUJZ-2.5-R7 ADP130AUJZ-1.2-R7 ADP130-
1.5-EVALZ
