ams Datasheet Page 1
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TSL2541
ALS, Light-to-Digital Sensor
The TSL2541 is a very-high sensitivity light-to-digital converter
that transforms light intensity into a digital signal output
capable of direct I²C interface. The ALS sensor features 2 output
channels, a visible channel and an IR channel. The visible
channel has a photodiode with a UV and IR blocking filter
whereas the IR channel has a photodiode with an IR pass filter.
Each channel has a dedicated data converter producing a 16-bit
output. This architecture allows applications to accurately
measure ambient light which enables devices to calculate
illuminance to control a display backlight.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TSL2541, ALS, Light-to-Digital
Sensor are listed below:
Figure 1:
Added Value of Using TSL2541
Benefits Features
•Single device integrated optical solution
•2.0mm x 2.0mm x 0.5mm
•Power management features
•I²C fast mode interface compatible
•Accurate ambient light sensing
•Photopic ambient light sense (ALS)
•UV / IR blocking filter
•Programmable gain and integration time
•Reduced power consumption •1.8V power supply with 1.8V I²C bus
General Description
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TSL2541 − General Description
Applications
The TSL2541 applications include:
•Ambient light sensing
•Display backlight control
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
Functional Blocks of TSL2541
Wa it Cont rol
I²C Interface
IR Ch
Lower Upper
INT
SCL
SDA
VDD
VSS
ALS Thresholds
VIS ADC
IR ADC
VIS Data
ALS Control
IR Data
Interrupt Out /
Threshol d Status
VIS Ch
PGND
TSL2541
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TSL2541 − Pin Assignment
Figure 3:
Pin Diagram of TSL2541
Figure 4:
Pin Description of TSL2541 (10-Pin QFN)
Pin Number Pin Name Description
1 PGND Power ground
2 INT Interrupt. Open drain output (active low)
3 SCL I²C serial clock input terminal
4 SDA I²C serial data I/O terminal
5 VDD Supply voltage
6 NC No connection
7 NC No connection
8 NC No connection
9 VSS Ground. All voltages are referenced to VSS
10 I/C Internal connection. Leave floating
Pin Assignment
3*1'
,17
6&/
6'$
1&
1&
1&
966
,&
9''
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TSL2541 − Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 5:
Absolute Maximum Ratings
Symbol Parameter Min Max Units Comments
VDD Supply voltage -0.3 2.2 V All voltages are with respect
to GND
VIO Digital I/O terminal voltage -0.3 3.6 V INT, SCL and SDA
Iout Output terminal current -1 20 mA INT and SDA
Tstrg Storage temperature range -40 85 °C
ISCR Input current (latch up immunity)
JEDEC JESD78D ± 100 mA Class II
ESDHBM Electrostatic discharge HBM
JS-001-2014 ± 2000 V
ESDCDM Electrostatic discharge CDM
JEDEC JESD22-C101F ± 500 V
Absolute Maximum Ratings
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TSL2541 − Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
Figure 6:
Recommended Operating Conditions
Note(s):
1. While the device is operational across the temperature range, performance will vary with temperature. Specifications are stated at
25°C unless otherwise noted.
Figure 7:
Operating Characteristics, VDD = 1.8V, TA = 25°C
Note(s):
1. This parameter indicates the supply current during periods of ALS integration. If Wait is enabled (WEN=1), the supply current is
lower during the Wait period.
2. Idle state occurs when PON=1 and all functions are not enabled.
3. Sleep state occurs when PON = 0 and I²C bus is idle. If Sleep state has been entered as the result of operational flow, SAI = 1, PON
will remain high.
4. Digital pins: SDA, SCL, INT, are tolerant to a communication voltage up to 3.0V.
Symbol Parameter Min Typ Max Units
VDD Supply voltage 1.7 1.8 2.0 V
Supply voltage accuracy, VDD total error including transients -3 3 %
TAOperating free-air temperature (1) -30 85 °C
Symbol Parameter Conditions Min Typ Max Units
fOSC Oscillator frequency 8.107 MHz
IDD Supply current
Active ALS State
(PON=AEN=1) (1) 50 90 150
µA
Idle State
(PON=1,AEN=0) (2) 30 60
Sleep State (3) 0.7 5
VOL INT, SDA output low voltage 6mA sink current 0.6 V
ILEAK Leakage current, INT, SCL and
SDA -5 5 µA
VIH SCL, SDA input high voltage (4) 1.26 V
VIL SCL, SDA input low voltage 0.54 V
TActive Time from power-on to ready
to receive I²C commands 1.5 ms
Electrical Characteristics
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TSL2541 − Typical Operating Characteristics
Figure 8:
ALS Operating Characteristics, VDD = 1.8V, TA = 25°C
Note(s):
1. For the Visible Channel, the values in this parameter are achieved by scaling the Visible Channel output (counts) via software by an
adjustment factor stored in the VISADJ Register (Address 0xE6).
Parameter Conditions Min Typ Max Units
Integration time step size 2.68 2.78 2.90 ms
Number of integration
steps 1256steps
Dark ADC count value Ee = 0 W/ cm2; AGAIN = 64x;
ATIME = 100ms (0xDC) 0 1 3 counts
Re
Irradiance responsivity (1)
Settings:
AGAIN = 16x
ATIME = 400ms
Visible Channel
White LED, 2700K 101 119 137
counts/
(W/cm
2
)
IR Channel
λD = 950 nm LED 359
counts/
(W/cm
2
)
Gain scaling, relative to 1x
gain setting
AGAIN = 4x 4
x
AGAIN = 16x 16
AGAIN = 64x 67
AGAIN = 128x 140
ADC noise AGAIN = 16x0.005% full scale
Typical Operating
Characteristics
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TSL2541 − Typical Operating Characteristics
Figure 9:
Spectral Responsivity
Figure 10:
ALS Responsivity vs Angular Displacement
0%
20%
40%
60%
80%
100%
120%
300 400 500 600 700 800 900 1000 1100
Normalized Responsivity
Wavelength (nm)
Spectral Response
Visible
IR
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
-90 -75 -60 -45 -30 -15 0 15 30 45 60 75 90
Normalized Response (%)
Angle of Incident Light (°)
Normalized Angular Response
Warm White LED
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TSL2541 − Detailed Description
Ambient Light Sensing
The ALS reception signal path begins as photodiodes receive
filtered light and ends with the 16-bit results in the VISDATAL/H
and IRDATAL/H registers. The visible channel's photodiode is
filtered with a UV and IR filter to receive only visible light. The
IR channel's photodiode is filtered to receive only IR. Signals
from the photodiodes simultaneously accumulate for a period
of time set by the value in ATIME before the results are available.
Gain is adjustable from 1x to 128x to facilitate operation over a
wide range of lighting conditions. Custom Lux equations can
be created for specific applications and system designs.
I²C Characteristics
The device uses I²C serial communication protocol for
communication. The device supports 7-bit chip addressing and
both standard and fast clock frequency modes with a chip
address of 0x39. Read and Write transactions comply with the
standard set by Philips (now NXP).
Internal to the device, an 8-bit buffer stores the register address
location of the desired byte to read or write. This buffer
auto-increments upon each byte transfer and is retained
between transaction events (i.e. valid even after the master
issues a STOP command and the I²C bus is released).
During consecutive Read transactions, the future/repeated I²C
Read transaction may omit the memory address byte normally
following the chip address byte; the buffer retains the last
register address + 1.
I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESSWRITE,
REGISTER-ADDRESS, DATA BYTE(S), and STOP. Following each
byte (9th clock pulse) the slave places an ACKNOWLEDGE/
NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is
transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE,
REGISTER-ADDRESS, START, CHIP-ADDRESSREAD, DATA BYTE(S),
and STOP. Following all but the final byte the master places an
ACK on the bus (9TH clock pulse). Termination of the Read
transaction is indicated by a NACK being placed on the bus by
the master, followed by STOP.
Alternately, if the previous I²C transaction was a Read, the
internal register address buffer is still valid, allowing the
transaction to proceed without “re”-specifying the register
address. In this case the transaction consists of a START,
CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but
Detailed Description
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TSL2541 − Detailed Description
the final byte the master places an ACK on the bus (9th clock
pulse). Termination of the Read transaction is indicated by a
NACK being placed on the bus by the master, followed by STOP.
The I²C bus protocol was developed by Philips (now NXP). For
a complete description of the I²C protocol, please review the
NXP I²C design specification at:
www.i2c-bus.org/references/
Timing Diagrams
Figure 11:
I²C Timing
Principles of Operation
System State Machine
An internal state machine provides system control of the ALS,
proximity detection, and power management features of the
device. At power up, an internal power-on-reset initializes the
device and puts it in a low power Sleep state. When a write on
I²C bus to the Enable register (0x80) PON bit is set, the device
transitions to the Idle state. If PON is disabled, the device will
return to the Sleep state to save power. Otherwise, the device
will remain in the Idle state until the ALS function is enabled.
Once enabled, the device will execute the ALS and Wait states
in sequence as indicated in Figure 12. Upon completion, the
device will automatically begin a new ALS-Wait cycle as long as
PON and AEN remain enabled. If the ALS function generates an
interrupt and the Sleep-After-Interrupt (SAI) feature is enabled,
the device will transition to the Sleep state and remain in a
low-power mode until an I²C command is received clearing the
interrupts in the STATUS register. See Interrupts for additional
information.
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TSL2541 − Detailed Description
Figure 12:
Detailed State Diagram
Note(s):
1. An I²C write to az-nth-iteration register, except of the value 00h (disable-az), resets az-done independent of actual cntrl-state.
In consequence, a new autozero calibration will be started in advance to the next ALS integration cycle.
aen
Run ALS
Integration
Run Autozero
Calibration
no
Oscillator On
(IDLE)
Oscillator Off
(SLEEP)
pon no
yes
az-done
yes
az-done = 1
wen
aen==1 &&
az-done==0
yes
az-done = 1
yes
no
Run Autozero
Calibration
Run WTIME timer
no
yes
wtime-done = 0
wtime-done = 1
autozero calibration is
executed in parallel to
running WTIME timer
az-done = 0 (reset)
az-done = 0, if az-nth
iterations passed since
last AZ calibration.
(refer to note 1
for exceptions)
no
az-done &
wtime-done
TSL2541 Operational States
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TSL2541 − Register Description
Figure 13:
Register Overview
Note(s):
1. This value is Factory Set (FS) during electrical test of the device.
2. Register Access:
R = Read Only
W = Write Only
R/W = Read or Write
SC = Self Clearing after access
Address Register Name R/W Register Function Reset Value
0x80 ENABLE R/W Enables states and functions 0x00
0x81 ATIME R/W ALS integration time 0x00
0x83 WTIME R/W Wait time 0x00
0x84 AILTL R/W ALS interrupt low threshold low byte 0x00
0x85 AILTH R/W ALS interrupt low threshold high byte 0x00
0x86 AIHTL R/W ALS interrupt high threshold low byte 0x00
0x87 AIHTH R/W ALS interrupt high threshold high byte 0x00
0x8C PERS R/W ALS interrupt persistence filters 0x00
0x8D CFG0 R/W Configuration register zero 0x80
0x90 CFG1 R/W Configuration register one 0x00
0x91 REVID R Revision ID 0x61
0x92 ID R Device ID 0xE4
0x93 STATUS R Device status register 0x00
0x94 VISDATAL R Visible channel data low byte 0x00
0x95 VISDATAH R Visible channel data high byte 0x00
0x96 IRDATAL R IR channel data low byte 0x00
0x97 IRDATAH R IR channel data high byte 0x00
0x9E REVID2 R Auxiliary ID 0x02
0x9F CFG2 R/W Configuration register two 0x04
0xAB CFG3 R/W Configuration register three 0x0C
0xD6 AZ_CONFIG R/W Autozero configuration 0x7F
0xDD INTENAB R/W Interrupt enables 0x00
0xE6 VISADJ R Visible channel adjustment factor FS (1)
Register Description
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TSL2541 − Register Description
Detailed Register Description
Enable Register (Address 0x80)
Figure 14:
Enable Register
Before activating AEN, preset each applicable operating mode
registers and bits.
Addr: 0x80 Enable
Bit Bit Name Default Access Bit Description
7:4 Reserved 0000 RW Reserved.
3 WEN 0 RW This bit activates the wait feature. Active high.
2 Reserved 0 RW Reserved.
1AEN 0 RW
This bit actives the ALS function. Active high.
*Set AEN=1 and PON=1 in the same command to
ensure auto-zero function is run prior to the first
measurement.
0PON 0 RW
This field activates the internal oscillator and ADC
channels. Active high.
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TSL2541 − Register Description
ATIME Register (Address 0x81)
Figure 15:
ATIME Register
The ATIME register controls the integration time of the ALS
ADCs. The timer is implemented with a down counter with 0x00
as the terminal count. The timer is clocked at a 2.8ms nominal
rate. Loading 0x00 will generate a 2.8ms integration time,
loading 0x01 will generate a 5.6ms integration time, and so
forth. The RC oscillator runs at 8MHz nominal rate. This gets
divided by 11 to generate the integration clock of 727kHz. One
count in ATIME (nominal 2.8ms) are 2.81ms. This is 2048
integration clock cycles: 125ns*11*8*256=2.81ms.
Addr: 0x81 ATIME
Bit Bit Name Default Access Bit Description
7:0 ATIME 0x00 RW
ALS value that specifies the integration time in 2.81ms
intervals. 0x00 indicates 2.8ms. The maximum ALS value
depends on the integration time. For every 2.81ms, the
maximum value increases by 1024. This means that to
be able to reach ALS full scale, the integration time has
to be at least 64*2.8ms.
Value Integration
Cycles
Integration
Time
Maximum
ALS Value
0x00 1 2.8ms 1023
0x01 2 5.6ms 2047
…… … …
0x3F 64 180ms 65535
…… … …
0xFF 256 721ms 65535
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TSL2541 − Register Description
WTIME Register (Address 0x83)
Figure 16:
WTIME Register
The wait timer is implemented using a down counter.
Wait time = (value +1) x 2.8ms. If WLONG is enabled then
Wait time = (value +1) x 2.8ms x 12.
AILTL Register (Address 0x84)
Figure 17:
AILTL Register
The Visible (Vis) channel is compared against low-going 16-bit
threshold value set by AILTL and AILTH.
Addr: 0x83 WTIME
Bit Bit Name Default Access Bit Description
7:0 WTIME 0x00 RW
Value that specifies the wait time between ALS cycles in
2.81ms increments.
Value Increments Wait Time
0x00 1 2.8ms (33.8ms)
0x01 2 5.6ms (67.6ms)
………
0x3F 64 180ms (2.16s)
………
0xFF 256 721ms (8.65s)
Addr: 0x84 AILTL
Bit Bit Name Default Access Bit Description
7:0 AILTL 0x00 RW This register sets the low byte of the LOW ALS threshold.
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TSL2541 − Register Description
AILTH Register (Address 0x85)
Figure 18:
AILTH Register
The Visible (Vis) channel is compared against low-going 16-bit
threshold value set by AILTL and AILTH.
The contents of the AILTH and AILTL registers are combined and
treated as a sixteen bit threshold value. If the value generated
by the C channel is below the AILTL/H threshold and the APERS
value is reached, the AINT bit is asserted. If AIEN is set, then the
INT pin will also assert.
When setting the 16-bit ALS threshold AILTL must be written
first, immediately followed by AILTH. Internally, the lower 8-bits
are buffered until the upper 8-bits are written. As the upper
8-bits are written both the high and low bytes are
simultaneously latched as a 16-bit value.
AIHTL Register (Address 0x86)
Figure 19:
AIHTL Register
The Visible (Vis) channel is compared against high-going 16-bit
threshold value set by AIHTL and AIHTH.
The contents of the AIHTH and AIHTL registers are combined
and treated as a sixteen bit threshold value. If the value
generated by the C channel is above the AIHTL/H threshold and
the APERS value is reached, the AINT bit is asserted. If AIEN is
set, then the INT pin will also assert. When setting the 16-bit
ALS threshold AIHTL must be written first, immediately
followed by AIHTH. Internally, the lower 8-bits are buffered until
the upper 8-bits are written. As the upper 8-bits are written both
the high and low bytes are simultaneously latched as a 16-bit
value.
Addr: 0x85 AILTH
Bit Bit Name Default Access Bit Description
7:0 AILTH 0x00 RW This register sets the high byte of the LOW ALS
threshold.
Addr: 0x86 AIHTL
Bit Bit Name Default Access Bit Description
7:0 AIHTL 0x00 RW This register sets the low byte of the HIGH ALS
threshold.
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TSL2541 − Register Description
AIHTH Register (Address 0x87)
Figure 20:
AIHTH Register
The Visible (Vis) channel is compared against high-going 16-bit
threshold value set by AIHTL and AIHTH.
The contents of the AIHTH and AIHTL registers are combined
and treated as a sixteen bit threshold value. If the value
generated by the C channel is above the AIHTL/H threshold and
the APERS value is reached, the AINT bit is asserted. If AIEN is
set, then the INT pin will also assert.
When setting the 16-bit ALS threshold AIHTL must be written
first, immediately follow by AIHTH. Internally, the lower 8-bits
are buffered until the upper 8-bits are written. As the upper
8-bits are written both the high and low bytes are
simultaneously latched as a 16-bit value.
Addr: 0x87 AIHTH
Bit Bit Name Default Access Bit Description
7:0 AIHTH 0x00 RW This register sets the high byte of the HIGH ALS
threshold.
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TSL2541 − Register Description
PERS Register (Address 0x8C)
Figure 21:
PERS Register
The frequency of consecutive visible channel results outside of
threshold limits are counted; this count value is compared
against the APEARS value. If the counter is equal to the APERS
setting an interrupt is asserted. Any time a clear channel result
is inside the threshold values the counter is cleared.
Addr: 0x8C PERS
Bit Bit Name Default Access Bit Description
7:4 Reserved 0000 RW Reserved.
3:0 APERS 0000 RW
This register sets the ALS persistence filter.
0Every ALS cycle
1 Any value outside ALS thresholds
2 2 consecutive ALS values out of range
3 3 consecutive ALS values out of range
4 5 consecutive ALS values out of range
5 10 consecutive ALS values out of range
6 15 consecutive ALS values out of range
7 20 consecutive ALS values out of range
……
13 50 consecutive ALS values out of range
14 55 consecutive ALS values out of range
15 60 consecutive ALS values out of range
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TSL2541 − Register Description
CFG0 Register (Address 0x8D)
Figure 22:
CFG0 Register
The wait timer is implemented using a down counter.
Wait time = (value +1) x 2.8ms. If WLONG is enabled then
Wait time = (value +1) x 2.8ms x 12.
Addr: 0x8D CFG0
Bit Bit Name Default Access Bit Description
7:3 Reserved 10000 RW This field must be set to the default value.
2WLONG 0 RW
When Wait Long is asserted the wait period as set by
WTIME is increased by a factor of 12.
1:0 Reserved 00 RW This field must be set to the default value.
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TSL2541 − Register Description
CFG1 Register (Address 0x90)
Figure 23:
CFG1 Register
REVID Register (Address 0x91)
Figure 24:
REVID Register
Addr: 0x90 CFG1
Bit Bit Name Default Access Bit Description
7:2 Reserved 000000 RW Reserved.
1:0 AGAIN 00 RW
This field sets the gain of the ALS sensor.
Value ALS Gain
01x
14x
216x
364x
Addr: 0x91 REVID
Bit Bit Name Default Access Bit Description
7:3 Reserved 01100 RO Reserved.
2:0 REV_ID 001 RO Device revision number.
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TSL2541 − Register Description
ID Register (Address 0x92)
Figure 25:
ID Register
Status Register (Address 0x93)
Figure 26:
Status Register
All flags in this register can be cleared by setting the bit high.
Alternatively, if the CFG3.int_read_clear bit is set, then simply
reading this register automatically clears all eight flags.
VISDATAL Register (Address 0x94)
Figure 27:
VISDATAL Register
Addr: 0x92 ID
Bit Bit Name Default Access Bit Description
7:2 ID 111001 RO Device type identification.
1:0 Reserved 00 RO Reserved.
Addr: 0x93 Status Register
Bit Bit Name Default Access Bit Description
7 ASAT 0 R, SC The Analog Saturation flag signals that the ALS results
may be unreliable due to saturation of the AFE.
6:5 Reserved 00 R, SC Reserved.
4AINT 0R, SC
The ALS Interrupt flag indicates that ALS results (visible
channel) have exceeded thresholds and persistence
settings.
3CINT 0R, SC
The Calibration Interrupt flag indicates that calibration
has completed.
2:0 Reserved 000 R, SC Reserved.
Addr: 0x94 VISDATAL
Bit Bit Name Default Access Bit Description
7:0 VISDATAL 0x00 RO This register contains the low byte of the 16-bit
visible channel data.
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TSL2541 − Register Description
VISDATAH Register (Address 0x95)
Figure 28:
VISDATAH Register
IRDATAL Register (Address 0x96)
Figure 29:
IRDATAL Register
IRDATAH Register (Address 0x97)
Figure 30:
IRDATAH Register
REVID2 Register (Address 0x9E)
Figure 31:
REVID2 Register
Addr: 0x95 VISDATAH
Bit Bit Name Default Access Bit Description
7:0 VISDATAH 0x00 RO This register contains the high byte of the 16-bit
visible channel data.
Addr: 0x96 IRDATAL
Bit Bit Name Default Access Bit Description
7:0 IRDATAL 0x00 RO This register contains the low byte of the 16-bit
IR channel data.
Addr: 0x97 IRDATAH
Bit Bit Name Default Access Bit Description
7:0 IRDATAH 0x00 RO This register contains the high byte of the 16-bit
IR channel data.
Addr: 0x9E REVID2
Bit Bit Name Default Access Bit Description
7:4 Reserved 0000 RO Reserved.
3:0 REVID2 0010 RO Package identification.
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TSL2541 − Register Description
CFG2 Register (Address 0x9F)
Figure 32:
CFG2 Register
The ALS gain can be adjusted by setting the two AGAIN bits as
well as the AGAINMAX and AGAINL bits which yields an overall
range from ½x to 128x.
Figure 33:
AGAIN Range
Addr: 0x9F CFG2
Bit Bit Name Default Access Bit Description
7:5 Reserved 000 RW Reserved.
4AGAINMAX 0 RW
This bit adjusts the overall ALS gain factor. See
Figure 33 for recommended settings and
corresponding overall ALS gain factor.
3 Reserved 0 RW Reserved.
2AGAINL 1 RW
This bit adjusts the overall ALS gain factor. See
Figure 33 for recommended settings and
corresponding overall ALS gain factor.
1:0 Reserved 00 RW Reserved.
AGAIN[1] AGAIN[0] AGAINMAX AGAINL Overall ALS Gain
00 0 0 ½
00 0 1 1
01 0 1 4
10 0 1 16
11 0 1 64
11 1 1 128
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TSL2541 − Register Description
CFG3 Register (Address 0xAB)
Figure 34:
CFG3 Register
The SAI bit sets the device operational mode following the
completion of an ALS or proximity cycle. If AINT and AIEN are
both set or if PINT and PIEN are both set, causing an interrupt
on the INT pin, and the SAI bit is set, then the oscillator will
deactivate. The Device will appear as if PON = 0, however, PON
will read as 1. The device can only be reactivated (oscillator
enabled) by clearing the interrupts in the STATUS register.
Addr: 0xAB CFG3
Bit Bit Name Default Access Bit Description
7 INT_READ_CLEAR 0 RW
If the Interrupt-Clear-by-Read bit is set, then all flag
bits in the STATUS register will be reset whenever
the STATUS register is read over I²C.
6:5 Reserved 10 RW Reserved.
4SAI 0RW
The Sleep After Interrupt bit is used to place the
device into a low power mode upon an interrupt pin
assertion.
PON SAI INT Oscillator
0XXOFF
10XON
111ON
110OFF
3:0 Reserved 1100 RW Reserved.
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TSL2541 − Register Description
AZ_CONFIG Register (Address 0xD6)
Figure 35:
AZ_CONFIG Register
INTENAB Register (Address 0xDD)
Figure 36:
INTENAB Register
Addr: 0xD6 AZ_CONFIG
Bit Bit Name Default Access Bit Description
7 Reserved 0 RW Reserved.
6:0 AZ_NTH_
ITERATION 1111111 RW
Run autozero automatically before every nth ALS
cycle (00h = never, n = every nth ALS cycle, and
7Fh = only before the first ALS cycle).
Addr: 0xDD INTENAB
Bit Bit Name Default Access Bit Description
7 ASIEN 0 RW ALS Saturation Interrupt Enable.
6:5 Reserved 00 RW Reserved.
4 AIEN 0 RW ALS Interrupt Enable.
3:0 Reserved 0000 RW Reserved.
ams Datasheet Page 25
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Register Description
VISADJ Register (Address 0xE6)
Figure 37:
VISADJ Register
The output of the visible channel should be adjusted via
software based on the value of this register. This register holds
an adjustment factor in which the MSB is a sign bit and the
remaining bits represent the percent change to be made to the
output. A few examples of the output adjustment factor can be
seen in Figure 38.
Figure 38:
Output Adjustment Factor
Addr: 0xE6 VISADJ
Bit Bit Name Default Access Bit Description
7:0 VISADJ FS R This register provides the output scaling factor
for the visible channel.
Register Value Adjustment (%) Adjustment Factor
0001 0100 20 1.20
0000 1000 8 1.08
0000 0011 3 1.03
0000 0000 0 1.00
1000 0000 0 1.00
1000 0011 -3 0.97
1000 1000 -8 0.92
1001 0100 -20 0.80
Page 26 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Application Information
Schematic
Figure 39:
Typical Applications Circuit
Note(s):
1. The value of the I²C pull up resistors RPU should be based on the 1.8V bus voltage, system bus speed and trace capacitance.
2. The bulk capacitor can affect the stability of a regulated supply output and should be chosen with the regulator characteristics in
mind.
3. VSS and PGND should be connected to the same solid ground plane as close to the device as possible.
Application Information
1.8V
RPU
4.7μF
R = 22Ω
RINT = 10kΩ
Bulk System
Capacitance
TSL2541
VDD
VSS
INT
SCL
SDA
PGND
RPU
V
BUS
INT
SDA
SCL
ams Datasheet Page 27
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Package Drawings & Markings
Figure 40:
Package Drawing
Note(s):
1. All linear dimensions are in micrometers. Dimension tolerance is ±20 μm unless otherwise stated.
2. The die is centered vertically within the package within a tolerance of ±75 μm.
3. Package top surface is molded with an electrically nonconductive black plastic compound having an index of refraction of 1.55.
4. Contact finish is Copper Alloy A194 with pre-plated NiPdAu lead finish.
5. This package contains no lead (Pb).
6. This drawing is subject to change without notice.
Package Drawings & Markings
&
/
$/6
&
/
352;
649,6
$&7,9($5($
,5
$&7,9($5($
,5
$&7,9($5($
&
/
&
/
120,1$/
3+272',2'(
$&7,9($5($
&
/
;
3,1
&
/
62/'(5&217$&76
$1'3+272',2'($&7,9(
$5($127(%
&
/
62/'(5&217$&76
;
;
;
Green
RoHS
Page 28 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Package Drawings & Markings
Figure 41:
Recommended PCB Pad Layout
Note(s):
1. All dimensions are in micrometers.
2. Dimension tolerances are 50μm unless otherwise noted.
3. This drawing is subject to change without notice.
;
;
;
;
;
;
;
;
;
3,1
ams Datasheet Page 29
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Tape & Reel Information
Figure 42:
Tape and Reel Information
Note(s):
1. All linear dimensions are in millimeters.
2. For missing tolerances and dimensions, refer to EIA-481.
Tape & Reel Information
±0,05
3,5
±0,1
4
2
±0,05
A-A (6 : 1)
±0,05
2,2Bo =
MAX10
0,23
±0,05
(3.5 : 1)
B-B (6 : 1)
MAX
2,2Ao =
±0,05
10
Ko = 0,8
±0,05
Page
Date Name
Drawn:
Check:
67505426
Brian Lim27/04/09
6:1
1
the registration of a utility model or design.
Under Construction (MAL)
00
ISO 2768-mK
Surface finish: Tolerance: Scale:
PS Conductive 12.00x0.23mm
Material:
Partnumber/Revision
Title:
LO-422 Carrier Tape
Responsible:
Similar:
payment of demages. All rights are reserved in the event of the grant of a patent or
Brian Lim
8
4
±0,1 +
0
0,1
1,5
1,75
±0,1
±0,1
0,5
±0,05
A
A
BB
Page 30 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Soldering & Storage Information
The QFN package has been tested and has demonstrated an
ability to be reflow soldered to a PCB substrate. The solder
reflow profile describes the expected maximum heat exposure
of components during the solder reflow process of product on
a PCB. Temperature is measured on top of component. The
components should be limited to a maximum of three passes
through this solder reflow profile.
Figure 43:
Solder Reflow Profile
Figure 44:
Solder Reflow Profile Graph
Parameter Reference Device
Average temperature gradient in preheating 2.5°C/s
Soak time tSOAK 2 to 3 minutes
Time above 217°C (T1)t
1Max 60s
Time above 230°C (T2)t
2Max 50s
Time above Tpeak - 10°C (T3)t
3Max 10s
Peak temperature in reflow Tpeak 260°C
Temperature gradient in cooling Max - 5°C/s
Soldering & Storage
Information
t3
t2
t1
tsoak
T3
T2
T1
Tpeak
Not to scale — for reference only
Time (sec)
Temperature (5C)
(s)
ams Datasheet Page 31
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Soldering & Storage Information
Storage Information
Moisture Sensitivity Optical characteristics of the device can be
adversely affected during the soldering process by the release
and vaporization of moisture that has been previously
absorbed into the package. To ensure the package contains the
smallest amount of absorbed moisture possible, each device is
baked prior to being dry packed for shipping. Devices are dry
packed in a sealed aluminized envelope called a
moisture-barrier bag with silica gel to protect them from
ambient moisture during shipping, handling, and storage
before use.
Shelf Life
The calculated shelf life of the device in an unopened moisture
barrier bag is 12 months from the date code on the bag when
stored under the following conditions:
•Shelf Life: 12 months
•Ambient Temperature: <40°C
•Relative Humidity: <90%
Rebaking of the devices will be required if the devices exceed
the 12 month shelf life or the Humidity Indicator Card shows
that the devices were exposed to conditions beyond the
allowable moisture region.
Floor Life
The QFN package has been assigned a moisture sensitivity level
of MSL 3. As a result, the floor life of devices removed from the
moisture barrier bag is 168 hours from the time the bag was
opened, provided that the devices are stored under the
following conditions:
•Floor Life: 168 hours
•Ambient Temperature: <30°C
•Relative Humidity: <60%
If the floor life or the temperature/humidity conditions have
been exceeded, the devices must be rebaked prior to solder
reflow or dry packing.
Rebaking Instructions
When the shelf life or floor life limits have been exceeded,
rebake at 50°C for 12 hours.
Page 32 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Ordering & Contact Information
Figure 45:
Ordering Information
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
Ordering Code I²C Bus I²C Address Delivery Form Delivery Quantity
TSL25413 1.8V 39h Tape and Reel 10000 pcs/reel
TSL25413M 1.8V 39h Tape and Reel 1000 pcs/reel
Ordering & Contact Information
ams Datasheet Page 33
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − RoHS Compliant & ams Green Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
RoHS Compliant & ams Green
Statement
Page 34 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
Copyrights & Disclaimer
ams Datasheet Page 35
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Document Status
Document Status Product Status Definition
Product Preview Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Preliminary Datasheet Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Datasheet Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Datasheet (discontinued) Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
Document Status
Page 36 ams Datasheet
Document Feedback [v1-01] 2018-Jan-23
TSL2541 − Revision Information
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Changes from 1-00 (2017-Oct-19) to current revision 1-01 (2018-Jan-23) Page
Updated Figure 8 and added note below 6
Updated Figure 13 and added note below 11
Added VISADJ Register (Address 0xE6) and Figure 38 25
Revision Information
ams Datasheet Page 37
[v1-01] 2018-Jan-23 Document Feedback
TSL2541 − Content Guide
1 General Description
1 Key Benefits & Features
2 Applications
2 Block Diagram
3 Pin Assignment
4Absolute Maximum Ratings
5 Electrical Characteristics
6 Typical Operating Characteristics
8 Detailed Description
8 Ambient Light Sensing
8 I²C Characteristics
8 I²C Write Transaction
8 I²C Read Transaction
9Timing Diagrams
9 Principles of Operation
9 System State Machine
11 Register Description
12 Detailed Register Description
12 Enable Register (Address 0x80)
13 ATIME Register (Address 0x81)
14 WTIME Register (Address 0x83)
14 AILTL Register (Address 0x84)
15 AILTH Register (Address 0x85)
15 AIHTL Register (Address 0x86)
16 AIHTH Register (Address 0x87)
17 PERS Register (Address 0x8C)
18 CFG0 Register (Address 0x8D)
19 CFG1 Register (Address 0x90)
19 REVID Register (Address 0x91)
20 ID Register (Address 0x92)
20 Status Register (Address 0x93)
20 VISDATAL Register (Address 0x94)
21 VISDATAH Register (Address 0x95)
21 IRDATAL Register (Address 0x96)
21 IRDATAH Register (Address 0x97)
21 REVID2 Register (Address 0x9E)
22 CFG2 Register (Address 0x9F)
23 CFG3 Register (Address 0xAB)
24 AZ_CONFIG Register (Address 0xD6)
24 INTENAB Register (Address 0xDD)
25 VISADJ Register (Address 0xE6)
26 Application Information
26 Schematic
27 Package Drawings & Markings
29 Tape & Reel Information
30 Soldering & Storage Information
31 Storage Information
31 Shelf Life
Content Guide
