ST7554
V.90 USB WORLD MODEM CONTROLLER
January 1999
SUMMARY DATA
TQFP48 (7 x 7 x 1.40mm)
(Full Plastic Quad Flat Pack)
ORDER CODE : ST7554TQF7
GENERAL
.USB HOT PLUG & PLAY INTERFACE
.DIRECT INTERFACE TO ST MAFE+DAA
CHIP-SET ST75951/ST952 FOR WORLD-
WIDE DAA DESIGN OR TO STLC7550 FOR
TRADI TION AL DAA DESI GN
.WINDOWS 98 AND NT 5.0 SUP POR T
.TAPI 2.0 COMPLIANT
.SOFTWARE UPGRADABLE
.MINIMUM SYSTEM REQUIREMENTS:
.USB MOTHERBOARD, 166MHz PENTIUM
PROCESSOR WITH MMX TECHNOLOGY,
WINDOWS 98 AND 16MBYTES RAM OR
WINDOWS NT 5.0 AND 32MB YTE S R AM
DEVIC E F EATURE S
.SINGLE 9.216MHz CRYSTAL OSCILLATOR
.INTEGRATED ANALOG AND DIGITAL 3.3V
REGULATORS
.DEDICATED PINS FOR RING, OFF-HOOK,
CLID, LOOP CURRE NT SENS E
.0.5µm CMOS PROCESS
.TQFP48 (7 x 7 mm) PACKAGE
DATA MO DEM / FAX / VOICE
.V.90
.V.34BIS, V.34, V.32BIS, V.32, V.22BIS, V.22,
V.23, V.21
.BELL 103 A ND B ELL 212A
.V.17, V.27TER, V.29, F A X C LASS 1 SUPPOR T
.V.42, V.42BIS, MNP 2, 3, 4, 5
.V.80
.V.8 AND A UT O MODE
.VOICE / FAX / MODEM DISTINCTION
.ADPCM VOICE COMPRESSION/DECOM-
PRESSION
.VOICE DETECTION (SILENCE DETECTION)
OTHER FEATURES
.VIRTUAL UART (460.8Kbps)
.AT HAYES COMMAND COMPATIBLE
.TIME INDEPENDENT ESCAPE SEQUENCE
(TIES) COMMAND
.CALLER ID
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
.DTMF DETE CTION A ND G ENERATION
.WAKE UP ON RING
.WORLD-WIDE PROGRAMMABLE SILICON
DAA SUPPORT FOR ST75951/ST952
MAF E+DAA CHIP-SET
UNIVERSAL SER IA L BUS
.SPECI FICATION 1.0, 12MBps FULL SPEE D
.ON-CHIP USB TRANSCEIVER WITH DIGIT AL PLL
.COMMUNICATION DEVICE CLASS AND
VE NDOR REQUEST S
.BUS OR SELF POWERED APPLICATION
(PIN-PROGRAMMABLE)
.ONNOW POWER MANAGEMENT (D0, D2, D3)
.LOW POWER CONSUMPTION (SUSPEND
MODE D2), WHOLE APPLICATION BELOW
500µA
DESCRIPTION
T he S T7554 is a s in gle ch ip h os t si gna l pr oc es s ing
Modem/fax/voice controller that supports data rates
up t o 56Kbp s. All d ata pump a nd pro tocol f unctio ns
are executed on the host PC’s processor. This
product has been developed in cooperation with
Smart Link Ltd, who ported "USB-Modio", its host
bas ed M odem and s ystem so ftw are in to ST syst em
and hardware platform. The ST7554 directly con-
nec ts to ST h igh per forma nce M odem analog fr ont-
end (MAFE) STLC7550 or to the highly integrated
MAFE+DAA chip-set ST75951/ST952. The ST7554
also features an Universal Serial Bus (USB) inter-
face for direct connection to the host PC for maxi-
mu m flexi bil it y an d r eal pl ug & pla y oper at io n.
1/11
1
2
3
4
5
6
7
8
16
15
14
13
9
10
11
17
18
19
20
21
22
26
25
28
27
30
29
31
32
33
37
39
38
41
40
42
43
44
12
23
24
34
35
36
45
46
47
48
D-
D+
GNDBUS
VREGD
VBUS
VREGA
AGND
PSM
XTALIN
XTALOUT
FLTPLL
RESET
DC
TRxD
DAASEL
RESERVED
DGND
DOUT
DIN
MCLK
FS
HC1
PDOWN
RESERVED
BUZEN
PULSE
DISHS
RFC
LED
CD
RESERVED
RESERVED
CLID
HO
HSDT
RI
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
7554S-01.EPS
PIN CONNECT IONS
ST7554
2/11
PIN LIST
Name Pin Type Description
XTALIN 9 I Crystal Input
XTALOUT 10 O Crystal Output
RESET 12 I Reset Function to initialise the device (active low)
VBUS 5 I Positive Voltage Regulator Input, connected to USB VBUS
GNDBUS 3 I Regulator Ground, connected to USB Ground (0V) (see Note 1)
VREGA 6 I/O Positive Regulated Analog Input/Output Power Supply
VREGD 4 I/O Positive Regulated Digital Input/Output Power Supply
PSM 8 I Power Supply Mode (Bus-powered or Self-powered)
D+ 2 I/O Positive Data Sig nal of Differenti al Data Bus confor ming to USB Standard
Specification 1.0
D- 1 I/O Negative Data Signal of Differential Data Bus conforming to USB Standard
Specification 1.0
TRxD 35 I/O Transmit/Receive Data Led
DC 36 I/O DC mask
BUZEN 37 I/O Buzzer Amplifier Enable/Mute
PULSE 38 I/O Pulse dialing
DISHS 39 I/O Disconnect external phone
RFC 40 I/O Refresh
LED 41 I/O LED control
CD 42 I/O Carrier Detect Led
CLID 43 I/O Caller ID
HO 45 I/O Hook Control
HSDT 46 I/O Current sense
RI 48 I/O Ring Indicator
HC1 27 O Modem Codec Hardware Control mode selection
PDOWN 26 O SSI Powerdown bit output (active low)
MCLK 29 O SSI Master Clock Output
DAASEL 34 I Select Silicon or Discrete DAA Configuration Mode
FS 28 I SSI Frame Synchronisation Input
DOUT 31 O SSI Serial Data Output
DIN 30 I SSI Serial Data Input
FLTPLL 11 OA PLL filter analog output. Must be connected to analog ground AGND with
33pF capacitor
DGND 32 I Digital Ground (0V) (see Note 1)
AGND 7 I Analog Ground (0V) (see Note 1)
RESERVED 13 to 25-33-44 - Not connected
RESERVED 47 - Connect to digital ground DGND
Note 1 : Analog and digital ground pins must be tied together to USB ground GNDBUS.
7554S-01.TBL
ST7554
3/11
PIN DESCRIPTI ON
1 - Power Supply (7 pins)
1.1 - Regulator Input Power Supply (VBUS)
This pin m ust be connected to USB VBUS (+5V).
It supplies the integrated analog USB transceiver.
It is also the positive regulator power supply input
(5V) when ST7554 is in bus-powered mode
(PSM = 1) and it is used to internally generate the
3.3V supply for the digital and analog circuitry.
1.2 - Regulated Analog VDD Supply (VREGA)
This pin is the analog power supply input (PSM = 0)
or analog 3.3V power supply output (PSM = 1).
This pin is the positive analog power supply for the
external Codec and DAA.
It is recommended to add a 1µF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.3 - Regulated VDD Supply (VREGD)
This pin is the digital power supply input (PSM = 0)
or digital 3.3V power supply output (PSM = 1).
This pin is the positive digital power supply for the
external Codec and DAA.
It is recommended to add a 1µF capacitor between
VREGA and GNDA as close as possible to the
IC pins.
1.4 - Power Supply Mod e (PSM)
This pin controls the VREGD and VREGA power
supply mode.
When PSM = 1, the application is bus-powered.
The 3.3V power supply is generated internally from
VBUS. In t his case VREGD and VREGA are out-
puts which can be used to supply 3. 3V to external
devices (see Figure 1).
When PSM = 0, the application is self-powered.
VBUS must be still connected to the VBUS Pin of
the USB connector in order to supply the integrated
USB transceiver. Anyway in this case VRE GD and
VRE GA mus t be fed by a 3.3V externally regulated
digital and analog power supplies (see Figure 2).
1.5 - Ground (DGND, AGND and G NDB US)
DGND, AGND and GNDBUS are the digital, analog
and USB ground return pins respectively.
They should be connected together outside the
chip to the GND pin of the USB plug.
8PSM
5VBUS
3GNDBUS
4VREGD
32 DGND
6VREGA
7AGND
ST7554
from USB
to other
digital ICs
to other
analog ICs
7554S-02.EPS
Figure 1 : ST7554 in Bus-Powered mode
(PSM = 1)
8PSM
5VBUS
3GNDBUS
4VREGD
32 DGND
6VREGA
7AGND
ST7554
from USB
from 3.3V
externally
regulated
supplies
7554S-03.EPS
Figure 2 : ST7554 in Self Powered mode
(PSM = 0)
2 - U SB Interface (D+ , D -)
These pins are the positive and negative USB
differential data lines. They shall be both connected
to the USB plug or USB protection circuit via 27Ω
series resistors for line impedance matching.
ST7554
4/11
3 - Reset, Powerdown (RESET, PDOWN)
RESET Pin initialises the internal counters and
control registers t o their default value. A minimum
low pulse of 1ms is required to reset th e chip.
In a typical application RESET is connected to
VBUS through a R, C network. This ensures t hat
the chip is reset at each connection / disconnection
to the USB bus (see Figure 3).
PDOW N Pin shall be connec ted to the powerdown
inputs of the external codec used on the SSI.
When ST7554 is in Suspend mode, PDOWN is
forced low so that the external codec is in
powerdown.
PIN DESCRIPTI ON (continued)
12
RESET
R
220k
W
C
10nF
VBUS
7554S-04.EPS
Figure 3 : RC network for RESET
910
R
1.8k
W
C
18pF
C
18pF
AGND AGND
XTAL
OUT
XTAL
IN
7554S-05.EPS
Figure 4 : Application schematic for the
9.216MHz external crystal
4 - Serial Synchronous Interface
ST7554 has a Serial Syncronous Interface (SSI)
dedicated to the connection of the STLC7550 or
ST75951, ST high performance Modem Analog
Front-End (MAFE).
4.1 - Data (DIN, DOUT)
Digital data word input/output of SSI, to be con-
nected to the data word pins of STLC7550 or
ST75951.
4.2 - Master Clock (MCLK)
This pin is the master clock output.
4.3 - Frame Synchronization (FS)
The frame synchronization is used to synchronize data
trans fer betw een ST75 54 and the ext ernal Co dec.
4.4 - Hardware Control (HC1)
HC1 must be connected to the corresponding pin of
STLC7550 or ST75951, while their HC0 Pin shall be
tied to the 3.3V VREGD digital supply. This pin
selects data or control modes for the Modem Codec.
4.5 - DAA Selection (DAASEL)
Connect to VREGD when using silicon DAA chipset
based on ST75951 + ST952. Connect to DGND
when using STLC7550 with discrete interface.
5 - DAA Con trol Pins ( IMP, DC, BUZE N,
PULSE, DISHS, RFC, LED, CLID, HO, HSDT, RI)
These pins control the World Wide software
prog rammable DA A thr ough ST759 51/ ST952.
6 - C rystal (XTALIN, XTALOUT)
These pins must be tied to the 9.216MHz external
crystal.
It is recomme nded to use a ±50ppm fundamental
parallel resonator crystal. It is recommended to
insert a 1.8kΩ resis tor between XT A LOUT and the
crystal to limit its energy to 100µW for a 20Ω
resonator (see Figure 4).
For a SMD crystal the load capacitor is typically
CLOAD = 12pF and this leads to an ideal value of
C = 24pF for the capacitors between the crystal
and analog ground (AGND). Anyway, in practice
these capacitors shall be reduced down to
C = 18pF each by considering parasitic capacitors
on PCB and package (see Figure 4).
Afte r a reset or when leavin g the s uspend sta te,
the 9.216MHz is asserted inside ST7554 only
3.5ms late r in or der t o wait for it to be sta ble.
7 - PLL Output Filter (FLTPLL)
This pin must be connected to the analog ground
(AGND) through a 33pF capacitor.
8 - R eserved Pins (18 pins)
These pins must be left not connected except
Pin 47 which should be connected to the digital
ground DGND.
ST7554
5/11
ELECTRICAL SPEC I F IC ATIONS
Unless otherwise stated, electrical character istics are specified over the operating range.
Typical values are given for V BUS = +5V, VREGA = 3.3V, VREGD = 3.3V, Tamb = 25°C.
Absolute Maximum Rating (AG ND = DGND = USB GND = 0V, all voltages with respect to 0V)
Symbol Parameter Value Unit
DVDD Digital Power Supply -0.3, 6.0 V
IIInput Current per Pin -10, +10 mA
IOOutput Current per Pin -20, +20 mA
VIA Analog Input Voltage -0.3, AVDD + 0.3 V
VID Digital Input Voltage -0.3, DVDD + 0.3 V
Toper Operating Temperature 0, +70 °C
Tstg Storage Temperature -55, +150 °C
Ptot Maximum Power Dissipation 200 mW
Warning : Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranted at these extremes.
Nom inal DC Characteristics (Tamb = 0 to 70°C unless otherwise specified)
Symbol Parameter Min. Typ. Max. Unit
POWER SUPPLY AND COMMON MODE VOLTAGE
VBUS Supply Voltage 4 5 5.25 V
IVBUS Supply Current TBD mA
IVBUSS Supply Current in Suspend Mode (PSM = 1) TBD µA
VREGA Analog regulated Output Power Supply (PSM =1)
Analog regulated Input Power Supply (PSM =0) 3.4-10%
3.3-10% 3.4
3.3 3.4+10%
3.3+10% V
V
VREGD Digital regulated Output Power Supply (PSM =1)
Digital regulated Input Power Supply (PSM =0) 3.4-10%
3.3-10% 3.4
3.3 3.4+10%
3.3+10% V
V
IVREGA Analog regulated Output Current (PSM =1)
Analog regulated Input Current (PSM =0) TBD 40 mA
mA
IVREGD Digital regulated Output Current (PSM =1)
Digital regulated Input Current (PSM =0) 20
20 mA
mA
PDLP Low Power Mode (Suspend mode D2, wake-up on ring enabled) TBD mW
PDOperating Power (SSI in power-down) TBD mW
PDOperating Power (D0 power state) TBD mW
DIGITAL INTERFACE (except XTALIN, XTALOUT, PSM and RESET) (these inputs have hysteresis)
VIH
VIL High Level Input Voltage
Low Level Input Voltage 0.8 x VREGD 0.2 x VREGD V
V
VOH
VOL High Level Output Voltage
Low Level Output Voltage 0.85 x VREGD 0.4 V
V
ILEAK Input Leakage Current ± 1 µA
IOL
IOH High Level Output Current (0 < VOL < VOLMax.)
Low Level Output Current (VOHMin. < VOH < VREGD)-2 2mA
mA
VHYST Schmitt Trigger Hysteresis 0.8 V
CIN Input Capacitance 3 pF
PSM, RESET (these inputs have hysteresis)
VIH
VIL High Level Input Voltage
Low Level Input Voltage 0.7 x VBUS 0.3 x VBUS V
V
ILEAK Input Leakage Current ± 1 µA
VHYST Schmitt Trigger Hysteresis 1 1.3 V
CRYSTAL OSCILLATOR (XTALIN, XTALOUT)
VIH
VIL High Level Input Voltage
Low Level Input Voltage 0.8 x VREGA
0.2 x VREGA V
V
IIH
IIL High Level Input Current
Low Level Input Current -20 20 µA
µA
ST7554
6/11
UNIVERSAL SERIAL BUS INTERFACE
(see Chapter 7 of USB rev 1.0 for complete Elec trical Specification)
Nom inal DC Characteristics (D+ , D -)
Symbol Parameter Min. Typ. Max. Unit
VDI Differential Input Sensitivity [(D+) - (D-)] 0.2 V
VCM Differential Common Mode Range 0.8 2.5 V
VSE Single Ended Receiver Threshold 0.8 2 V
VOH
VOL High Level Output Static Voltage (RL of 15kΩ to GND)
Low Level Output Static Voltage (RL of 1.5kΩ to 3.6V) 2.8 3.6
0.3 V
V
ILO Hi-Z State Data Line Leakage Current (0V < VIN < 3.3V) ±10 µA
CIN Transceiver Capacitance (Pin to GND) 20 pF
RD (2) Driver Output Resistance (steady state drive) TBD TBD Ω
Note 2 : Excludes external resistor. In order to comply with USB Specifications 1.0, external series resistors of 27Ω ±1% each on D+ and D-
are recommended
AC Characteristics (D+, D-) (see Figure 5 for tes t scheme)
Symbol Parameter Min. Typ. Max. Unit
tDR Average bit rate (12 M/s ± 0.05%) 11.97 12.03 Mbps
tRRise Time between 10% and 90% (see Figure 6) 4 20 ns
tFFall Time 10% and 90% (see Figure 6) 4 20 ns
VCRS Output Signal Crossover Voltage 1.3 2 V
1
2
15k
W
50pF 15k
W
50pF
Test
1.5k
W
V
REGD
27
W
Test
D+
D- 27
W
7554S-06.EPS
Figure 5 : Test Scheme for D+/D-
t
R
t
F
90%
10%
90%
10%
7554S-07.EPS
Figure 6 : Rise and Fall Time M easures
ST7554
7/11
ST75951 ST952ST7554 POTS
USB
7554S-08.EPS
Figure 7 : ST7554 Typical Application Diagram with ST75951/ST952
TYPICAL APPLICATIONS
STLC7550 DAAST7554 POTS
USB
7554S-09.EPS
Figure 8 : ST7554 Typical Application Diagram with STLC7550
ST7554
8/11
23
C3
R2 Q1
B1
R4
C5
8
LINI
LIM1
24
GAIN
R5
T1
R0
R1
Line
Plug
Q2
R3
C4
11
OHC
10
COM
Q3
17
TER1
9
IDC
16
TER2
Q4
3
RIN
R9
Q5
20
LINE
22
IDI
R10
C9
R11
D1
D2
R12 R7
R6
21
IDG
19
VDR
15
VDREF
14
I
REF
18
SET
25
LCOM
32
LCOM
6
TOFF
C6 C7 R8 C8
IC3
ST952
26
27
AOUT
AIN
D5
D6
30
31
D1
D2
D3
D4
1
2
4
5
35
34
D1
D2
31
30
D3
D4
27
26
D5
D6
U1
U2
U3
C10
IC2
ST75951
28
23
AGND1
38
AGND2
22
V
REFN
32
V
CMS
39
V
CM
29
V
CMP
G1
21
V
REFP
40
AV
DD
6
DGND
5
DV
DD
41
45
AUXIN
TSTD1
33
TSTA2
TSTA1
15
18
19
20
RING
GPIO2
GPIO1
47
46
DIN
DOUT
GPIO0
17
GPIO3
2
SCLK
7
XTALOUT
14
M/S
43
RESET
10
HC0
42
HM
8
XTALIN
3
FS
11
PWRDWN
9
HC1
16
GPI
444
MCM
TS
C24
C25 DV
DD
AGND
C22
C16
C17 C23
C18
C19
C20
C21
G2
L1
L2
R15
DV
DD
C13
29
MCLK
28
FS
26
PDOWN
27
HC1
34
DAASEL
17 31 30 43 45 48
DOUT
DIN
CLID
HO
RI
C12
9
XTALIN
10
XTALOUT
K1
R16
C11
41
LED
LED
7
AGND
10
FLTPLL
32
3
2
1
5
84126
RESET
V
REGA
V
REGD
PSM
DGND
GNDBUS
D+
D-
VBUS
3
2
1
4
5
6
7
8
USB6
U5
1
2
3
4
USB
Plug
U4
R19
R20
C29
L3
L4
GND
R18
R17
DV
DD
C15
C30C31
D4
C14
AV
DD
C26 C27
ST7554
IC1 C28
18 47
RESERVED
RESERVED
RESERVED
Note : This is an example schematic.
Details may change without notice.
Refer to ST USB Dongle Modem documentation.
R14
R19
7554S-10.EPS
Figure 9 : ST7554 Schematic Diagram with ST75951/ST952
TYPICAL APPLICATIONS (continued)
ST7554
9/11
TYPICAL APPLICATIONS (continued)
Note : This is an example schematic.
Details may change without notice.
Refer to ST USB Dongle Modem documentation.
IC2
STLC7550
21
AGND1
33
AGND2
20
V
REFN
27 32
V
CM
19
V
REFP
31
AV
DD
6
DGND
5
DV
DD
3
SCLK
8
XTALOUT
9
XTALIN
4
FS
17
PWRDWN
15
HC1
742
MCM
TS
C19
C18 DV
DD
AGND
C9
C17
C15 C8
C16
C14
C11
C10
29
MCLK
28
FS
26
PDOWN
27
HC1
34
DAASEL
17 31 30
DOUT
DIN
C21
9
XTALIN
10
XTALOUT
K1
R9
C22
41
LED
D1
7
AGND
10
FLTPLL
32
3
2
1
5
84126
RESET
V
REGA
V
REGD
PSM
DGND
GNDBUS
D+
D-
VBUS
3
2
1
4
5
6
7
8
USB6
U1
1
2
3
4
USB
Plug
U4
R6
R7
C12
L2
L3
GND
R2
R3
DV
DD
C7
C23C25 C24
AV
DD
C6 C5
ST7554
IC1 C13
18 47
RESERVED
RESERVED
RESERVED
R10
48
45
RI
HO
R8
43
TSTD1
44 45
DIN
DOUT
18
16
R5
41
M/S
HC0
RESET C20
DV
DD
28
AUXIN-
AUXIN+
L4 L1
C2 C3
G1 G2
40
30
39
29
IN+
OUT+
OUT-
IN-
9
10 8
U3
R26
R4
C4
AGND
R33
U3 3
2
1R29
C37
C38
R31
U3 6
5
7
V
CM
C39
R17
R13
C35
R15 C30
12
13 14
U3
R1
R21
R23
R28
R16
C1
AGND
C32
Q1
Q2
R25
R30
R22D3
C36
B1
C31
T1
C28
T2
Line
Plug
L5
L6
R20
R12
6
5
8
D5
R14
C27
D2 D4
7
3
4
1
2
DV
DD
R32
R11
R19
R27
R18
R24
7554S-11.EPS
Figure 10 : ST7554 Schematic Diagram with STLC7550 (in TQFP48 package)
ST7554
10/11
48 37
D3
e
13 24
1
12 25
36
c
A1 A2
A
D1
D
E3
E1
E
L
K
L1
0,25 mm
.010 inch
GAGE PLANE
0,10 mm
.004 inch
SEATING PLANE
B
PM-5B.EPS
PACKAGE MECHANICAL DATA
48 PINS - THIN PLAS TIC QUAD FLAT PACK (TQFP)
Dimensions Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.216
e 0.50 0.0197
E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.216
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K0
o
(Min.), 7o (Max.)
5B.TBL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
conseque nces of use of such information nor for any infri nge ment of patents or other rights of third parties which m ay resul t from
its use. No lic ence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or s ystems
without expr ess wri tte n approv al of STMi croe lect roni cs.
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ST7554
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