Philips Semiconductors Military FAST Products 4-Bit binary counters FEATURES @ Synchronous counting and ioading Two Count Enable inputs for n-bit cascading Positive edge-triggered clock Asynchronous reset (54F 161A) @ Synchronous reset (54F 163A) High-speed synchronous expansion Typical count rate of 120MHz DESCRIPTION Synchronous 4-bit (54F 161A, 54F 163A) counters feature an internal carry look- ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The Clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the DO - D3 inputs to be loaded into the counter on the positive-going edge of the clock (providing that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs. A Low level at the Master Reset (MR) input sets all four outputs of the flip-flaps (Q0 - Q3) in 54F161A to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 54F 163A, the clear function is synchronous. A Low level at the Reset (SR) input sets ali four outputs of the flip-flops (Q0 - Q3) to Low levels after the next positive-going transition on the Clock (CP) input (providing that the setup and hold requirements for MR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. This synchronous reset feature enables the designer to INPUT AND OUTPUT LOADING AND FAN-OUT TABLE Product specification ee 54F161A, 54F163A modify the maximum count with only one external NAND gate (see Figure A). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable inputs (CEP and CET) must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure B). For conventional operation of 54F 161A and 54F 163A, the following transitions should be avoided: 1. High-to-Low transition on the CEP or CET input if Clock is Low. 2. Low-to-High transition on the Parallel Enable input when CP is Low, if the count enables and MR are High at or before the transition. For 54F 1634 there is an additional transition to be avoided: 3. Low-to-high transition on the MR input when Clock is Low, if the Enable and PE inputs are High at or before the transition. The TC output is subject to decoding spikes due to internal race conditions. Therefore. itis not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. ORDERING INFORMATION DESCRIPTION ORDER CODE | pfaicnaren 16-Pin Ceramic DIP car leanben | GDIPI-T16 16-Pin Ceramic FlatPack | P4r\Paqinca | GDFP2-FI6 20-Pin Ceramic LLCC car TegABon | CQCC2-N20 *MIL-STD 1835 or Appendix A of 1995 Military Data Handbook PINS DESCRIPTION HonLow iaHLow! CEP Count enable parallel input 1.0/1.0 20pA/0.6mA CET Count enable trickle input 1.0/2.0 20pA/1.2mA cP Clock pulse input (active rising edge) 1.0/1.0 20nA/0.6MA MR Asynchronous master reset input (active Low) 1.0/1.0 20nA/0.6mMA SR Synchronous reset input (active Low) 1.0/2.0 20nA/1.2mA DO - D3 Parallel data inputs 4.0/1.0 20nA/0.6mMA PE Parallel enable input (active Low) 1.0/2.0 20pA/1.2MA Q0 - Q3 Flip-flop outputs 50/33 1.0mA/20mMA tc Terminal count output 50/33 1.O0mA/20mA NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20uA in the High state and 0.6mA in the Low state. January 17, 1991 756 853-0603 01465Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A PIN CONFIGURATION LOGIC SYMBOL Voc SR Cy Yoc Te cp [2] Te ao Do [3] ao ar 01 [4] a1 a2 b2 [5] a2 aa Ds a3 ceT cEP CET rE ano [8] PE 9 3 4 5 6 9 3 4 5 6 t St} pd) , | | | | PE DO Dt ob2 oa PE 00 DI D2 D3 7_| CEP 7_ CEP 54F161A 54F163A 1o cer tc | 16 10 CET to L16 2; cP 2{ cp 1q MR ao at a2. aa id SR @o ai a2. a3 4 13012~C**A 4 61300120OH CEP GND NC PE CET January 17, 1991 757Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A STATE DIAGRAM Logic Equations: Count Enable = CEP.CET-PE TC = Q0.Q1.02.03-CET LOGIC DIAGRAM bo o1 D2 D3 "FIGIA CEP CET Tc ce DETAIL A DETAIL A DETAIL A MR (161A) SA ('161A) Qo ai a2 Q3 NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays MODE SELECT FUNCTION TABLE, 54F161A OPERATING MODE INPUTS OUTPUTS MR cP CEP CET PE Dn Qn Tc Reset (clear) L xX x x x xX L L Parallel load H T x X I I L L H T X x I h H (1) Count H T h h h x count (1) Hold (do nothing) H Xx | X h x qn (1) H xX xX 12) h x Qn L January 17, 1994 758Phitips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A MODE SELECT FUNCTION TABLE, 54F163A OPERATING MODE INPUTS OUTPUTS SR CP CEP CET PE Dn Qh Tc Reset (clear) | T x x x x L L Parallel load h t xX x t L L h tT x x | h H (2) Count h T h h h x count (2) Hald (do nathing) h xX l x h x Gn (2) h x x \ h x dn L High voltage level steady state Low voltage level steady state High voltage level one setup time prior to the Low-to-High clock transition Low voltage level one setup time prior to Low-to-High clock transition Don't care Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Low-to-High clock transition NOTES: (1) The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 54F161A) (2) The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 54F 163A) Vuovnnayn 3axK- IFT ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT Vec Supply voltage range -0.5 to +7.0 Vv Vi Input voltage range -0.5 to +7.0 Vv I Input current range -30 to +5 mA Vo Voltage applied to output in High output state range -0.5 to +#Voc v lo Current applied to output in Low output state 40 mA Tstq Storage temperature range -65 to +150 C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX Voc Supply voltage 45 5.0 5.5 Vin High-level input voltage 2.0 Vv Vit Low-level input voltage 0.8 lik Input clamp current -18 mA low High-level output current -1.0 mA lou Low-level output current 20.0 ma Tamb Operating free-air temperature range -55 +125 C January 17, 1991 759Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS! LIMITS UNIT MIN TYP2 MAX ah Veco = MIN, Vit = MAX, Vou High-level output voltage log = MAX, Viq = MIN 25 v | Voc = MIN, Vi, = MAX, Voi Low-ievel output voltage lou = MAX, Vigy = MIN 0.35 0.50 Vv Vik Input clamp voltage Vec = MIN, | = Ik -0.73 1.2 Vv hee Input current at maximum input voltage Voc = MAX, V = 7.0V 100 pA Wie High-level input CET, SR, PE Voc = MAX, V| = 2.7V 40 pA current Other inputs 20 pA Ue Low-level input CET, SR, PE Voc = MAX, V = 0.5V 1.2 mA current Other inputs -0.6 mA los Short-circuit output current? Voc = MAX -60 -150 mA lec Supply current (total) locH Voc = MAX 55 mA lock 55 mA AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT Tamb = +25C Tamb = -55C to +125C Vec = +5.0V Veco = +5.0V + 10% C, = 50pF, R, = 5000 C, = S0pF, R, = 5002 MIN TYP MAX MIN MAX fax Maximum clock frequency Waveform 1 100 120 759 MHz tpLH Propagation delay Waveform 1 2.0 4.0 6.5 2.0 7.5 ns toa CP toQ, PE = High 3.5 7.0 10.0 3.5 11.5 ns teLH Propagation delay Waveform 1 2.0 4.0 7.0 2.0 8.5 ns tPpHL CP to Q, PE = Low 3.0 6.0 8.5 3.0 10.0 ns tpLH Propagation delay 4.0 10.0 14.0 4.0 16.5 ns teu CP to TC Waveform 1 35 14.0 | 16.0 3.5 18.5 ns teLy Propagation delay 2.0 45 7.5 2.0 9.0 ns tpHL CET to TC Waveform 2 2.0 45 75 2.0 3.0 ns Propagation delay tpHL MB to Q, (54F161A) Waveform 3 5.5 9.0 12.0 5.5 14.0 ns Propagation delay TPHL MR to TC (54F 161A) Waveform 3 45 11.5 45 14.0 ns January 17, 1991 760Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A AC SETUP REQUIREMENTS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT Tamb = +25C Tamb = -85C to +125C Vec = +5.0V Voc = +5.0V + 10% C, = 50pF, Ry, = 50002 C, = 50pF, R, = 50002 MIN TYP MAX MIN MAX ts(H) Setup time, High or Low .0 5.5 ns tl) Dp to CP Waveform 5 5.9 55 ns th(H) Hold time, High or Low 2.0 25 ns th(L) Dp to CP Waveform 5 2.0 25 ng ts(H) Setup time, High or Low 11.0 13.5 ns LU) PE or SR to CP Waveform 5 or 6 85 105 ns t,(H) Hold time, High or Low 2.0 2.0 ns in(L) PE or SR to CP Waveform 5 or 6 0 0 ns te(H) Setup time, High or Low 11.0 13.0 ns te(L) CEP or CET to CP Waveform 4 5.0 65 ng ty(H) Hold time, High or Low 2.0 2.0 ns til) GEP or CET to CP Waveform 4 a Q ns tw(H) Clock pulse width (load), 6.5 9.0 ns ty(L} High or Low Waveform 1 3.5 4.0 ns tw(H) Clock pulse width (count), 6.5 9.0 ns tel) High or Low Waveform 1 35 40 ns MR pulse width Low tw(L} (54F 161A) Waveform 3 5.0 9.5 ns Recovery time, MR to CP tec (64F161A) Waveform 3 6.0 6.0 ns NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type and function table for operating mode. 2. All typical values are at Voc = 5V. Ta = 25C. 3. Not more than one output should be shorted at a time. For testing log, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, log tests should be performed last. . loc is measured with the outputs left open and by setting the outputs Low for tcc_ and again by setting the outputs high for Icon. . These parameters are guaranteed, but not tested. . Pulse width tests are guaranteed as specified, but tested at 7.0ns due to tester limitations. ans January 17, 1991 761Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F 161A, 54F163A AC WAVEFORMS tM AX cP TJ vu f VM \ two *) 'PLH 'PHL VOH Qn YM YM Vou Tw VM YM Tc Waveform 1. Clock to Output Delays, Maximum Waveform 2. Propagation Delays CET Input to TC Output Clock Frequency, and Clock Pulse Width CED AND CET cP You VM Vou Waveform 3. Master Reset Pulse Width, Master Waveform 4. CEP and CET Setup and Hold Times Reset to Output Delay and Master Reset to Clock Recovery Time (54F161A) DATA Dn STABLE Ym YM t(H) Waveform 5. Parallel Data and Parallel Enable Setup and Waveform 6. Synchronous Reset Setup, Pulse Width Hold Times and Hold Times (54F163A) NOTE: Far ail waveforms Vag = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance January 17, 1991 762Philips Semiconductors Military FAST Products Product specification 4-Bit binary counters 54F161A, 54F163A APPLICATION DIAGRAM Vee PE DO DI O2 D3 CEP CET 54F163A Te cLock 4 cp MR Qo ai a2. (3 TERMINAL COUNT = 6 a. A Maximum Count Modifying Scheme Terminal Count = 6 pitit; {ttt | [| | Li | { i | || H = ENABLE COUNT Ls DISABLE COUNT PE DO D1 D2 03 PE DO DI D2 D3 PE DO D1 D2 D3 PE DO D1 D2 03 PE DO D1 D2 D3 cep +] CEP CEP CEP L_| CEP H = ENABLE COUNT L= DISABLE COUNT] CET To }*4 cET Te > CET Te }J CET Tc CET Te P cP | cP { cP | cP | cp MR ao a1 @2 a3 [!|~4 MR ao a1 a2 aa -{MR ag at az a3 -1 MR ao Qi G2 3 MR ao ai a2 a3 i tt | IT 7 | TTT TET TT ed b. Synchronous Multistage Counting Scheme TEST CIRCUIT AND WAVEFORM FunctionTable. 2.7 wo zw > Vx Vee NEGATIVE vi v 1, ? PULSE M M ov VIN YouT | ' PULSE D.U.T. THL(th 'TLH(tr) ~ GENERATOR 7 Ry | T cL? AL 7 TLH(tr) anv i i | POSITIVE 0.3V _ tw ov Test Circuit for Totem-Pole Outputs VM = 1.5V Input Pulse Definition DEFINITIONS: RL = Load Resistor; see AC Characteristics for value. INPUT PULSE CHARACTERISTICS C, = Load capacitance includes jig and probe capacitance; see Family Rep. Rate | Pulse Width tun true AC Characteristics for value. Ry = Termination resistance should be equal to Zour of pulse S4F IMHz 500ns <2.5ns <2.5ns generators. Vy = Unclocked pins must be held at: <0.8V; >2.7V or open per January 17, 1991 763