XQ17V16VQ44N - Xilinx, Inc.

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Product Specification 1-800-255-7778

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Features

• 16Mbit storage capacity

• Guaranteed operation over full military temperature

range: –55°C to +125°C

• One-time programmable (OTP) read-only memory

designed to store configuration bitstreams of Xilinx

FPGA devices

• Dual configuration modes

- Serial configuration (up to 33 Mb/s)

- Parallel (up to 264 Mb/s at 33 MHz)

• Simple interface to Xilinx QPro FPGAs

• Cascadable for storing longer or multiple bitstreams

• Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

• Low-power CMOS Floating Gate process

• 3.3V supply voltage

• Available in compact plastic VQ44 and ceramic CC44

packages

• Programming support by leading programmer

manufacturers.

• Design support using the Xilinx Alliance and

Foundation series software packages.

• Guaranteed 20 year life data retention

Description

Xilinx introduces the high-density QPro™ XQ17V16 series

QML configuration PROM which provide an easy-to-use,

cost-effective method for storing large Xilinx FPGA configu-

ration bitstreams. The XQ17V16 is a 3.3V device with a

storage capacity of 16 Mb and can operate in either a serial

or byte wide mode. See Figure 1 for a simplified block dia-

gram of the XQ17V16 device architecture.

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising clock edge, data appears on the PROM

DATA output pin that is connected to the FPGA DIN pin. The

FPGA generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

When the FPGA is in Master SelectMAP mode, it generates

a configuration clock that drives the PROM and the FPGA.

After the rising CCLK edge, data are available on the

PROMs DATA (D0-D7) pins. The data will be clocked into

the FPGA on the following rising edge of the CCLK. When

the FPGA is in Slave SelectMAP mode, the PROM and the

FPGA must both be clocked by an incoming signal. A

free-running oscillator may be used to drive CCLK. See

Figure 2.

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or Foun-

dation series development system compiles the FPGA

design file into a standard Hex format, which is then trans-

ferred to most commercial PROM programmers.

QPro XQ17V16 Military 16Mbit

QML Configuration PROM

DS111 (v1.0) December 15, 2003 08Product Specification

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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1-800-255-7778 Product Specification

Pin Description

DATA[0:7]

Data output is in a high-impedance state when either CE or

OE are inactive. During programming, the D0 pin is I/O.

Note that OE can be programmed to be either active High or

active Low.

CLK

Each rising edge on the CLK input increments the internal

address counter, if both CE and OE are active.

RESET/OE

When High, this input holds the address counter reset and

puts the DATA output in a high-impedance state. The polar-

ity of this input pin is programmable as either RESET/OE or

OE/RESET

. To avoid confusion, this document describes

the pin as RESET/OE, although the opposite polarity is pos-

sible on all devices. When RESET is active, the address

counter is held at “0”, and puts the DATA output in a

high-impedance state. The polarity of this input is program-

mable. The default is active High RESET, but the preferred

option is active Low RESET, because it can connected to

the FPGAs INIT pin and a pullup resistor.

The polarity of this pin is controlled in the programmer inter-

face. This input pin is easily inverted using the Xilinx

HW-130 Programmer. Third-party programmers have differ-

ent methods to invert this pin.

When High, this pin disables the internal address counter,

puts the DATA output in a high-impedance state, and forces

the device into low-ICC standby mode.

CEO

Chip Enable output, to be connected to the CE input of the

next PROM in the daisy chain. This output is Low when the

CE and OE inputs are both active AND the internal address

counter has been incremented beyond its Terminal Count

(TC) value. In other words: when the PROM has been read,

CEO will follow CE as long as OE is active. When OE goes

inactive, CEO stays High until the PROM is reset. Note that

OE can be programmed to be either active High or active

Low.

Figure 1: Simplified Block Diagram for XQ17V16 (does not show programming circuit)

EPROM

Cell

Matrix

Address Counter

D0 Data

(Serial or Parallel Mode)

Output

CLK

BUSY

VCC VPP GND

DS073_02_072600

RESET/

OE/

RESET

D[1:7]

(SelectMAP Interface)

CEO

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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Product Specification 1-800-255-7778

BUSY (XQ17V16 only)

If BUSY pin is floating, the user must program the BUSY bit

which will cause BUSY pin to be internally tied to a

pull-down resistor. When asserted High, output data are

held and when BUSY pin goes Low, data output will

resume.

VPP

Programming voltage. No overshoot above the specified

max voltage is permitted on this pin. For normal read oper-

ation, this pin must be connected to VCC. Failure to do so

may lead to unpredictable, temperature-dependent opera-

tion and severe problems in circuit debugging. Do not leave

VPP floating!

VCC and GND

Positive supply and ground pins.

PROM Pinouts for XQ17V16

(Pins not listed are “no connect”)

Capacity

Controlling PROMs

Connecting the FPGA device with the PROM.

• The DATA output(s) of the PROM(s) drives the DIN

input of the lead FPGA device.

• The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s).

• The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

• The RESET/OE input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

when a reconfiguration is initiated by a VCC glitch.

• The PROM CE input is best connected to the FPGA

DONE pin(s) and a pullup resistor. CE can also be

permanently tied Low, but this keeps the DATA output

active and causes an unnecessary supply current of

15 mA maximum.

• SelectMAP mode is similar to Slave Serial mode. The

DATA is clocked out of the PROM one byte per CCLK

instead of one bit per CCLK cycle. See FPGA data

sheets for special configuration requirements.

FPGA Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are established

by a configuration program. The program is loaded either

automatically upon power up, or on command, depending

on the state of the three FPGA mode pins. In Master Serial

mode, the FPGA automatically loads the configuration pro-

Pin Name 44-pin VQFP 44-pin CLCC

BUSY 24 30

D0 40 2

D1 29 35

D2 42 4

D3 27 33

D4 9 15

D5 25 31

D6 14 20

D7 19 25

CLK 43 5

RESET/OE

(OE/RESET)

13 19

CE 15 21

GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43

CEO 21 27

VPP 35 41

VCC 8, 16, 17, 26, 36,

14, 22, 23, 32,

42, 44

Device Configuration Bits

XQ17V16 16,777,216

Xilinx FPGAs and Compatible PROMs

Device Configuration Bits XQ17V16(s)

XQ2V1000 4,082,656 1

XQ2V3000 10,494,432 1

XQ2V6000 21,849, 568 2

XQV600E 3,961,632 1

XQV1000E 6,587,520 1

XQV2000E 10,159,648 1

XQV100 781,216 XQ1701L(1)

XQV300 1,751,808 1

XQV600 3,607,968 1

XQV1000 6,127,744 1

Notes:

1. See XQ1701L Series (DS062)

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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1-800-255-7778 Product Specification

gram from an external memory. The Xilinx PROMs have

been designed for compatibility with the Master Serial

mode.

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA

mode-select pins are Low (M0=0, M1=0, M2=0). Data is

read from the PROM sequentially on a single data line. Syn-

chronization is provided by the rising edge of the temporary

signal CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line, two control lines, and a clock

line are required to configure an FPGA. Data from the

PROM is read sequentially, accessed via the internal

address and bit counters which are incremented on every

valid rising edge of CCLK.

If the user-programmable, dual-function DIN pin on the

FPGA is used only for configuration, it must still be held at a

defined level during normal operation. The Xilinx FPGA

families take care of this automatically with an on-chip

default pull-up/down resistor or keeper circuit.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for

future FPGAs requiring larger configuration memories, cas-

caded PROMs provide additional memory. After the last bit

from the first PROM is read, the next clock signal to the

PROM asserts its CEO output Low and disables its DATA

line. The second PROM recognizes the Low level on its CE

input and enables its DATA output. See Figure 2.

After configuration is complete, the address counters of all

cascaded PROMs are reset if the FPGA PROGRAM pin

goes Low, assuming the PROM reset polarity option has

been inverted.

QPro XQ17V16 Military 16Mbit QML Configuration PROM

DS111 (v1.0) December 15, 2003 www.xilinx.com 5

Product Specification 1-800-255-7778

Figure 2: (a) Master Serial Mode (b) Virtex SelectMAP Mode

(dotted lines indicates optional connection)

PROGRAM

DIN

CCLK

INIT

DONE

First

PROM

DATA

CEO

BUSY BUSY

CLK

OPTIONAL

Slave FPGAs

with identical

configurations

FPGA

(Low Resets the Address Pointer)

VCC Vpp

OPTIONAL

Daisy-chained

FPGAs with

different

configurations

OE/RESET

DOUT

Modes(1)

BUSY BUSY

Virtex SelectMAP Mode, XQ17V16 only.

4.7K

VCC VCC

VCC Vpp

VCC

(2)

Master Serial Mode

DS073_03_062602

(1) For Mode pin connections, refer to the appropriate FPGA data sheet.

(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.

Cascaded

PROM

DATA

CLK

OE/RESET

PROGRAM

VIRTEX

SelectMAP

BUSY

WRITE

INIT

D[0:7]

CCLK

DONE

CLK

D[0:7]

OE/RESET

First

PROM Second

PROM

Modes(3)

3.3V

External

Osc(4)

CEO

4.7K

(2)

VCC

VCC Vpp

VCC

I/O(1)

(1) CS and WRITE must be pulled down to be used as I/O. One option is shown.

(2) Virtex, Virtex-E is 300 ohms, all others are 4.7K.

(3) For Mode pin connections, refer to the appropriate FPGA data sheet.

(4) External oscillator required for Virtex/E SelectMAP or Virtex-II slave SelectMAP modes.

CLK

D[0:7]

OE/RESET

CEO

VCC

VCC Vpp

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1-800-255-7778 Product Specification

Standby Mode

The PROM enters a low-power standby mode whenever CE

is asserted High. The output remains in a high impedance

state regardless of the state of the OE input.

Programming

The devices can be programmed on programmers supplied

by Xilinx or qualified third-party vendors. The user must

ensure that the appropriate programming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently damage the device.

Absolute Maximum Ratings

Table 1: Truth Table for XQ17V00 Control Inputs

Control Inputs

Internal Address

Outputs

RESET CE DATA CEO ICC

Inactive Low If address < TC(1): increment

If address > TC(1): don’t change

Active

High-Z

High

Low

Active

Reduced

Active Low Held reset High-Z High Active

Inactive High Not changing High-Z High Standby

Active High Held reset High-Z High Standby

Notes:

1. The XQ17V00 RESET input has programmable polarity

1. TC = Terminal Count = highest address value. TC + 1 = address 0.

Symbol Description Conditions Units

VCC Supply voltage relative to GND –0.5 to +7.0 V

VPP Supply voltage relative to GND –0.5 to +12.5 V

VIN Input voltage relative to GND –0.5 to VCC +0.5 V

VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum soldering temperature (10s @ 1/16 in.) +260 °C

TJJunction temperature Ceramic +150 °C

Plastic +125 °C

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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Product Specification 1-800-255-7778

Operating Conditions (3.3V Supply)

DC Characteristics Over Operating Condition

Symbol Description Min Max Units

VCC(1) Supply voltage relative to GND (TC = –55°C to +125°C) Ceramic 3.0 3.6 V

Supply voltage relative to GND (TJ = –55°C to +125°C) Plastic 3.0 3.6 V

TVCC VCC rise time from 0V to nominal voltage 1.0 50 ms

Notes:

1. During normal read operation VPP must be connected to VCC.

2. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise

time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly.

Symbol Description Min Max Units

VIH High-level input voltage 2 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = –3 mA) 2.4 - V

VOL Low-level output voltage (IOL = +3 mA) - 0.4 V

ICCA Supply current, active mode (at maximum frequency) - 100 mA

ICCS Supply current, standby mode - 1 mA

ILInput or output leakage current –10 10 µA

CIN Input capacitance (VIN = GND, f = 1.0 MHz) - 15 pF

COUT Output capacitance (VIN = GND, f = 1.0 MHz) - 15 pF

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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AC Characteristics Over Operating Condition for XQ17V16

Symbol Description Min Max Units

TOE OE to data delay - 15 ns

TCE CE to data delay - 20 ns

TCAC CLK to data delay(2) -20ns

TDF CE or OE to data float delay(3,4) -35ns

TOH Data hold from CE, OE, or CLK(4) 0-ns

TCYC Clock periods 50 - ns

TLC CLK Low time(4) 25 - ns

THC CLK High time(4) 25 - ns

TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns

THCE CE hold time to CLK (to guarantee proper counting) 0 - ns

THOE OE hold time (guarantees counters are reset) 25 - ns

TSBUSY BUSY setup time 5 - ns

THBUSY BUSY hold time 5 - ns

Notes:

1. AC test load = 50 pF.

2. When BUSY = 0.

3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.

4. Guaranteed by design, not tested.

5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.

RESET/OE

CLK

BUSY

DATA

TCE

TOE

TLC

TSCE TSCE THCE

THOE

TCAC

TSBUSY THBUSY

TOH TDF

TOH

THC

DS073_05_072600

TCYC

QPro XQ17V16 Military 16Mbit QML Configuration PROM

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Product Specification 1-800-255-7778

AC Characteristics Over Operating Condition When Cascading

Symbol Description Min Max Units

TCDF CLK to data float delay(2,3) -50 ns

TOCK CLK to CEO delay(3) -30 ns

TOCE CE to CEO delay(3) -35 ns

TOOE RESET/OE to CEO delay(3) -30 ns

Notes:

1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady

state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.

CLK

DATA

CEO

First Bit

Last Bit

TCDF

DS026_07_020300

OE/RESET

TOCK TOOE

TOCE

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Ordering Information

Revision History

The following table shows the revision history for this document.

Date Version Revision

12/15/03 1.0 Initial Xilinx release.

XQ17V16 CC44 M

Manufacturing Grade

Package Type

Device Number

Device Ordering Options

Device Type Package Grade

XQ17V16 CC44 44-pin Ceramic Chip Carrier Package MMilitary Ceramic TC = –55°C to +125°C

VQ44 44-pin Plastic Thin Quad Flat Package NMilitary Plastic TJ = –55°C to +125°C

Valid Ordering Combinations

M Grade N Grade

XQ17V16CC44M XQ17V16VQ44N