SCAN18374T
D Flip-Flop with TRI-STATE®Outputs
General Description
The SCAN18374T is a high speed, low-power D-type
flip-flop featuring separate D-type inputs organized into dual
9-bit bytes with byte-oriented clock and output enable control
signals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and BOUNDARY-SCAN Architecture with
the incorporation of the defined BOUNDARY-SCAN test
logic and test access port consisting of Test Data Input (TDI),
Test Data Out (TDO), Test Mode Select (TMS), and Test
Clock (TCK).
Features
nIEEE 1149.1 (JTAG) Compliant
nBuffered positive edge-triggered clock
nTRI-STATE outputs for bus-oriented applications
n9-bit data busses for parity applications
nReduced-swing outputs source 24 mA/sink 48 mA (Mil)
nGuaranteed to drive 50Ωtransmission line to TTL input
levels of 0.8V and 2.0V
nTTL compatible inputs
n25 mil pitch Cerpack packaging
nIncludes CLAMP and HIGHZ instructions
nStandard Microcircuit Drawing (SMD) 5962-9320701
Connection Diagram
Pin Names Description
AI
(0–8)
,BI
(0–8)
Data Inputs
ACP, BCP Clock Pulse Inputs
Pin Names Description
AOE
1
, BOE
1
TRI-STATE Output Enable Inputs
AO
(0–8)
,BO
(0–8)
TRI-STATE Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100322-1
September 1998
SCAN18374T D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100322 www.national.com
Truth Tables
Inputs AO
(0–8)
ACP AOE
1
AI
(0–8)
XHXZ
NLLL
NLHH
Inputs BO
(0–8)
BCP BOE
1
BI
(0–8)
XHXZ
NLLL
NLHH
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N=L-to-H Transition
Functional Description
The SCAN18374 consists of two sets of nine edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The buffered clock and buffered Output Enable pins
are common to all flip-flops. Each set of the nine flip-flops will
store the state of their individual D inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(ACP or BCP) transition. With the Output Enable (AOE
1
or
BOE
1
) LOW, the contents of the nine flip-flops are available
at the outputs. When the Output Enable is HIGH, the outputs
go to the high impedance state. Operation of the Output En-
able input does not affect the state of the flip-flops.
Logic Diagram
Block Diagrams
DS100322-13
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte-A
DS100322-2
Note: BSR stands for Boundary Scan Register
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Block Diagrams (Continued)
Tap Controller
DS100322-3
Byte-B
DS100322-4
Note: BSR stands for Boundary Scan Register
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Description of Boundary-Scan Circuitry
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location.
Scan cell TYPE1 is intended to solely observe system data,
while TYPE2 has the additional ability to control system
data. (See IEEE Standard 1149.1
Figure 10–11
for a further
description of scan cell TYPE1 and
Figure 10–12
for a fur-
ther description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as well
as at each of the two internal active-high output enable sig-
nals. AOE controls the activity of the A-outputs while BOE
controls the activity of the B-outputs. Each will activate their
respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage iden-
tical to scan cell TYPE1. It captures a fixed logic low.
The INSTRUCTION register is an eight-bit register which
captures the value 00111101.
The two least significant bits of this captured value (01) are
required by IEEE Std 1149.1. The upper six bits are unique
to the SCAN18374T device. SCAN CMOSTestAccess Logic
devices do not include the IEEE 1149.1 optional identifica-
tion register. Therefore, this unique captured value can be
used as a “pseudo ID” code to confirm that the correct device
is placed in the appropriate location in the boundary scan
chain.
MSB →LSB
Instruction Code Instruction
00000000 EXTEST
10000001 SAMPLE/PRELOAD
10000010 CLAMP
00000011 HIGHZ
All Others BYPASS
Bypass Register Scan Chain Definition
Logic 0
DS100322-9
Instruction Register Scan Chain Definition
DS100322-10
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Description of Boundary-Scan Circuitry (Continued)
Scan Cell TYPE1
DS100322-7
Scan Cell TYPE2
DS100322-8
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Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register
Scan Chain Definition (42 Bits in Length)
DS100322-25
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Description of Boundary-Scan Circuitry (Continued)
Boundary-Scan Register Definition Index
Bit No. Pin Name Pin No. Pin Type Scan Cell Type
41 AOE
1
3 Input TYPE1 Control
Signals
40 ACP 54 Input TYPE1
39 AOE Internal TYPE2
38 BOE
1
26 Input TYPE1
37 BCP 31 Input TYPE1
36 BOE Internal TYPE2
35 AI
0
55 Input TYPE1 A–in
34 AI
1
53 Input TYPE1
33 AI
2
52 Input TYPE1
32 AI
3
50 Input TYPE1
31 AI
4
49 Input TYPE1
30 AI
5
47 Input TYPE1
29 AI
6
46 Input TYPE1
28 AI
7
44 Input TYPE1
27 AI
8
43 Input TYPE1
26 BI
0
42 Input TYPE1 B–in
25 BI
1
41 Input TYPE1
24 BI
2
39 Input TYPE1
23 BI
3
38 Input TYPE1
22 BI
4
36 Input TYPE1
21 BI
5
35 Input TYPE1
20 BI
6
33 Input TYPE1
19 BI
7
32 Input TYPE1
18 BI
8
30 Input TYPE1
17 AO
0
2 Output TYPE2 A–out
16 AO
1
4 Output TYPE2
15 AO
2
5 Output TYPE2
14 AO
3
7 Output TYPE2
13 AO
4
8 Output TYPE2
12 AO
5
10 Output TYPE2
11 AO
6
11 Output TYPE2
10 AO
7
13 Output TYPE2
9AO
8
14 Output TYPE2
8BO
0
15 Output TYPE2 B–out
7BO
1
16 Output TYPE2
6BO
2
18 Output TYPE2
5BO
3
19 Output TYPE2
4BO
4
21 Output TYPE2
3BO
5
22 Output TYPE2
2BO
6
24 Output TYPE2
1BO
7
25 Output TYPE2
0BO
8
27 Output TYPE2
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=−0.5V −20 mA
V
I
=V
CC
+0.5V +20 mA
DC Output Diode Current (I
OK
)
V
O
=−0.5V −20 mA
V
O
=V
CC
+0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to V
CC
+0.5V
DC Output Source/Sink Current (I
O
)±70 mA
DC V
CC
or Ground Current
Per Output Pin ±70 mA
Junction Temperature
Cerpack +175˚C
Storage Temperature −65˚C to +150˚C
ESD (Min) 2000V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
SCAN Products 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (V
O
) 0VtoV
CC
Operating Temperature (T
A
)
Military −55˚C to +125˚C
Minimum Input Edge Rate dV/dt 125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of SCAN circuits outside databook specifications.
DC Electrical Characteristics
Symbol Parameter V
CC
(V) Military Units Conditions
T
A
=−55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High 4.5 2.0 V V
OUT
=0.1V
Input Voltage 5.5 2.0 or V
CC
−0.1V
V
IL
Maximum Low 4.5 0.8 V V
OUT
=0.1V
Input Voltage 5.5 0.8 or V
CC
−0.1V
V
OH
Minimum High 4.5 3.15 V I
OUT
=−50 µA
Output Voltage 5.5 4.15
4.5 2.4 V V
IN
=V
IL
or V
IH
5.5 2.4 I
OH
=−24 mA
V
OL
Maximum Low 4.5 0.1 V I
OUT
=50 µA
Output Voltage 5.5 0.1
4.5 0.55 V V
IN
=V
IL
or V
IH
5.5 0.55 I
OL
=48 mA
I
IN
Maximum Input 5.5 ±1.0 µA V
I
=V
CC
, GND
Leakage Current
I
IN
Maximum Input 5.5 3.7 µA V
I
=V
CC
TDI, TMS Leakage −385 µA V
I
=GND
Minimum Input
Leakage 5.5 −160 µA V
I
=GND
I
OLD
Minimum Dynamic 5.5 63 mA V
OLD
=0.8V Max
I
OHD
Output Current
(Note 3) −27 mA V
OHD
=2.0V Min
I
OZ
Maximum Output 5.5 ±10.0 µA V
I
(OE) =V
IL
,V
IH
Leakage Current
I
OS
Output Short 5.5 −100 mA V
O
=0V
Circuit Current (min)
I
CC
Maximum Quiescent 5.5 168 µA V
O
=Open
Supply Current TDI, TMS =V
CC
5.5 930 µA V
O
=Open
TDI, TMS =GND
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DC Electrical Characteristics (Continued)
Symbol Parameter V
CC
(V) Military Units Conditions
T
A
=−55˚C to +125˚C
Guaranteed Limits
I
CCt
Maximum I
CC
5.5 2.0 mA V
I
=V
CC
− 2.1V
Per Input V
I
=V
CC
− 2.1V
5.5 2.15 TDI/TMS Pin, Test One
with the Other Floating
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Noise Specifications
Symbol Parameter V
CC
(V) Military Units
T
A
=−55˚C to +125˚C
Guaranteed Limits
V
OLP
Maximum High Output Noise
(Notes 4, 5) 5.0 0.8 V
V
OLV
Minimum Low Output Noise
(Notes 4, 5) 5.0 -0.8 V
Note 4: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
AC Electrical Characteristics
Normal Operation
Symbol Parameter V
CC
(V)
(Note 6)
Military Units
T
A
=−55˚C to +125˚C
C
L
=50 pF
Min Max
t
PLH
, Propagation Delay 5.0 2.5 11.0 ns
t
PHL
CP to Q 2.5 12.0
t
PLZ
, Disable Time 5.0 1.5 10.5 ns
t
PHZ
1.5 10.3
t
PZL
, Enable Time 5.0 2.0 13.0 ns
t
PZH
2.0 11.0
AC Operating Requirements
Normal Operation
Symbol Parameter V
CC
(V)
(Note 6)
Military Units
T
A
=−55˚C to +125˚C
C
L
=50 pF
Guaranteed Minimum
t
S
Setup Time, H or L 5.0 3.0 ns
Data to CP
t
H
Hold Time, H or L 5.0 1.5 ns
CP to Data
t
W
CP Pulse Width 5.0 5.0 ns
f
max
Maximum ACP/BCP 5.0 70 MHz
Clock Frequency
Note 6: Voltage Range 5.0 is 5.0V ±0.5V.
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AC Electrical Characteristics
Scan Test Operation
Symbol Parameter V
CC
(V)
(Note 7)
Military Units
T
A
=−55˚C
to +125˚C
C
L
=50 pF
Min Max
t
PLH
, Propagation Delay 5.0 3.5 15.8 ns
t
PHL
TCK to TDO 3.5 15.5
t
PLZ
, Disable Time 5.0 2.5 12.8 ns
t
PHZ
TCK to TDO 2.5 12.6
t
PZL
, Enable Time 5.0 3.0 16.7 ns
t
PZH
TCK to TDO 3.0 15.0
t
PLH
, Propagation Delay 5.0 5.0 21.2
t
PHL
TCK to Data Out 5.0 21.7 ns
During Update-DR State
t
PLH
, Propagation Delay 5.0 5.0 21.2
t
PHL
TCK to Data Out 5.0 21.0 ns
During Update-IR State
t
PLH
, Propagation Delay 5.0 5.5 21.5
t
PHL
TCK to Data Out 5.5 23.0 ns
During Test Logic
Reset State
t
PLZ
, Propagation Delay 5.0 4.5 19.6
t
PHZ
TCK to Data Out 4.0 18.9 ns
During Update-DR State
t
PLZ
, Propagation Delay 5.0 5.0 22.4
t
PHZ
TCK to Data Out 5.0 22.4 ns
During Update-IR State
t
PLZ
, Propagation Delay 5.0 5.5 23.3
t
PHZ
TCK to Data Out 5.0 22.9 ns
During Test Logic
Reset State
t
PZL
, Propagation Delay 5.0 5.0 22.6
t
PZH
TCK to Data Out 5.0 19.7 ns
During Update-DR State
t
PZL
, Propagation Delay 5.0 7.0 26.2
t
PZH
TCK to Data Out 6.5 23.1 ns
During Update-IR State
t
PZL
, Propagation Delay 5.0 7.0 27.4
t
PZH
TCK to Data Out 7.0 24.5 ns
During Test Logic
Reset State
Note 7: Voltage Range 5.0 is 5.0V ±0.5V.
All Propagation Delays involving TCK are measured from the falling edge of TCK.
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AC Operating Requirements
Scan Test Operation
Symbol Parameter V
CC
(V)
(Note 8)
Military Units
T
A
=−55˚C
to +125˚C
C
L
=50 pF
Guaranteed Minimum
t
S
Setup Time, H or L 5.0 3.0 ns
Data to TCK (Note 9)
t
H
Hold Time, H or L 5.0 4.5 ns
TCK to Data (Note 9)
t
S
Setup Time, H or L 5.0 3.0 ns
AOE
1
, BOE
1
to TCK (Note 11)
t
H
Hold Time, H or L 5.0 4.5 ns
TCK to AOE
1
, BOE
1
(Note 11)
t
S
Setup Time, H or L 5.0 3.0 ns
Internal AOE, BOE
to TCK (Note 10)
t
H
Hold Time, H or L 5.0 3.0 ns
TCK to Internal AOE,
BOE (Note 10)
t
S
Setup Time 5.0 3.0 ns
ACP, BCP (Note 12) to TCK
t
H
Hold Time 5.0 3.5 ns
TCK to ACP, BCP (Note 12)
t
S
Setup Time, H or L 5.0 8.0 ns
TMS to TCK
t
H
Hold Time, H or L 5.0 2.0 ns
TCK to TMS
t
S
Setup Time, H or L 5.0 4.0 ns
TDI to TCK
t
H
Hold Time, H or L 5.0 4.5 ns
TCK to TDI
t
W
Pulse Width TCK 5.0
H 15.0 ns
L 5.0
f
max
Maximum TCK 5.0 25 MHz
Clock Frequency
T
pu
Wait Time, Power Up 5.0 100 ns
to TCK
T
dn
Power Down Delay 0.0 100 ms
Note 8: Voltage Range 5.0 is 5.0V ±0.5V.
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 9: This delay represents the timing relationship between the data Input and TCK at the associated scan cells numbered 0–8, 9–17, 18–26 and 27–35.
Note 10: This delay represents the timing relationship between AOE, BOE and TCK at scan cells 36 and 39 only.
Note 11: Timing pertains to BSR 38 and 41 only.
Note 12: Timing pertains to BSR 37 and 40 only.
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Capacitance
Symbol Parameter Typ Units Conditions
C
IN
Input Pin Capacitance 4.0 pF V
CC
=5.0V
C
OUT
Output Pin Capacitance 13.0 pF V
CC
=5.0V
C
PD
Power Dissipation 34.0 pF V
CC
=5.0V
Capacitance
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13
Physical Dimensions inches (millimeters) unless otherwise noted
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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56-Lead Ceramic Flatpak (F)
NS Package Number WA56A
SCAN18374T D Flip-Flop with TRI-STATE Outputs
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
