SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 x 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor Interface Control Logic IRA, ORA, AEA, and AFA Flags Synchronized by CLKA D D D D D D Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Low-Power 0.8-m Advanced CMOS Technology Supports Clock Frequencies up to 50 MHz Fast Access Times of 13 ns Packaged in 132-Pin Ceramic Quad Flat Package description The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 x 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths. The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A. The SN54ACT3632 is characterized for operation over the full military temperature range of -55C to 125C. For more information on this device family, see the following application reports: D D D FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005) Metastability Performance of Clocked FIFOs (literature number SCZA004) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 NC NC VCC CLKB ENB W/RB CSB GND IRB ORB AFB AEB VCC MBF1 MBB RST2 FS1 GND FS0 RST1 MBA MBF2 AEA AFA VCC ORA IRA CSA W/RA ENA CLKA GND NC HFP PACKAGE (TOP VIEW) NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 130 128 126 124 122 120 118 131 129 127 125 123 121 119 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC - No internal connection 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 functional block diagram MBF1 RST1 FIFO1, Mail1 Reset Logic 512 x 36 SRAM Write Pointer Output Register Port-A Control Logic Input Register Mail1 Register CLKA CSA W/RA ENA MBA 36 Read Pointer Status-Flag Logic IRA AFA ORB AEB FIFO1 36 FS0 FS1 A0-A35 ProgrammableFlag Offset Registers 9 B0-B35 FIFO2 Status-Flag Logic Output Register Read Pointer IRB AFB 36 Write Pointer 512 x 36 SRAM Input Register ORA AEA Mail2 Register FIFO2, Mail2 Reset Logic RST2 Port-B Control Logic CLKB CSB W/RB ENB MBB MBF2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 Terminal Functions TERMINAL NAME I/O A0-A35 I/O Port-A data. The 36-bit bidirectional data port for side A. AEA O (port A) Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2 is less than or equal to the value in the almost-empty A offset register, X2. AEB O (port B) Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1 is less than or equal to the value in the almost-empty B offset register, X1. AFA O (port A) Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in FIFO1 is less than or equal to the value in the almost-full A offset register, Y1. AFB O (port B) Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations in FIFO2 is less than or equal to the value in the almost-full B offset register, Y2. B0-B35 I/O Port-B data. The 36-bit bidirectional data port for side B. CLKA I Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the low-to-high transition of CLKA. CLKB I Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the low-to-high transition of CLKB. CSA I Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is high. CSB I Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is high. ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A. ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B. I Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0 or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full and almost-empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2 go high, the first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs. IRA O (port A) Input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and writes to its array are disabled. IRA is set low when FIFO1 is reset and is set high on the second low-to-high transition of CLKA after reset. IRB O (port B) Input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and writes to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition of CLKB after reset. MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the A0-A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects FIFO2 output-register data for output. MBB I Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects FIFO1 output-register data for output. MBF1 O Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high when FIFO1 is reset. MBF2 O Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 also is set high when FIFO2 is reset. ORA O (port A) Output-ready flag. ORA is synchronized to the low-to-high transition of CLKA. When ORA is low, FIFO2 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high. ORA is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded to empty memory. FS1, FS0 4 DESCRIPTION POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION ORB O (port B) Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory. RST1 I FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST1 is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. RST2 I FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur while RST2 is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. W/RA I Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a low-to-high transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is high. W/RB I Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a low-to-high transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is low. detailed description reset The FIFO memories of the SN54ACT3632 are reset separately by taking their reset (RST1, RST2) inputs low for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low, and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory. A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1) inputs for choosing the almost-full and almost-empty offset programming method. almost-empty flag and almost-full flag offset programming Four registers in the SN54ACT3632 are used to hold the offset values for the almost-empty and almost-full flags. The port-B almost-empty flag (AEB) offset register is labeled X1 and the port-A almost-empty flag (AEA) offset register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1 and the port-B almost-full flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A (see Table 1). Table 1. Flag Programming FS1 FS0 RST1 RST2 X1 AND Y1 REGISTERS X2 AND Y2 REGISTERS H H X 64 X H H X X 64 H L X 16 X H L X X 16 L H X 8 X L H X X 8 L L Programmed from port A Programmed from port A X1 register holds the offset for AEB; Y1 register holds the offset for AFA. X2 register holds the offset for AEA; Y2 register holds the offset for AFB. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 almost-empty flag and almost-full flag offset programming (continued) To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset (RST1) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can be reset simultaneously or at different times. To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0 and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register uses port-A (A8-A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from 1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high and both FIFOs begin normal operation. FIFO write/read operation The state of the port-A data (A0-A35) outputs is controlled by the port-A chip select (CSA) and the port-A write/read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is high. The A0-A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the A0-A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low, and IRA is high. Data is read from FIFO2 to the A0-A35 outputs by a low-to-high transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO reads and writes on port A are independent of any concurrent port-B operation. Table 2. Port-A Enable Function Table CSA W/RA ENA MBA CLKA A0-A35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L In high-impedance state FIFO1 write L H H H In high-impedance state Mail1 write L L L L X Active, FIFO2 output register None L L H L Active, FIFO2 output register FIFO2 read L L L H X Active, mail2 register None L L H H Active, mail2 register Mail2 read (set MBF2 high) The port-B control signals are identical to those of port A with the exception that the port-B write/read select (W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0-B35) outputs is controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB is high or W/RB is low. The B0-B35 outputs are active when CSB is low and W/RB is high. Data is loaded into FIFO2 from the B0-B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is low, ENB is high, MBB is low, and IRB is high. Data is read from FIFO1 to the B0-B35 outputs by a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO reads and writes on port B are independent of any concurrent port-A operation. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 FIFO write/read operation (continued) Table 3. Port-B Enable Function Table CSB W/RB ENB MBB CLKB B0-B35 OUTPUTS PORT FUNCTION H X X X X In high-impedance state None L L L X X In high-impedance state None L L H L In high-impedance state FIFO2 write L L H H In high-impedance state Mail2 write L H L L X Active, FIFO1 output register None L H H L Active, FIFO1 output register FIFO1 read L H L H X Active, mail1 register None L H H H Active, mail1 register Mail1 read (set MBF1 high) The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select may change states during the setup- and hold-time window of the cycle. When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the port's chip select, write/read select, enable, and mailbox select. synchronized FIFO flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2. Table 4. FIFO1 Flag Operation NUMBER OF WORDS IN FIFO1 SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA ORB AEB AFA IRA 0 L L H H 1 to X1 H L H H (X1 + 1) to [512 - (Y1 + 1)] H H H H (512 - Y1) to 511 H H L H 512 H H L L X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from port A. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 Table 5. FIFO2 Flag Operation NUMBER OF WORDS IN FIFO2 SYNCHRONIZED TO CLKA SYNCHRONIZED TO CLKB ORA AEA AFB IRB 0 L L H H 1 to X2 H L H H (X2 + 1) to [512 - (Y2 + 1)] H H H H (512 - Y2) to 511 H H L H 512 H H L L X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from port A. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. output-ready flags (ORA, ORB) The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. A FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an output-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. From the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the output-ready flag synchronizing clock; therefore, an output-ready flag is low if a word in memory is the next data to be sent to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the output-ready flag high and shifting the word to the FIFO output register. A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tsk1, or greater, after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 7 and 8). input-ready flags (IRA, IRB) The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array. When the input-ready flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when the input-ready flag is low and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls an input-ready flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written in a minimum of two cycles of the input-ready flag synchronizing clock; therefore, an input-ready flag is low if less than two cycles of the input-ready flag synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high transition on the input-ready flag synchronizing clock after the read sets the input-ready flag high. A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tsk1, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figures 9 and 10). 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 almost-empty flags (AEA, AEB) The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). An almost-empty flag is low when its FIFO contains X or fewer words and is high when its FIFO contains (X + 1) or more words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its almost-empty flag to reflect the new level of fill. Therefore, the almost-empty flag of a FIFO containing (X + 1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 11 and 12). almost-full flags (AFA, AFB) The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset programming). An almost-full flag is low when its FIFO contains (512 - Y) or more words and is high when its FIFO contains [512 - (Y + 1)] or less words. A data word present in the FIFO output register has been read from memory. Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [512 - (Y + 1)] or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [512 - (Y + 1)]. An almost-full flag is set high by the second low-to-high transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [512 - (Y + 1)]. A low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time tsk2, or greater, after the read that reduces the number of words in memory to [512 - (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figures 13 and 14). mailbox registers Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port-data-transfer operation. A low-to-high transition on CLKA writes A0-A35 data to the mail1 register when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB writes B0-B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail register are ignored while the mail flag is low. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port mailbox select input is low and from the mail register when the port-mailbox select input is high. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB, W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register remains intact after it is read and changes only when new data is written to the register. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 CLKA th(RS) CLKB th(FS) tsu(RS) tsu(FS) IIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII RST1 FS1, FS0 0,1 tpd(C-IR) tpd(C-IR) IRA tpd(C-OR) ORB tpd(R-F) AEB tpd(R-F) AFA tpd(R-F) MBF1 Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight FIFO2 is reset in the same manner to load X2 and Y2 with a preset value. CLKA 4 tsu(FS) RST1, RST2 IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII IIIIII IIIIIIIIIII III III IIII IIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII th(FS) FS1, FS0 0,0 tpd(C-IR) IRA tsu(EN) tsk1 th(EN) ENA tsu(D) th(D) A0-A35 AFA Offset (Y1) AEB Offset (X1) AFB Offset (Y2) CLKB AEA Offset (X2) First Word to FIFO1 1 2 tpd(C-IR) IRB tsk1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tsk1, IRB may transition high one cycle later than shown. NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles. Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA IRA III III III IIIIII III IIIIII III IIIIII III IIIIII IIIIIII IIIIII IIIIII IIIIII IIIIIIIIIIIIII th(EN) tsu(EN) CSA IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII tsu(EN) W/RA th(EN) tsu(EN) MBA th(EN) tsu(EN) ENA th(EN) tsu(D) A0-A35 th(EN) tsu(EN) th(EN) tsu(EN) th(D) W1 Written to FIFO1 W2 No Operation Figure 3. Port-A Write Cycle for FIFO1 tc tw(CLKH) tw(CLKL) CLKB IRB tsu(EN) CSB IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII tsu(EN) W/RB tsu(EN) MBB tsu(EN) ENB tsu(D) B0-B35 Written to FIFO2 III III III III III III IIIIIII IIIIIII IIIIII IIIIII th(EN) th(EN) th(EN) th(EN) tsu(EN) th(D) W1 W2 IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIIIIIIIIIII IIIIIIIIIIIIII th(EN) th(EN) tsu(EN) No Operation Figure 4. Port-B Write Cycle for FIFO2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA ORA IIII IIII IIIIIIII IIIIII IIIIII IIIIIIII IIIIII IIIIII II II CSA W/RA tsu(EN) MBA th(EN) tsu(EN) th(EN) tsu(EN) ENA No Operation tpd(M-DV) ta ta ten W1 A0-A35 W2 IIIII IIIII IIIII IIIII th(EN) tdis W3 Read from FIFO2 Figure 5. Port-A Read Cycle for FIFO2 tc tw(CLKH) tw(CLKL) CLKB ORB IIII IIII IIIIIIII IIIIII IIIIIII IIIIIIII IIIIII IIIIIII II II CSB W/RB tsu(EN) MBB th(EN) tsu(EN) th(EN) tsu(EN) ENB tpd(M-DV) B0-B35 ta ta ten W1 W2 Read from FIFO1 Figure 6. Port-B Read Cycle for FIFO1 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 No Operation W3 IIIII IIIII IIIII IIIII th(EN) tdis SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA CSA W/RA MBA Low High tsu(EN) IIII IIII IIII IIII tsu(EN) ENA IRA A0-A35 High tsu(D) IIIIIIIIIIIIIIIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIII th(EN) th(EN) th(D) W1 tc tw(CLKL) tsk1 tw(CLKH) 1 CLKB 2 3 tpd(C-OR) tpd(C-OR) Old Data in FIFO1 Output Register ORB CSB Low W/RB High MBB Low IIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIII tsu(EN) ENB th(EN) ta B0-B35 Old Data in FIFO1 Output Register W1 tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the FIFO1 output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, the transition of ORB high and load of the first word to the output register may occur one CLKB cycle later than shown. Figure 7. ORB-Flag Timing and First Data-Word Fall Through When FIFO1 Is Empty POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB CSB Low W/RB Low tsu(EN) IIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIII th(EN) MBB tsu(EN) th(EN) ENB IRB High tsu(D) B0-B35 th(D) W1 tsk1 tc tw(CLKL) tw(CLKH) 1 CLKA 2 3 tpd(C-OR) tpd(C-OR) Old Data in FIFO2 Output Register ORA CSA Low W/RA Low MBA Low IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII tsu(EN) th(EN) ENA ta A0-A35 W1 Old Data in FIFO2 Output Register tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition of ORA high and load of the first word to the output register may occur one CLKA cycle later than shown. Figure 8. ORA-Flag Timing and First Data-Word Fall Through When FIFO2 Is Empty 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKB CSB Low W/RB High MBB Low IIII III IIII III tsu(EN) ENB ORB High th(EN) ta B0-B35 Previous Word in FIFO1 Output Register Next Word From FIFO1 tsk1 tc tw(CLKH) 1 CLKA FIFO1 Full IRA CSA W/RA MBA ENA tw(CLKL) 2 tpd(C-IR) tpd(C-IR) Low IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIII High tsu(EN) th(EN) tsu(EN) th(EN) tsu(D) A0-A35 th(D) To FIFO1 tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, IRA may transition high one CLKA cycle later than shown. Figure 9. IRA-Flag Timing and First Available Write When FIFO1 Is Full POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tc tw(CLKH) tw(CLKL) CLKA CSA Low W/RA Low MBA Low IIII III IIII III tsu(EN) ENA ORA th(EN) High ta A0-A35 Previous Word in FIFO2 Output Register Next Word From FIFO2 tsk1 tc tw(CLKH) 1 CLKB FIFO2 Full IRB CSB tw(CLKL) 2 tpd(C-IR) tpd(C-IR) Low IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII W/RB Low tsu(EN) MBB tsu(EN) ENB tsu(D) B0-B35 IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII th(EN) th(EN) th(D) To FIFO2 tsk1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk1, IRB may transition high one CLKB cycle later than shown. Figure 10. IRB-Flag Timing and First Available Write When FIFO2 Is Full 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 CLKA IIIIIIIIII IIIIIIIIII tsu(EN) ENA th(EN) tsk2 CLKB AEB 1 2 tpd(C-AE) X1 Words in FIFO1 tpd(C-AE) IIIIIIIIII IIIIIIIIII (X1 + 1) Words in FIFO1 tsu(EN) ENB th(EN) tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AEB may transition high one CLKB cycle later than shown. NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been read from the FIFO. Figure 11. AEB When FIFO1 Is Almost Empty CLKB IIIIIIIIII IIIIIIIIII tsu(EN) ENB th(EN) tsk2 CLKA 1 2 tpd(C-AE) AEA X2 Words in FIFO2 tpd(C-AE) IIIIIIIIII IIIIIIIIII (X2 + 1) Words in FIFO2 tsu(EN) ENA th(EN) tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AEA may transition high one CLKA cycle later than shown. NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been read from the FIFO. Figure 12. AEA When FIFO2 Is Almost Empty POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 tsk2 CLKA IIIIIIIIII IIIIIIIIII tsu(EN) ENA 1 tpd(C-AF) AFA 2 th(EN) tpd(C-AF) (512 - Y1) Words in FIFO1 [512 - (Y1 + 1)] Words in FIFO1 IIIII IIII IIIII IIII CLKB tsu(EN) ENB th(EN) tsk2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tsk2, AFA may transition high one CLKB cycle later than shown. NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been read from the FIFO. Figure 13. AFA When FIFO1 Is Almost Full tsk2 CLKB IIIIIIIIII IIIIIIIIII tsu(EN) ENB 1 tpd(C-AF) AFB 2 th(EN) [512 - (Y2 + 1)] Words in FIFO2 tpd(C-AF) (512 - Y2) Words in FIFO2 CLKA ENA th(EN) IIIII IIIII tsu(EN) tsk2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tsk2, AFB may transition high one CLKA cycle later than shown. NOTE A: FIFO2 write (CSB = L, W/RB= L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been read from the FIFO. Figure 14. AFB When FIFO2 Is Almost Full 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 CLKA th(EN) tsu(EN) CSA W/RA MBA ENA IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII th(D) tsu(D) A0-A35 III III III III III III IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII W1 CLKB tpd(C-MF) tpd(C-MF) MBF1 CSB W/RB IIII MBB IIIIII IIII IIII IIII IIII tsu(EN) ENB ten B0-B35 tpd(M-DV) tpd(C-MR) th(EN) tdis W1 (remains valid in mail1 register after read) FIFO1 Output Register Figure 15. Mail1 Register and MBF1 Flag POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 CLKB th(EN) tsu(EN) CSB IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIIII IIIIIII IIIIIII W/RB MBB ENB tsu(D) B0-B35 W1 III III III III III IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII th(D) CLKA tpd(C-MF) tpd(C-MF) MBF2 CSA IIIII W/RA MBA IIIIIII IIII III IIII IIII tsu(EN) ENA ten A0-A35 tpd(M-DV) tpd(C-MR) tdis W1 (remains valid in mail2 register after read) FIFO2 Output Register Figure 16. Mail2 Register and MBF2 Flag 20 th(EN) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. recommended operating conditions MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current -4 mA IOL TA Low-level output current 8 mA 125 C High-level input voltage 2 Operating free-air temperature -55 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 2.4 TYP VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = -4 mA IOL = 8 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI = VCC or 0 VO = VCC or 0 ICC VCC = 5.5 V, VI = VCC - 0.2 V or 0 CSA = VIH A0-A35 0 CSB = VIH B0-B35 0 CSA = VIL CSB = VIL ICC VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Co VI = 0, VO = 0, UNIT V 0.5 V 5 A 5 A 400 A A0-A35 1 mA B0-B35 1 All other inputs Ci MAX 1 f = 1 MHz 4 pF f = 1 MHz 8 pF All typical values are at VCC = 5 V, TA = 25C. This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 through 17) MIN MAX UNIT 50 MHz fclock tc Clock frequency, CLKA or CLKB 20 ns tw(CLKH) tw(CLKL) Pulse duration, CLKA and CLKB high 8 ns Pulse duration, CLKA and CLKB low 8 ns tsu(D) Setup time, A0-A35 before CLKA and B0-B35 before CLKB 5 ns tsu(EN) Setup time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB 5 ns tsu(RS) tsu(FS) Setup time, RST1 or RST2 low before CLKA or CLKB 6 ns 8.5 ns th(D) th(EN) Hold time, A0-A35 after CLKA and B0-B35 after CLKB 1 ns Hold time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB Hold time, RST1 or RST2 low after CLKA or CLKB 1 ns 4 ns Hold time, FS0 and FS1 after RST1 and RST2 high 3 ns Skew time between CLKA and CLKB for ORA, ORB, IRA, and IRB 9 th(RS) th(FS) tsk1 Clock cycle time, CLKA or CLKB Setup time, FS0 and FS1 before RST1 and RST2 high ns tsk2 Skew time between CLKA and CLKB for AEA, AEB, AFA, and AFB 16 ns Requirement to count the clock edge as one of at least four needed to reset a FIFO Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and CLKB cycle. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see Figures 1 through 17) PARAMETER fmax ta MIN MAX 50 UNIT MHz Access time, CLKA to A0-A35 and CLKB to B0-B35 3 15 ns tpd(C-IR) tpd(C-OR) Propagation delay time, CLKA to IRA and CLKB to IRB 2 10 ns Propagation delay time, CLKA to ORA and CLKB to ORB 1 10 ns tpd(C-AE) tpd(C-AF) Propagation delay time, CLKA to AEA and CLKB to AEB 1 10 ns Propagation delay time, CLKA to AFA and CLKB to AFB 1 10 ns Propagation delay time, CLKA to MBF1 low or MBF2 high and CLKB to MBF2 low or MBF1 high 0 10 ns Propagation delay time, CLKA to B0-B35 and CLKB to A0-A35 3 18.7 ns Propagation delay time, MBA to A0-A35 valid and MBB to B0-B35 valid 3 13 ns tpd(R-F) Propagation delay time, RST1 low to AEB low, AFA high, and MBF1 high, and RST2 low to AEA low, AFB high, and MBF2 high 1 20 ns ten Enable time, CSA and W/RA low to A0-A35 active and CSB low and W/RB high to B0-B35 active 2 18 ns tdis Disable time, CSA or W/RA high to A0-A35 at high impedance and CSB high or W/RB low to B0-B35 at high impedance 1 13 ns tpd(C-MF) tpd(C-MR) tpd(M-DV) Writing data to the mail1 register when the B0-B35 outputs are active and MBB is high Writing data to the mail2 register when the A0-A35 outputs are active and MBA is high 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION IOL Output Under Test VLoad CL (see Note A) IOH LOAD CIRCUIT 3V Timing Input 3V High-Level Input 1.5 V 1.5 V 1.5 V GND GND tsu Data, Enable Input th tw 3V 1.5 V 3V 1.5 V Low-Level Input GND 1.5 V GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 3V 1.5 V 1.5 V GND tPLZ tPZL Low-Level Output 3V 3V 1.5 V VOL tpd VOH 1.5 V 1.5 V GND tPZH High-Level Output 1.5 V Input In-Phase Output 0V tpd 1.5 V tPHZ VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. Includes probe and jig capacitance B. tPZL and tPZH are the same as ten. C. tPLZ and tPHZ are the same as tdis. CONDITIONS FOR LOAD CIRCUIT IOL (mA) IOH (mA) VLoad (V) CL (typical) (pF) tPZH tPZL 8 4 0 20 4 8 3 20 tPHZ tPLZ 8 6 1.5 20 8 6 1.5 20 PARAMETER tPD 4 8 1.5 Includes probe and test-fixture capacitance 20 Figure 17. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SN54ACT3632 512 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A - SEPTEMBER 1996 - REVISED APRIL 1998 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 300 fdata = 1/2 fclock TA = 75C CL = 0 pF I CC(f) - Supply Current - mA 250 VCC = 5.5 V 200 VCC = 5 V 150 VCC = 4.5 V 100 50 0 0 10 20 30 40 50 fclock - Clock Frequency - MHz Figure 18 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 60 70 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN54ACT3632HFP ACTIVE CFP HFP Pins Package Eco Plan (2) Qty 132 1 TBD Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ACT3632 : * Catalog: SN74ACT3632 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MGQF011 - DECEMBER 1996 HFP (S-GQFP-F132) CERAMIC QUAD FLATPACK 1.540 (39,12) SQ 1.460 (37,08) 116 84 117 83 0.025 (0,635) 1 0.014 (0,36) 0.009 (0,20) 17 51 18 50 0.800 (20,32) TYP 0.150 (3,81) 0.110 (2,79) 0.960 (24,38) SQ 0.940 (23,88) 0.008 (0,20) 0.004 (0,10) 4073432/A 11/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Body dimensions do not include glass overrun or protrusions. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF and ZigBee(R) Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video & Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2008, Texas Instruments Incorporated