ty AP = o: HARRIS SEMICOND SECTOR G) HARRIS CMOS Presettable Up/Down Counters High-Voltage Types (20-Volt Rating) CD45106 ~ BCD Type CD4516B ~ Binary Type @ CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchron- ously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capa- bility) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number Present on the jam inputs by a high level on the PRESET ENABLE line. The CD45108 will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the CARRY-IN input is heid low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in paratlel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The CD45108 and CD4516B can be cascaded in the ripple mode by connecting the CARRY- QUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subse- quent counting stage. (See Fig. 15). These devices are similar to types MC 14510 and MC 14516. The CD45108 and CD4516B Series types are supplied in 16-lead hermetic duai-in- line ceramic packages (D and F suffixes), 16-lead dual-in-tine plastic packages (E suf- fix), and in chip form (H suffix). evagleie 61 YOO 34 2 ist crock aa 3 l4}-93 Bria Ble oARRY A$ 2b p2 ae ub a2 TaRAy Sut i? UP/DOWN ss i8 RESET TOP VIEW) tea ott CD45108, CD45168 TERMINAL ASSIGNMENT Features: = Medium-speed operation -- fox = 8 MHz typ. at 10 V Synchronous internal'carry propagation Reset and Preset capability @ 100% tested for quiescent current at 20 V @5-V, 10-V, and 15-V parametric ratings = Standardized symmetrical output characteristics = Maximum input current of 1 ZA at 18 V over full package temperature range; 100 nA at 18 V and 25C Noise margin (full package-temperature range}: 1 Vat Vpp =5V 2 Vat Vop = 10 V 2.5 Vat Vpop = 15 V = Meets all requirements of JEDEC Tentative Standard No. 13B, Standard Specifications for Description of B Series CMOS Devices 44E D BM 4302271 0037568 2 ERIHAS TY S29 3-O G CD4510B, CD4516B Types PRESET. ENAGLE, 045108, CD4616B FUNCTIONAL DIAGRAM Ps F 93 4 LE o4 Yoo #16 CLOCK Vegea UP/O08N ? CARRY WN P tanay oor 92CS-24824 Applications: = Up/Down difference counting | Multistage synchronous counting = Multistage ripple counting @ Synchronous frequency dividers OPERATING CONDITIONS AT Ta = 25C, Unless Otherwise Specified For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges. Characteristic Vpp | Min.| Max.| Units Supply Voltage Range (At Ta = Full Package-Temperature Range) 3] 18 Vv 5 150] - Clock Pulse Width, ty 10 75] | ns 15 60; 5 - |2 Clock Input Frequency, fet 10 -|4 MHz 15 15.5 5 150} Preset Enable or Reset Removal Time 10 80] - ] os 16 60] Clock Rise and Fall Time, t ~7 5 oc ise and Fall Time, t-Ct, tL 15 _ 5 us 5 130} Carry-In Setup Time, ts 10 60) | ns 15 45] - 5 360) Up-Down Setup Time, ts 10 160 | ns 15 107 ~ 5 220 | = Preset Enable or Reset Pulse Width, tw 10 100} - | ns 15 75] - Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter {similar to setup time). *{f more than one unit is cascaded in the parallel clocked application, t-CL should be made less than or equal to the sum of the fixed Propagation delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitive load, 3-249 COMMERCIAL CMOS HIGH VOLTAGE ICspe kee SA lin | A Ree HARRIS SEMICOND SECTOR MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE RANGE, {Vop) Vollages referanced to Vgg Terminal) ... INPUT VOLTAGE RANGE, ALLINPUTS | OC INPUT CURRENT, ANY ONE INPUT see POWER DISSIPATION PER PACKAGE (Po): ForTa = -55C to #100C FORT, = FULL PACKAGE -TEMPERATURE RANGE (All Package Types) OPERATING-TEMPERATURE RANGE (Ta) STORAGE TEMPERATURE RANGE stg) LEAD TEMPERATURE (DUAING SOLDERING): At distance 1/16 + 1/32 inch (1.59 + 0.79mm) from casa for 1 aa P: cvocx CARRY CUT aLu_npurs SROTECTED ay cMcs PROTECTION NETWORK canay a yproown * WOE > CD45108B Types - -O.5V to +20 - -0.5V lo Vpp +0.5V soomw Tee cet e ee ee eee eens Derate Linearity at 12mW/C to 200mW OS MAX oo. cece eee +2659C 2 a2 3 93 22e- 2709302 Fig.3 Logic Diagram for CD4570B. ORAIN-*3-SOULRCE WOR"AGE -uggiy TARE tus! iz z 8 3 z = DUTPUT mGm (SOURCE I CURKE Fig. Mieumum Output high fsource} current Characceristecs. LOAD CAPACITANCE (, IF a2es-20r27a1 Fig.6 Typical transition ume vs. load capacitance, 3-250 PROPAGATION DELAY TIME (tay. teni)ns | 4302027) 00375659 4 BERHAS T ~TS* 23-09 ORAIN-TO-SGURCE VOLTAGE (og]~ wee gar aes. Fig.1 Typical output tow (sink) current characteristics. CRAIN-TO-SOURCE VOLTAGE Woul=v 925 -24g 8 Fig.2 Minimum output low {sink} current characteristics, ORAIN-TO-SOURCE YOLTASE (ps}v wees tantay Fig.4 Typical outaut high {source} current characteristics, | iGIENT TEMPERATURE (Talsa5 o LCA Capacntance s2ts-27305 Fig.7 Typical Propagation delay timevs, load capacitance for clock- ta-Q outputs.HARRIS SEMICOND SECTOR YUE D MM 4302271 0037570 O BHAS TAS -Hd-04 - CD4510B Types STATIC ELECTRICAL CHARACTERISTICS | Load capacitance erleacie > Bs CONDITIONS LIMITS AT INDICATED TEMPERATURES {C} 3 CHARACTER. itz IsTIC 3B UNITS] ice Yo | Vin [Yoo ~ 25 (v} (v) | tv) | -55 | 40 | +85 | +125] Min. | Typ. | Max. x3 Ss Quiescent Device - 05 5 5 5 150 150 ~ 0.04 5 32 Current, = {010} 10 | 10 { 10 | 300 [ 300 | [004 [10 A BS 'DD Max ~ __{915/ 1s | 20 [20 | 606 [00 | - | ooat 20] F - 0,20} 20 | 100 | 100 [3000 [30001 0.08 100 : Output Low o4 | os] 5 | o64 [oer | 042 | 0.36] 051 1 = SUPPLY VoUTSVoo exeneaiace (Sink) Current 05 0,10] to 16 15 1.1 0.9 1.3 26 _ Fig.8 Typical maximum clock input frequency tou Min is fowls [a2 fa [oa [oa laa | 6a] vs. supply voltage, Output High 4.6 05 5 0 64] -0.61 | -0.42 | -0.36/-0.51 -1 - mA (Source) 2.5 05 5 -2 4} -18 | -1.3 [-1.15]-16 7-32 - Current, 95 [o1ol 10 [-16[-15 |-11 | -09 |-19 | 26 TO foH Min teolet 20A8 135 |0.15] 15 |-42] -4 ~28 | -2.4 /-3.4 | -6.8 - eit .=50 oF Output Voitage ~ 0.5 5 0.05 - 0 0.05 Sra, Low-Level. - fo. 10 0.05 = o | 005 VOL Max ~ 0.15] 15 0.05 - 0 0.05 Vv Output Voltage - 0s 5 495 4.95 5 - wo an High-Level. ~ 0.10} 10 9.95 9.95 | 10 = g VOH Min (o1s} 15 14.95 1495] 15 | ow Input Low o6.45{ f 5 15 |[- lis Z Voltage, 19 - | 10 3 -~f{- 3 [=e Vit Max. Ww > 1.5,13.5[ - 15 4 = a 4 Vv ot 1 10 to? 103 1o* = 3 " _ = CLOCK INPUT FREQUENCY (feuliHz. 92s-27007 Ss Input High 0.5. 4.5 = 5 35 35 Fig.9 Typical dynamic power dissipation 8 = Voltage, 1g - 10 7 7 = _ vs. frequency. Vi Min Pye i3s] - fos nN mufp- fe taput Current a lay Max, - 0.18] 18 | s01f sor | st 1 | - Je1o-5} son] pa Yoo ri an pz" oz 23" a3 pa* a4 INPUTS t Reser ss ORESET ENABLE x) cuscK nes tags s5 Fig. 11 Quiescent-device-cur- rent test circuit. Yoo INPUTS | Yoo 4 Nore . MEASURE INPUTS ) _ SEQUENTIALLY, Vss ~~ TO GOTH Vop AND Vgg- ~_ |, CONNECT ALL UNUSED INPUTS TO EITHER Von. OF Ves: vss S2CS-2Fac2 Fig. 12 Input-current Fig. tu Logic Oragram for CO4516B. vecy-atezanz test circuit, 3-251HARRIS SEMICOND SECTOR CD4510B Types U4E D DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25C, CL =50 pF, input ty, ty = 20 ns, RL = 200 kQ MA 4302271 0037571 2 BEHAS Condit- Limits ions : Characteristic Vpp All Packages Units {V) | Min. Typ. | Max. Propagation Delay Time (tpHL. tPLH) 5 - 200 400 Clock-t0- Output (See Fig. 10) 10 = 100 200 ns 15 - 75 150 5 - 210 420 Preset or Reset-to-Q Output 10 - 105 210 ns 15 - 80 160 5 - 240 480 Clock-to-Carry Out 10 - 120 240 ns 15 - 90 180 5 - 125 250 Carry-In-to-Carry Out 10 - 60 120 ns 15 - 50 | 100 5 - 320 640 Preset or Reset-to-Carry Out 10 - 160 320 ns 15 - 125 260 5 - 100 200 Transition Time (tTHL, tTLH) (See Fig. 9} 10 ~ 50 100 ns 15 - 40 80 5 2 4 - Max. Clack Input Frequency (fol) 10 4 8 - MHz 15 5.5 11 - Input Capacitance (Cyy) - 5 7.5 pF Set-up Time. ts 5 25 12 - Preset Enable to J, 10 10 6 - 15 10 5 _ Hoid times. ty 5 60 30 _ Clock to Carry-In 10 30 4 > 15 30 1 _ ns 5 30 10 _ Clock to Up/Down 10 30 4 ~_ 15 30 5 _ 70 35 - Preset Enable to J, 10 40 20 _ 15 40 20 _ 3-252 THY S-Q3OF9 Yoo INPUTS outeuTs ao Ven 4 Nom | @ 2 vie > + 4 = NOTE: TEST ANY ONE INPUT, Vss WITH OTHER INPUTS AT Yoo OR Vss- 92cs-2r4ocnt Fig, 13 input-voltage test circuit. el e-20ns {be 20rs fa re : 30% wha tf50% | PelO% Ves . VARIABLE a f WIOTH i steu~27012 Fig.14 Power-dissipation test circuit and input waveform.HARRIS SEMICOND SECTOR W4E D MM 4302271 0037572 4 BEIHAS CD4510B Types TY, S- Q3-0 7 CARRY X = DONT CARE TRUTH TABLE o 2 30 40 % 6& HM 80 3 [CO CARRY : : : , : ' Scuny 97+. 2:3 4:5,6; 71a, 9! airtels elsfalifofe:sielr|o . azeu-27008 Fig. 15 Timing Diagram for CD4510B. 92-100 (2.337-2.540) clock TARRY iN uPrcown AESET L 4-10 (0.102-0.254) 97-105 {2.464 - 2.667) PE vi " "0 92$-27037a1 Yss Dimensions and Pad Layout tor CD4510BH. o COMMERCIAL CMOS HIGH VOLTAGE ICs gat Qs a4 CARRY Out counr sj 6 a oe ee : ! i i s2eu-2700981 Fig. 16 Timing diagram for CD4516B. 90-98 {2.286- 2.489} of el ~ SAMPLE ae AND }J =a HOLD to-B1T RALLEL a A/D A ANALOG 0] :6-CHANNEL START CONVERTER UTPUTS puts | Le] MAT PLEXER # c0sg67 cLock o CCNVERSION => ne Logic eae ~ SELECT = a INPUTS | END > 4-10 ar a4 0102-0.254) 92C8-2703681 pReseT, s| CO4516 ao- NPUTS, (2.032- 2.235) T CLOCK PRESET wsearca Dimensions and Pad Layout for CD45 16BH. This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD45168. Fig. 17 ~ Typical 16-channel, 10-bit data acquisition system. Dimensions in parentheses are in millimeters and are derived from the basic inch dimeasions as indicated. Grid graduations are in mils (1073 inch), 3-253HARRIS SEMICOND SECTOR QUE D GM 430e271 0037573 & GMHAS CD4510B Types T-Y4S-93O7F PARALLEL CLOCKING UP/DOWN > PRESET > ENABLE . UP/D PE J) va dy dg UVO PE dg J3 dg UPD PE J) Jo Jz uq * 4 cI co4siosi6 co.OCjc i c04si0716 co OA.I. coasiosis 0.0> R CL % Gg Q3 O% R CLO} Op O3 % RCL Q Q2 Q3 04 cLocK > RESET > * CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4510/16 IC's. These negative- joing glitches do not affect proper CO4510/16 operation. However, if the SaRny OUT signals are used to trigger other edge-sensitive logic devices, such as FFs or counters, the CARRY OU f signals should be gated with the clock signal . using a 2-input OR gate such as CD40718. RIPPLE CLOCKING JP/ DOWN > PRESET > ~~ iit Liid UPD PE 4 vo J3 Ug UVYD PE J) dp Jy vg UP/D PE J dp v3 U4 4 cI co4sios16 co 4 cI cpasioze = =6co {9 cr cpasione ~0. D> R CL Q, Qo Q3 Q4 RCL Q Qo 03 Q4 FR cL & Qo O3 Q%4 CLOCK Lf va coao7i8 RESET > RIPPLE CLOCKING MODE THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT THE ONLY RESTRICTION ON CHANGING 7 THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH For cascading counters operating Ina fixed up count or down-count mode, the OR gates are not required between stages, and is connected directly to (he CLinput of the next stage with CI grounded. 92CL-171I94R5 Fig. 18 Cascading counter packages. 3-254