& HIGH-SPEED OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS TILBUFFER 740L6000 TTLINVERTER 740L6001 oPTOMOGIC LSTTLto ouos BUFFER 740L6010 rm CMOS INVERTER 740L6011 PART | LOGICCOMPATIBILITY | LOGIC OUTPUT @ Industry first LSTTL to TTL and LSTTL to NUMBER | INPUT | OUTPUT | FUNCTION | CONFIGURATION CMOS complete logic-to-logic optocoupler 74OL6000| LSTTL TTL BUFFER TOTEM POLE = Incorporates LED drive circuitryuse as 740L6001| LSTTL | TTL | INVERTER} TOTEMPOLE logic gate 74OL6010;) LSTTL CMOS BUFFER | OPEN COLLECTOR = Very hich d 740L6011| LSTTL | CMOS | INVERTER | OPEN COLLECTOR ery nigh spee = Choice of buffer or inverter @ Choice of TTL or CMOS compatible output up to 15 volts SYMBOL m@ Fan-out of 10 TTL loads, fan-in 1 LSTTL load = Internal noise shieldvery high CMR of +15 @ Transmission line interfacereceiver and KV Ia s : . driver w Provides superior 5300 VRMS Withstand m@ Excellent as bridged receiver in fast LAN operations. (WTV)quarantees 480 VAC Buffer highways = Compact 6-pin DIP . Bus interface : : m@ UL recognized (File #E90700) = Logic family interface with ground loop noise & Saine noise immunity as LSTTL/TTL elimination . @ High speed AC/DC voltage sensing Driver for power semiconductor devices Inverter @ Level shifting = Replaces fast pulse transformers 1Veo (INpUt Veo) 6Veco (Output Voc) 2-Vy (Data in) 5-V, (Data out) 3-GND, (Input GND) 4-GND, (Output GND) 74OL6000 74016001 740L6010 740L6011 NOISE NOISE NOISE NOISE SHIELD Craig Cb SHIELD SHIELD SHIELD ha od Ehaecd JE ] Eb#! bat) E A] BL BE 5 2004 C2005 C2002 C2003 LSTTL to TTL Buffer LSTTL to TTL Inverter LSTTL to CMOS Buffer LSTTL to CMOS Inverter Le]OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS OPTOLOGIC" is the first family of truly logic compatible optically coupled logic interface gates. The family consists of four device types offering LSTTL to TTL and LSTTL to CMOS interfacing. Each of these interfacing functions is available as a buffer (A=B), or as an inverter (A=B). The LSTTL input compatibility is provided by an input integrated circuit, with industry standard logic levels. This input amplifier IC switches a temperature compensated current source driving a high speed GaAsP/GaAs 700 nm LED emitter. 22 kQ TYP. INPUT -- = GND LSTTL INPUT CIRCUIT 2010 All Inputs Operating temperature range ....... Input supply voltage ................ Input voltage ........... 2... cee Output supply voltage .............. Output voltage..................05, Output current ..................0.. Power dissipation ................. Lead temperature (soldering, 10 sec) 55C to +125C .... OC to +70C This novel integration scheme eliminates CTR degradation over time and temperature. The emitter is optically coupled to an integrated photodetector/high-gain, high-speed output amplifier IC. The superior 15 kV/14s common-mode noise rejection is ensured through the use of an optically transparent noise shield. The TTL compatible output has a totem-pole with a fan-out of 10. The CMOS compatible output has an open collector Schottky-clamped transistor that interfaces to any CMOS logic between 4.5 and 15 volts. --- Vee > % 150.0 TYP OUTPUT = GND TTL OUTPUT CIRCUIT 2009 74QL6000/01 Output eee Ee The 7401.6010/11 may also be used to drive power MOS FETS or transistors up to 15 volts. The Optologic coupler family typically offers propagation of delays of 60 ns and can support 15 MBaud data communication. The two input chips and the output chip are assembled in a 6-pin DIP high insulation voltage plastic package. It provides a withstand test voltage of 5300 VRMS (1 minute), which is recognized as a working voltage of 480 VRMS. - - -_ Vee RL OUTPUT = GND CMOS QUTPLT CIRCUIT C2026 740L6010/11 Output Storage temperature range .......... Operating temperature range bee eee eee 7V_ Input supply voltage ........ 6... cee eee eee eee 7V_ Inputvoltage .... See eee 7V Output supply voltage . 6... bee eee ee 7V_ = Output voltage 0. cece eee eee beeen eee 40mA Outputcurrent .................0............. 40 MA beeen 350mW_ = Power dissipation ......................... 350 mW* Lene e eee 260C __ Lead temperature (soldering, 10 sec) ........... 260C *See Fig. 12 for maximum allowable output supply voltage.@& HIGH-SPEED OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS ICAL CHARACTERISTIC: iE PARAMETER SYM MIN TYP* MAX UNITS TEST CONDITIONS FIG. NOTES 740L6000 740L6001 740L6000/01 TTL OUTPUT 740L6000/01 Input supply voltage Veet 4.5 5.0 5.5 Vv 1 Output supply voltage Veco 45 5.0 5.5 Vv 1 High-level input voltage Ve 2.0 v 1 Low-level input voltage Vit 0.8 Vv 1 Input clamp _ = voltage Vie 1.2 v Veo#4.5 V, L=18 mA 1 TON vent tn 1.0 40.0 BA Veo =5.5 Vv, Vn=4.5 Vv 1 Low-level input cv urent -200.0 -400.0 yA Vou=5.5 V, Vy =0.4 V 1 Input supply - - current (high) locas 10.0 14.0 mA Voa=5.5 V, Vin=Vin 1 Input supply _ _ current (low) leon 10.0 14.0 mA Veo = 5.5 V, Vin=Vi 1 High-level _ _ Veo =4.5 V, Veco 4.5 V, output voltage Von 2.4 3.0 Vv Vw=2.0V Vy=0.8V Io -400,0A 1 0.6 Vv Veo=4 Vv, Voco=4.5 Vv, - . =16mA Low-level Vou 0.3 _ Wa=08V 0 Vye2.0y # 8m 1 output voltage 05 V Voo=4.5 V, Voco=4.5 V, . lo=4 mA High-level _ _ _ _ Voa=4.5 V, Veco=4.5 V, output current bon 8.0 10.0 mA Vin= Vin Vin=Va Von=2.4V 1 Low-level _ _ Veo =4.5 V, Veco=4.5 V, output current lor 16.0 mA Vn=0.8 V Vin=2.0V 4 =0.6 V 1 output current los 5.0 25.0 40.0 mA Vin=Veu Vino Vie Voo=5.5 V, Veco=5.5 V 1 Output supply _ - Veo=5.5 V, Vo=Vor current (high) 'c2or 90 15.0 mA Vi= Vu Vnv=Va Voco=5.5 V 1 Output supply _ _ Veoi=5.5 V, Vo=Vou, current (low) leoot 8.0 12.0 mA Viv= Vi Vin=Viu Veoo=5.5 V 1 *All typical values are at T,=25C PARAMETER TEST CONDITIONS TTL OUTPUT 740L6000/01 Propagation delay time for output low level Propagation delay time : tr 70 100 ns 15, 17 1 for output high level nt Vea=5 V, Veco=5 V Output rise time for output high level Output fall time nap a for output low level 4 5 ns 15,17 1 tea 60 100 ns 15, 17 1 t 45 ns 15, 17 1OPTOELECTRONICS HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS s niess PARAMETER SYM MIN TYP* MAX UNITS TEST CONDITIONS FIG. NOTES 740L6010 740L6011 740L6010/11 CMOS OUTPUT 740L6010/11 Input supply voltage Vee 4.5 5.0 5.5 Vv 1 Output supply voltage Veco 45 15.0 Vv 1,3 High-level input voltage Vn 2.0 V 1 Low-level input voltage Va 08 Vv 1 Input clamp _ _ __ voltage Vix 1.2 Vv Veo=4.5 V, l=-18mA 1 High-level input Svourrent In 10,5 40.000 HA Vea=5.5 V, Vn=4.5 V 1 row lever input h -200.0 -400.0 yA Veu=5.5 V, Vi=0.4V 1 Input supply _ _ current (high) loci 10.0 14.0 mA Veci=5.5 V, Vin=Via 1 Input supply = = current (low) loon 10.0 14.0 mA Veo =8.5 V, Vin=Vin 1 06 Veo =4.5 V, Veco=4.5 V, . lo=16mMmA Low-level Vor 0.4 Vv Vn=O.8V Vy=2.0V 1 output voltage 05 Vooi=4-5 V, Voco=4.5 V, . lo=4 mA High-level _ _ Veo 4.5 V, Von=15 V, output current! 1.0 100.0 0 HA Viv= Vig Vn= Vin Voco=4.5 15 V 1 Low-level _ _ Veo =4.5 V, Vo.=0.6 V, output current ln 16.0 mA Vw=0.8V Vin=2.0V Voco=4.5 15 V 1 9.0 12.0 Vea =5.-5 v, Vo=Vou, . V.Co=4.5 V Output supnly lecon mA Vn=Via Vin= Vi 1 current (high to 180 Voa=5.5 V, Vo= Vou, . . Voco=15 V 8.0 12.0 Veo =5.5 Vv, Vo=Vou . , Voeco=4.5 V Output supply lecot mA Viv=Vi Vin= Via 1 current (low) Veo=5.5 V, Vo=Vo, 11.0 18.0 Veoo=15 V *Ail typical values are at T,=25C Se : ITCHING CH. TI less Otherwise Speci , PARAMETER MIN TYP MAX UNITS TEST CONDITIONS FIG. NOTES TTL OUTPUT 740L6010/11 Propagation delay time for output low level toa 60 120 ns 15,18 1 Propagation delay time for output high level Ts 100 180 ns Veo=5 V 15.18 4 Output rise time Veco=5 V, R.=470 0 for output high level t 50 ns 18,18 1 Output fall time for output low level 4 5 ns 15,18 1OPTOELECTROMICS PARAMETER CAL CHARA SYMBOL LOGIC-TO-LOGIC OPTOCOUPLERS TEST CONDITIONS 740L6000/01/10/11 Common mode transient immunity at logic high level output cM. 5000 15000 Vins Vea=5 V, Veco=5 V, 16,19 Vow=50 Vop Common mode transient immunity ary 5000 15000 Vius 16.19 at logic low level output . us , Cammon mode coupling C. 0.005 oF capacitance om . Capacitance (input-output) Cro 0.7 pF V.o=0, f=1 MHz 2 Withstand insulation test T,=25C, voltage Viso 5300 VAMS t=1 min, lo <1 pA 2 Insulation resistance Riso 10" a Vio=500 VDC 2 100 = ; 0 hin E a Veo = 5.5V x Vin=4.5V 5 -100- vyvi=o4v 35 b = Leeper iL 2 -200 | eee -300 -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE (C) C2028 Fig. 1. Input Current vs. Ambient Temperature lcci INPUT SUPPLY CURRENT (mA) Iccin 7 -601 740L6000-6010 cc = 5.5 V -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE (C) 2029 Fig. 2. input Supply Current vs. Ambient Temperature / f Z t 12 = 2] | ~ ~~ 6 --740L.6010/6011 loco OUTPUT SUPPLY CURRENT (mA)} Veo =5.5V 3b Veco = 15 V se: 740L6010/6011 740L6000/6001 Veo = 5.5 V Veci = 5.5 V Veco=5.5V Veco = 5.5 V -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE ( C} C2030 Fig. 3. Output Supply Current vs. Ambient Temperature lo QUTPUT CURRENT (mA) Veer = 4.5 V Veco =4.5V Voi = 0.6 V Vou =2.4V |OH (740L6000/6001) -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE (C) C2031 Fig. 4. Output Current vs. Ambient TemperatureOPTOELECTRONICS HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS 1 -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE (C) C2036 Fig. 9. 74QL6010/11 Switching Times vs, Ambient Temperature 5 S 05 | Veer =4.5V wi 4 Veco =4.5V g lon = -400 pA 5 0.4 > 3 zc @loL=16mA 1 eT Zz os x 5 2 o i ee @ lov = 4 mA zm 0.2 1 4 = Veo =4.5V 7 O14 Veco =4.5V a -20 0 20 40 60 80 100 a -40 -20 0 20 40 60 80 100 > Ta AMBIENT TEMPERATURE (C) Ta AMBIENT TEMPERATURE ( C) 2032 C2033 Fig. 5. High-Level Output Voltage Fig. 6. Low-Level Output Voltage vs. Ambient Temperature vs. Ambient Temperature 5 Veci= 5.0 V Veco = 5.0V Vocin = 4.5 V PW = 200 ns 4 Veco =15V 7] @ 200} PERIOD=1 us Vout = 15V 1 100 3 3 50 ] / F oO & 2 Zz x 5 10 = 5 1 = Y a 0 |__| 1 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Ta AMBIENT TEMPERATURE (C) Ta AMBIENT TEMPERATURE (C) C2034 C2035 Fig. 7. 740L6010/11 Leakage Current Fig. 8. 740L6000/01 Switching Times vs. Ambient Temperature vs. Ambient Temperature Veoo = 5 = 4700 _M am=Vcco = 15V PW = 200 @1 Voc! =5V PERIOD =1 us Sg _ Wy 2 200 tPLH a~ ~ tPLH ol 8 | 100 tr =F 7 = 5V w tPHL z S = 5V = 50 tr 2 > 6 = 2V Ee = 6 2S 5 = 08V = 8= 4 = 470 0) (740L6010/6011) 5 1 ig & 25 3 z 5 oz 5 = @ oc Fr 1 Qo 500 1000 1500 2000 2500 Vcm COMMON MODE TRANSIENT AMPLITUDE (V) 2037 Fig. 10. Common Mode Rejection vs. Common Mode Voltage 1-62 HIGH-SPEED OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS z Lt DISSIPATION @ Ta = 25C E cd ter cco x - ~ 10 a g y a 5 = 300 5 / a i= wi 8 w = x 4) i ge | a ' < 2 t i xz 200 9 bro Q o x Veco ak Veci = 5.5 & 4 RANGE FOR 740L6000/6001 Za ] 3 68 1 | FO g ? | ~ & 0 0 4 5 6 7 8 9 10 14 12 13 14 15 4 5 6 7 8 9 10111213 1415 Vec SUPPLY VOLTAGE (V) Veco OUTPUT SUPPLY VOLTAGE (V) C2038 C2039 Fig. 11. Supply Current vs. Fig. 12. Power Dissipation vs. Supply Voltage Ambient Temperature = 16 > 100 | = wy 1s z oO 3 ft E14 | 0 Q E ( 9 13 faa e 5-100 5 1.2 oO cc 5 xm ot a F = 200 5 io Voc = 5.0V S Veco = 5.0V z 7 0.9 Vecoi= 4.5 V x -40 - 40 ao 4 -300 LL. 5 0 -20 0 20 60 00 0 1 9 3 4 5 6 > Ta AMBIENT TEMPERATURE (C) Vin INPUT VOLTAGE (V) C2040 C2041 Fig. 13. Input Threshold Voltage vs. Fig. 14, Input Current vs. Ambient Temperature Input Voltage Veet g 1 @ Veco +V ' 6 +5 uF 470.41 (740L6010/11) 2 Wooo +5 {470.0 7aOLe010/11) "PULSE GEN - 2 5 PW = 200 ns PERIOD =1us w= 575 }Zo = 500 3 4 "Ci = 15pF STRAY CAPACITANCE INCLUDING PROBE C2042 20463 Fig. 15. Switching Time Test Circuit Fig. 16. Common Mode Rejection Test Circuit= HIGH-SPEED OPTOELECTRONICS LOGIC-TO-LOGIC OPTOCOUPLERS INPUT, INPUT. 3.2 OUTPUT, Vo (7416000) caoLenty OUTPUT, Vo. OUPTUT, Vo (7406001) (740L6011) Fig. 17. 740L6000/01 Switching Times Fig. 18. Switching Parameters vs. Ambient Temperature 740L6010/11 ~ S50V Vem / \ dVem _ Vom OV dt te VOoH \S CMH A _ Vig = 2.0 V (MIN.) JX Vo = 0.8 V (MAX.) VoL CML te C2046 - Fig. 19. Common Mode Rejection E | Waveforms 8.39 2.33 REF (NPUT | {INPUT OUTPUT OUTPUT Voc j | GND GND Veo BUS , |; BUS BUS BUS ! ! ' ' ! | | ( DATA DATA IN 11 OUT td [ay _ 7 it le it it Vl it i i | by i | il 1] Vy id C2027 0.40 DIMENSIONS IN mm Fig. 20. Suggested PCB Lay-out PACKAGE CODE K ST1603A 1. The Veco And Vea Supply voltages to the device must each be bypassed by a 0.1 ,.f capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristics. its purpose is to stabilize the operation of the high-gain amplifiers. Failure to provide the bypass will impair the DC and switching properties. The total lead length between capacitor and optocoupler should not exceed 1.5mm. See Fig. 20. 2. Device considered a two-terminal device: Pins 1, 2 and 3 shorted together, and Pins 4, 5 and 6 shorted together. 3. For example, assuming a Vec, of 5.0 V, and an ambient temperature of 70C, the maximum allowable Veco is 12.1 V. 1-64@ OPTOELECTRONICS HIGH-SPEED LOGIC-TO-LOGIC OPTOCOUPLERS PRSG 100 ns BIT INTERVAL 74OL6000 BUFFER Local area data communication systems can greatly improve their noise immunity by including OPTOLOGIC gates in the design. The Optologic input amplifier offers the feature of very high input impedance that permits their use as bridged line receivers. The system shown above illustrates an optically isolated transmitter and multidrop receiver system. The network uses a 74O0L6000 and buffer (Figure D) to isolate the transmitter and drive the 75Q, coax cable. This application uses a 1000 ft. aerial suspension 750 CATV coax cable with data taps at 250 ft. intervals. The 74OL6001s function as bridged receivers, and as many as 30 receivers could be placed along the line with minimal 42-11 HORIZONTAL=20 ns/DIV VERTICAL =2 V/DIV Figure A 109 2N4252 2N2222 ALL DIODES ING263 = C2047 Figure D Buffer |< 1000 F. L804 LS04 8 9 10 signal degradation. The communication cable is terminated with a single 75Q load at the far end of the line. Signal quality Eye Pattern is shown in Figures A, B and C witha 1OMBaud NRZ Psuedo-Random Sequence (PRS). Traces 1-3 in Figure A describes the transmitter section. Traces 4-7 in Figure B show the output of the four Optologic bridged terminations. Traces 8-11 in Figure C illustrate Eye Pattern as 5 saeiiatiaiiewee . ee oa HORIZONTAL=20 ns/DIV 42-12,02 VERTICAL=2 V/DIV Figure B LSo4 HORIZONTAL =20 ns/DIV VERTICAL =2 V/DIV 750 }250 rome 250 rope 250 rope 250 rr] TERMINATION 740.L6001 ssn 7ao.6001_\/ 74016001 5 8 Z "1 LSso4 C2048 seen at the output of a 74LS04 logic gate. The data quality is well preserved in that only a 30% Eye closure is seen at the receiver located 1000 ft. from the transmitter. The data communication system is - completely optically isolated from all of the terminal equipments. Power for the transmitter (Veco) and receiver (Voci) is taken from an isolated power supply and distributed through a drain or messenger wire. 42-13,03 Figure C _NOTES: All Optologic Gate Input and Output Amplifiers Bypassed With 0.1 wF Capacitors PRSG=Pseudo Random Sequence Generator 1to 11 Refer To Testpoints; See Waveforms on Figs. A, B and C 1-65