MOTOROLA wt SEMICONAD CI, a TECHNICAL DATA Advance Information MC145031 MC145031 Encoder MC145032 MC145032 Decoder MC145033 MC145033 Encoder/Decoder MC145034 MC145034 Encoder MC145035 MC145035 Decoder The encoders convert parallel address and data inputs into the Manchester DW SUFFIX code format and output the information serially via a data out pin. 28 SOG PACKAGE The decoders revert the serial Manchester-coded input back into binary and ' CASE 751F compare the incoming address with local one. If both addresses match, an output valid signal (VD) is asserted and the proper data appears at the data out pins. ORDERING INFORMATION The difference between the MC145031/2 and MC145034/5 is the valid out- MC14503xDW SOG Package put pin, VD. The valid output of the MC145031/2 is a toggle function while the MC145034/5 is a one shot valid address output pulse if a correct data se- quence and matched address is received. The MC145033 encoder/decoder has a status output. The status pin, when high, indicates the device is encoding. During decoding or standby, status is low. Typical Applications: Remote Control, Security Systems, and Keyless Entry e Manchester Coding RC Oscillator, No Crystal Required Binary Address and Data Inputs Two-Word Transmit Sequence Built-in Input Data Amplifier Schmitt-Trigger Serial Input for Excellent Noise Immunity Coda Break Output with Adjustable Error Code Transmission Time Window e Operating Voltage Range: 2 to 6 V Operating Temperature Range: ~40 to 85C * MC145031 Encoder/MC145032 Decoder Pair: 13 Address and 4 Data Lines or 17 Address Lines * MC145033 Encoder/Decoder: 15 Address Lines MC145034 Encoder/MC145035 Decoder Pair: 13 Address and 4 Data Lines or 17 Address Lines This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-43MC145031MC145032MC145033*MC145034eMC145035 BLOCK DIAGRAM OF MC145031/2/3/4/5 OSC-Ri OSC-R2 OSCC | j OSCILLATOR WITH ENABLE STATUS ANDDIVIDER =| > Tc145033 ONLY) MANCHESTER DATAOUT ENCODER 9 (MC145031/3/4 ONLY) TXEN (Mo145001/9/4 ONLY) ENCODER CONTROL s 1 ADORESS/ | POWER DATA | ADDRESS/DATA ON i RESET GENERATOR COMPARATOR AVINDOW FLOP > (mc145032:96 ONLY) (Motasoa26 ONLY) e| GENERATOR AX DATA MANCHESTER (M0145032/9/5 ONLY) aB> DECODER RESET (MC145032/35 ONLY) C (MC145032/45 ONL MONO- DATA STABLE | wy DATA Ly pops PIN 28 = Vpp Ose. OUTPUT (MC145032/5 ONLY) PIN 27 = Vgg | ob (MG145032/3/5 ONLY) MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-44MC145031MC145032MC145033eMC145034MC145035 PIN ASSIGNMENTS MC145031 ENCODER MC145032 DECODER MC145033 ENCODER/DECODER aod: 2) vo alt 2D Vp Aoi 2D Vp Ai Q2 27 0 Vss Ai fJ2 27 [] Vsg Ai 2 27 0 Vss 23 26 [J OSC-R2 a2 13 26 ] Osc-R2 az 3 26 {] OSC-R2 a3 (]4 25 {] OSc-c Aa (J 4 25 1) Osc AS 4 25 [] osc-c Ags 24 [] OSC-R1 AM 5 24 [] OSC-RI Aa (5 24 [] OSC-Ri A5 6 23 (INC. 45 6 23 J vb AS 6 23 0 w 46 7 22 DNC. Ae 7 22 ce As 7 22 foe A7 [J8 21 TNC. A7 8 21 f) RXDATA A7 [8 21 1] RXDATA Ag (79 20 f] NC. Ag 9 20 [] RESET As q9 20 [] RESET Ag (J 10 19 [] DATAOUT A9 (J 10 19 [] MODE AQ QJ 10 19 [] DATAOUT Ato 11 18 0 TXEN Ato (} 11 18 () Ce Ato [Jit 18 [] TXEN Ail 12 17 7 Ate Ail] 12 17 f) At603 Ail QJ 12 7 CE Ai2 13 16 D) a1s/02 Ai2 1] 13 16 D A152 Al2 413 16 f] status Aigo [J 14 15) Atami AIaDO [} 14 15 D aia Ai3 (]14 15] ara MC145034 ENCODER MC145035 DECODER w01e 2D vo wo: 20 vo Ai 92 27 1 Vsg Al J2 27 1) Vsg A243 26 [J OSC-R2 a2 3 26 [] osc-R2 A3 4 25 f] Osc A3 4 25 [] Osc-c M5 24 [J OSC-R1 AB 5 24 [] OSC-RI AS 6 23 TNC. As 6 23 f] vb Ab 7 22 [I NC. As 7 22 Ice A7 8 a ONG. A7 (Js 21 [} RXDATA AB 9 20 I) NC. ag 9 20 [] RESET Ag 10 49 1} DATAOUT Ag {10 19 [] MODE Ato O11 18 fT TXEN Ate Q 11 18 {} Ce AN [712 17 D Aie03 Alt (12 17 f] Atana Az 913 16 D aise Ai2 913 16 1) aism2 AtaDo [J 14 15 [I] Ata A1300 {14 15 J} Alani MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 645MC145031MC145032MC145033MC145034MC145035 MAXIMUM RATING* (Voltages Referenced to Vcc) This device contains protection cir- Symbol Parameter Value Unit cuitry to guard against damage due Vpp DC Supply Voltage 0.5 to +0.7 i] to high static voltages or electric 7 fields. However, pracautions mustbe Vin DE Input Voltage O5tovpp+05 | V taken to avoid application of any volt- Vout DC Output Voltage -0.5toVpp10.5 | V age higher than maximum rated volt- i; DC Input Current, Pin mA ages to this high impedance circuit. in pu per 10 For proper operation, Vin and Vout lout DC Output Current, per Pin +10 mA should be constrained to the range Vsss(Vin of Vout)SVDD- IpD DC Supply Current, Vpp and Vss Pins +30 mA Except for the Address inputs, un- Po Power Dissipation, per Packaget 500 mw Usedinputs must always be tied to an appropriate logic voltage level (e.g., Tsig Storage Temperature 5 to +150 C gither Vgg or Vpp). The Address in- TL Lead Temperature (10-second soldering) 260 C puts may be left open, see Pin De- scriptons. Unused outputs must be * Maximum Ratings are those values beyond which damage to the device may occur. t Power Dissipation Temperature Derating -12 MWC from 65C to 85C left open. ELECTRICAL CHARACTERISTICS (Ta-40 to 85C, C,_=-50 pF, Vpp=2.5 to 6 V unless otherwise stated) Symbol Parameter Test Condition Vpp | Guaranteed Unit v Limit Vpp Power Supply Voltage Range _ 2.0 to6.0 Vv VIL Maximum Low-Level Input Voltage Except RXDATA 25 0.3 Vv 6.0 1.2 VIH Minimum High-Level Input Voltage Except RXDATA 25 1.9 Vv 6.0 4.5 VoL Maximum Low-Level Output Voltage lour=0 pA 2.5 0.15 V lout=0.4 mA 0.4 lout=0 WA 6.0 0,15 lout=1.0 mA 0.4 Vou | Minimum High-Level Output Voltage lour=0 BA 2.5 2.35 v lout=-0.4 MA 2.0 lout=0 WA 6.0 5.85 lout=1 OmA 5.5 lin Maximum Input Current RXDATA | Vin=Vpp or Vsg 6.0 +80 pA TXEN, Reset, OSC-R2 403 li Maximum High-Level Input Leakage Current A0-A16 | Vin=Vop 6.0 0.3 WA Iie Maximum Low-Level Pull-Up Current AO-A1N6 | Vin=Vss 6.0 -100 WA loz Maximum 3-State Leakage Current Data Out | Vout=VDD or Vss 6.0 +500 nA lop Maximum Quiescent Supply Current (per Package) Device in standby mode, 2.5 25 pA Vin=VDD or Vs for TXEN, 6.0 100 Decoder in, Reset, OSC-R2. Vin=Vss, Vpp. or open for AO-A16. lout=0 HA Idd Maximum RMS Operating Supply Current (per Package) Oscillator Frequency 25 700 pA =500 kHz. 6.0 2500 Vin=VSs or VoD for TXEN, Reset, OSC-R2. Vin=Vss, VDD. or open for A0-A16. lour=0 pA lo_ | Code Break Sink Current CB 5 mA Vin Minimum RXDATA Input Level For Decoder Square wave, see Figure 1 6.0 200 mV pp MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-46MC145031*MC145032MC145033MC145034MC145035 AC ELECTRICAL CHARACTERISTICS (Ta=25C, C_=50 pF, Vpp=2.5 to 6 V unless otherwise stated) Symbol Parameter Yoo Guaranteed Unit fose Maximum Oscillator Frequency (50% Duty Cycle) (Figure 2) _ 500 kHz tg Debounce Time, TXEN (guarantees 1 encoding sequence) _ 500 osc cycles ty Minimum Input Puise Width, TXEN or Reset (Figure 3) 25 200 ns 6.0 80 Cin Maximum Input Capacitance 10 pF 5k 21 DEVICE UNDER TEST 1A 0.1 pF ose Vy / OSC-R1 50% Vsig v Figure 1. Decoder In Sensitivity Test Figure 2. Switching Waveform yv TXEN pp OR 50% RESET. Vgg tw Figure 3. Switching Waveform MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-47GENERAL DESCRIPTION ENCODER The encoder circuit encodes the parallel binary input ad- dress/data into manchester code and outputs the information soriaily. Each transmitted word is preceded by atwo-bit dead time in- terval. Once the TXEN (transmit enable) pin is triggered by a high level, a two-word transmit sequence following a 12-bit preamble is serialiy output at the DATAOUT terminal. The transmit sequences repeat continuously if the TXEN remains high. The minimum is one complete sequence; if TXEN goes low, the transmission continues untii the end of the current transmit sequence. The data rate is set at one sighth of the system clock, which is a RC oscillator. One transmission cycle comprises: 1. 12-bit preamble 2. 2-bit dead time interval 3. First word 4, 2-bit dead time interval 5. Second word One transmitted word consists of: 1. 2 start bits 2. The address/data bits 3. 2 stop bits DECODER The decoder circuit accepts a serial manchester-coded in- put at the RXDATA pin. The data stream is then decoded and compared with the focal address set by the paralle! address in- puts. When a correct transmit sequence (two identical words) is raceived and the incoming address matches the local one, the VD output on the MC145035 goes high and the decoded data may then be read at the data outputs DO-D3 if the mode pin is high. See the mode pin discription. The valid output VD remains high unless an erroneous address/data is detected or the transmit sequence is terminated. For the MC145032 and MC145033, the valid data cutput (VD) is a toggle function. That is, VD changes state once each time a valid sequence of bits is raceived. If needed, VD can be reset to a low level via the reset pin. If the decoder detects an error in the incoming transmit se- quence, atime window is opened at the end of that sequence. Iftwo consecutive erroneous transmit sequences are received within that window, the code break output CB goes jow untilthe window's duration is over. During the opened window, the CB output can be reset by either the reset input or a correct trans- mit sequence that follows. The window duration is controlled by an external capacitor connected to pin CE. The duration of the code break output is equal to TB which is half of error win- dow time constant TE. PIN DESCRIPTIONS Vpp (Pin 28) Power supply. This pin may range from +2 to+ 6 V with re- spact to Vss. MC145031MC145032*MC145033MC145034MC145035 Vss (Pin 27) Power supply ground. TXEN (Pin 18}MC 145031, MC 145033, and MC145034 Only Transmit enable. A low to high transition on this pin initiates a transmit sequence. Transmission is continuous if TXEN re- mains high. DATA OUT (Pin 19}MC145031, MC145033, and MC145034 Only Three-state encoder output. i serially outputs the manchester-codad transmit data, when initiated by TXEN. VD (Pin 23)}MC1 45032 and MC145033 Only Decoder valid address output. This toggle output changes state whenever correct transmit sequence is received and the address matches the local one, See Figure 4. A high level on VD can be cleared by either a correct transmit sequence that follows or the reset input. VALID | | RECEIVED +] | | j SEQUENCES VD OUTPUT | | | (TOGGLE} Figure 4, Vaiid Address Output Timing (MC145032 and MC145033) VD (Pin 23}MC145035 Only Decoder valid address output. This pin goes high if and only if a correct transmit sequence is received and the address matches the lecal one. The valid output remains high unless an erroneous address/data is detected or the transmit sequence is tarminated. The minimum duration of VD is guaranteed by an external RC. See Figures 5 and 6. VALID SEQUENCES | PULSE WIDTH VD OUTPUT f aS RC (ONE SHOT) Figure 5. Valid Address Output Timing (MC145035) RESET (Pin 20}MC1 45032 and MC145033 Only A positive pulse on this pin resets the code break output CB and valid address output VD. RESET (Pin 20}MC145035 Only Apositive pulse on this pin resets the code break output CB and the valid output VD. !ts resets VD only when there is no RXDATA received. See Figura 6. CB (Pin 22}MC145032, MC145033, and MC145035 Only Decoder code-break open-drain output. It goes low if two additional consecutive erronecus transmit sequences follow- ing the 1st error have been raceived within the window set by MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-48MC145031MC145032MC145033MC145034MC145035 external capacitor Ce. While in active state, it can be cleared +V by the raset input. An external PNP transistor may be utilized to charge up the 10k CE (timing capacitor) to disable the low frequency oscillator. As a result, the TB counter stops. in this case, the CB output remains activated until a reset signal is applied to resat the CE flip flop. Sea Figures 7 and 8. 10k AO THROUGH A12 AND A13/D0 THROUGH A16/D3 cc coe 1 (Pins 1 Through 17)}MC145031, MC145032, MC145034, i and MC145035 ! I Bidirectional address/data pins. These pins form a binary ! Ltn SQ | input port during encoding. The pins become a three-state | { data output port during decoding if the moda pin is tied to Vpp. J c pO a | Pa 7 ! ~ | | ! | | | I 2 | | d ; I wt | $ 100 1 da t | I TERROR coDE at Cs! | | | DETECTOR eee | 3 CODE | Wnbow | Ce | | A | BREAK GENERATOR I | | DETECTER scumnt | = | 1B TRIGGER | CE 1 LOW FREQ. OSC. | an b---~ 4 reset | 5 ! 1 = | ne RESET | Loa J Figure 6, One Shot VD Output Circuit (MC145035) Figure 7. Code Break Window Control J * Lf a 5 1c a a = = 0 COUNTER RESET TBF RESET COUNTER C = DIVIDE-BY-128 LOW FREQ. OSCILLATOR we ERROR CODE DETECTED Tc | ist ERROR CODE 1 r DETECTED ERROR CODE SCHMITT So J) COUNTER TRIGGER COUNTER RESET pP CRG COUNTER DIVIDE-BY-256 }# ERROR WINDOW oo TE eH 3R Figure 8 Error Window TE and Code Break Window Generator TB MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-49MC145031MC145032MC145033eMC145034eMC145035 AO Through A14 (Pins 1 through 15}MC145033 Only Binary address inputs. These pins form a binary input port during the encoding sequence. These inputs become the local address during the decoding sequence. STATUS (Pin 16)}MC145033 Only Encode/Decode Status. This pin is high during the encoding sequence and low during decoding or idle. When Status is low, the DATAOUT pin is in the high-imped- ance state. RXDATA (Pin 21}-MC145032, MC145033, and MC145035 Only Serial data input to the Manchester decoder. Minimum en- coded data signal jevel is 200 mV pp. See Figure 9. RXDATA INPUT __-4 MANCHESTER DATA de DECODER EXTERNAL DATA SCHMITT AC AMPLIFIER TRIGGER COUPLING Figure 9. RXDATA Pin Coupling OSC-R2, OSC-R1, OSC-C (Pins 26, 24, and 25) Oscillator pins. The oscillator fraquency is determined by the external RC network. See Figure 10. for {5 180 kHz where R2=2R1 Tha system oscillating frequency is eight times the Encoded Data Rate. Figure 10. RC Oscillator There is only 4% change in system oscillating frequency as the supply voltage varies from 2.0 volts to 6.0 volts. The Encoder System Oscillating frequency can be varied +10% with reference to Decoder system oscillator frequency for valid detection. MODE (Pin 19}MC145032 and MC145035 Mode select input. This pin defines the A13/00-A16/D3 lines to be address or data lines. It is internally pulled high. L=Address Lines H=Data Lines Ce (Pin 18MC145032 and MC145035, Pin 17 MC145033) Error window duration control input. The built-in schmitt trig- ger oscillator frequency is controlled by external capacitor Ce. The error window TE is equal to 256 times the internal oscilla- tor cycle. If an unmatched data word (error code) is detected, an inter- nal error window TE is generated. If two or more errors are de- tected within the TE period, a code break signal CB is acti- vated, signalling that an outsider is trying to break the code of this system. (Noise cannot activate the code break output.) only one error code is detected within the window, the win- dow period is automatically extended fram the iast invalid word to check if there are two or more error codes. If so, the code break signal is activated; if not, TE is closed after a defined pe- riod. See Figures 8 and 11. TWO ERROR WORDS RX INVALID J WORD RX | 1 ERROR WINDOW ' EXTEND 1 ERROR ry 71 WINDOW ' ra CODE BREAK | | Figure 11. Error Window and Code Break Output Timing TE and TB are generated from a schmitt-trigger low frequen- cy oscillator of which the period (TC) is controlled by the timing capacitor Cg. The period of this low frequency oscillator is de- tined as TC as indicated in Figure 8. TE is generated by an 8-stage counter. TB is generated by an 7-stage counter. TE=256 TC and TB=128 TC. The relation between TC and tha timing capacitor CE is listed below with a 5.0-volt supply. Timing Capacitor Cycla Time TC 4.7 LF 1430 ms 1.0 pF 330 ms 0.1 pF 26 ms 0.047 WF 12 ms 0.022 iF 5.6 ms 0.01 pF 2.5 ms 0.0047 pF 1.0 ms 0.001 pF 0.3 ms In order to minimize faise CB triggers, one Error Code is al- lowed for every Error Window period (256 TC). Suppose Ce = 4.7 nF, TC = 1430 ms, TE = 256 TC. On an average, it takes 2 to the power of 10 trials in order to succeed in breaking the system coding. Total time taken in breaking the system coding = # of trials x TC x 256. MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITSMC145031eMC145032MC145033eMC145034MC 145035 ENCODER TXEN 5 | ENCODER DATAOUT DECODER ' LI 1ST (| 2ND | PREAMBLE I 1 lg ONE TRANSMIT SEQUENCE >4 ' 18T WORD 2ND WORD WORD WORD ! PREAMBLE | | he ONE TRANSMIT SEQUENCE RXDATA \ _"t J DECODER VD OUTPUT PREAMBLE worn I I Ls LI 1ST 2ND r I LU 1 On ND PREAMBLE = WORD WORD | WORD | t- RECEIVING DELAY Figure 12. MC145031/2/3 Encoding and Decoding Timing Diagram ENCODER TXEN 8 L ENCODER DATAOUT PREAMBLE ST ND ' a WORD WORD ba ONE TRANSMIT SEQUENCE ~ J ' ' AXDATA % * ist | PREAMBLE woRD WORD DECODER VO OUTPUT (CASE 1) 1 Me TAT) DECODER VD OUTPUT (CASE 2) -tor, Te Ti! f] DECODER RESET (IF INPUT WITHIN T1) (CASE 2) t: RECEIVING DELAY Tt: INTERVAL DETERMINED BY EXTERNAL RC PER FIGURE 6 Figure 13. MC145034/5 Encoding and Decoding Timing Diagram Single Transmission MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-51MC145031MC145032eMC145033eMC145034MC145035 Yoo 13 ADDRESSES ENCODER TXEN ENCODER | | DATAOUT a a 1 al! ol all el 18T PREAMBLE WORD WORD WORD WORD gL WORD WORD i DECODER t RXDATA =| | | ll | | _ ist Hann HE ist Ub ano LF ist LU ono L- woRD WORD PREAMBLE WORD WORD wens WORD WORD aa DECODER VD OUTPUT t: RECEIVING DELAY Figure 14. MC145034/5 Encoding and Decoding Timing Diagram Continuous Transmissions TRANSMIT 18 28 TXEN Voo DATAOUT wlrloalt~ |] mw] om] el wotnme = a ee ee mini -| co FOR DATA RATE = 500 BAUD OSC. FREQ = 4 kHz Ri =10kO R2 = 22kQ C=0.01 pF Figure 15. Typical Application 001 HF == 2i 19 V+ ol ee" 28 20 = wolaol~al, mi, wy] wo] rm Yoo 13 ADDRESSES MOTOROLA CMOS APPLICATION-SPECIFIC DIGITAL-ANALOG INTEGRATED CIRCUITS 6-52