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SLLS025A − JULY 1986
Copyright 1986, Texas Instruments Incorporated
Revision Information
3−1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
•Dual Circuits Capable of Driving
High-Capacitance Loads at High Speeds
•Output Supply Voltage Range up to 24 V
•Low Standby Power Dissipation
description
The SN75372 is a dual NAND gate interface
circuit designed to drive power MOSFETs from
TTL inputs. It provides high current and voltage
levels necessary to drive large capacitive loads at
high speeds. The device operates from a VCC1 of
5 V and a VCC2 of up to 24 V.
The SN75372 is characterized for operation from
0°C to 70°C.
schematic (each driver)
V
CC1
V
CC2
To Other
Driver
To Other
Driver
Output Y
GND
Input A
Enable E
1Y
7
2Y
6
E2EN
1A 1
2A 3
logic symbol†
TTL/MOS
1
2
3
4
8
7
6
5
1A
E
2A
GND
VCC1
1Y
2Y
VCC2
D OR P PACKAGE
(TOP VIEW)
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
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
SLLS025A − JULY 1986
3−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC1 (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VCC2 −0.5 V to 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current, VO (tw < 10 ms, duty cycle < 50%) 500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to network GND.
DISSIPATION RATING TABLE
PACKAGE
TA = 25
°
C
DERATING FACTOR
TA = 70
°
C
PACKAGE
TA = 25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70 C
POWER RATING
D 725 mW 5.8 mW/°C464 mW
P1000 mW 8.0 mW/°C640 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC1 4.75 5 5.25 V
Supply voltage, VCC2 4.75 20 24 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
High-level output current, IOH −10 mA
Low-level output current, IOL 40 mA
Operating free-air temperature, TA0 70 °C
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SLLS025A − JULY 1986
3−3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of VCC1, VCC2, and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = −12 mA −1.5 V
VOH
High-level output voltage
VIL = 0.8 V, IOH = −50 µA VCC2−1.3 VCC2−0.8
V
VOH High-level output voltage VIL = 0.8 V, IOH = −10 mA VCC2−2.5 VCC2−1.8 V
VIH = 2 V, IOL = 10 mA 0.15 0.3
VOL Low-level output voltage VCC2 = 15 V to 24 V,
IOL = 40 mA VIH = 2 V, 0.25 0.5 V
VF
Output clamp-diode forward voltage
IF = 20 mA
1.5
V
V
F
Output clamp-diode forward voltage V
= 0, I
F
= 20 mA 1.5 V
II
Input current at maximum input
1
mA
II
Input current at maximum input
voltage VI = 5.5 V 1mA
IIH
High-level input current
Any A
40
A
IIH High-level input current Any E VI = 2.4 V 80 µA
IIL
Low-level input current
Any A
−1 −1.6
mA
IIL Low-level input current Any E VI = 0.4 V −2 −3.2 mA
ICC1(H) Supply current from VCC1, both
outputs high
VCC2 = 24 V,
2 4 mA
ICC2(H) Supply current from VCC2, both
outputs high
All inputs at 0 V,
VCC2 = 24 V,
No load 0.5 mA
ICC1(L) Supply current from VCC1, both
outputs low
VCC2 = 24 V,
16 24 mA
ICC2(L) Supply current from VCC2, both
outputs low
All inputs at 5 V,
VCC2 = 24 V,
No load 7 13 mA
ICC2(S) Supply current from VCC2, standby
condition VCC1 = 0,
All inputs at 5 V, VCC2 = 24 V,
No load 0.5 mA
†All typical values are at VCC1 = 5 V, VCC2 = 20 V, and TA = 25°C.
switching characteristics, VCC1 = 5 V, VCC2 = 20 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDLH Delay time, low-to-high-level output 20 35 ns
tDHL Delay time, high-to-low-level output 10 20 ns
tTLH Transition time, low-to-high-level output
CL = 390 pF,
RD = 10 Ω,
See Figure 1
20 30 ns
tTHL Transition time, high-to-low-level output
C
L
= 390 pF,
R
D
= 10
Ω
,
See Figure 1
20 30 ns
tPLH Propagation delay time, low-to-high-level output 10 40 65 ns
tPHL Propagation delay time, high-to-low-level output 10 30 50 ns
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SLLS025A − JULY 1986
3−4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
10%
5 V
2.4 V
VCC1
TEST CIRCUIT
Input
GND
VCC2
Pulse
Generator
(see Note A) Output
CL = 390 pF
(see Note B)
20 V
RD
Input
Output
VOLTAGE WAVEFORMS
≤
10 ns
90%
1.5 V 0.5 µs
tDHL tTLH
VCC2−3
V
2 V
0 V
VOH
≤
10 ns
90%
1.5 V 10%
tPHL tPHL
tDLH
tTHL
VCC2−3 V 2 V VOL
3 V
NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω.
B. CL includes probe and jig capacitance.
Figure 1. Test Circuit and Voltage Waveforms, Each Driver
TYPICAL CHARACTERISTICS
−1
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
−10 −100
0.3
0.2
0.1
00204060
0.4
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.5
80 100
VCC2−0.5
VCC2−1
VCC2−1.5
VCC2−2
VCC2−2.5
VCC2−3
VCC1 = 5 V
VCC2 = 20 V
VI = 0.8 V
TA = 25°C
TA = 70°C
TA = 0°C
V0H − High-Level Output Voltage − V
VOH
I
OL
− Low-Level Output Current − mA
VCC1 = 5 V
VCC2 = 20 V
VI = 2 V
TA = 70°C
TA = 0°C
VOL − Low-Level Output Voltage − V
VOL
I
OH
− High-Level Output Current − mA
VCC2
− 0.01 − 0.1
Figure 2 Figure 3
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SLLS025A − JULY 1986
3−5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
10 20 40 100 400 1000
f − Frequency − kHz
POWER DISSIPATION (BOTH DRIVERS)
vs
FREQUENCY
200
400
200
0
800
1000
1200
600
12
8
4
00 0.5 1 1.5
16
20
VOLTAGE TRANSFER CHARACTERISTICS
24
2 2.5
V
I
− Input Voltage − V
V) − Output Voltage − V
VO
VCC1 = 5 V
VCC2 = 20 V
No Load
TA = 25°C
VCC1 = 5 V
VCC2 = 20 V
Input: 3-V Square Wave
50% Duty Cycle
TA = 25°C
CL = 600 pF
CL = 1000 pF
CL = 2000 pF
CL = 4000 pF
CL = 400 pF
PT − Power Dissipation − mWPD
Allowable in P Package Only
Figure 4 Figure 5
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
FREE-AIR TEMPERATURE
100
80
20
00 102030405060
High-to-Low-Level Output − ns
140
180
200
70 80
60
160
120
40
TA − Free-Air Temperature − °C
kSVR − Propagation Delay Time,
tPLH
Low-to-High-Level Output − ns
kSVR − Propagation Delay Time,
tPHL
T
A
− Free-Air Temperature − °C
100
80
20
0
140
180
200
60
160
120
40
0 1020304050607080
CL = 50 pF
CL = 200 pF
CL = 1000 pF
CL = 2000 pF
CL = 4000 pF
VCC1 = 5 V
VCC2 = 20 V
RD = 10 Ω
See Figure 1
CL = 4000 pF
CL = 2000 pF
CL = 1000 pF
VCC1 = 5 V
VCC2 = 20 V
RD = 10 Ω
See Figure 1
CL = 200 pF CL = 390 pF
CL = 50 pF
CL = 390 pF
Figure 6 Figure 7
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SLLS025A − JULY 1986
3−6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
0 5 10 15
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
20 25
100
80
20
0
140
180
200
60
160
120
40
Low-to-High-Level Output − ns
V
CC2
− Supply Voltage − V
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
VCC2 SUPPLY VOLTAGE
100
80
20
0
140
180
200
60
160
120
40
0 5 10 15 20 2
5
V
CC2
− Supply Voltage − V
− Propagation Delay Time,
tPLH
VCC1 = 5 V
RD = 10 Ω
TA = 25°C
See Figure 1
CL = 2000 pF
CL = 1000 pF
CL = 200 pF CL = 390 pF
CL = 50 pF
VCC1 = 5 V
RD = 10 Ω
TA = 25°C
See Figure 1 CL = 4000 pF
CL = 2000 pF
CL = 1000 pF
CL = 390 pF
CL = 200 pF
CL = 50 pF
CL = 4000 pF
High-to-Low-Level Output − ns
− Propagation Delay Time,
tPLH
Figure 8 Figure 9
0 1000 2000 3000 4000
VCC1 = 5 V
VCC2 = 20 V
TA = 25°C
See Figure 1
Low-to-High-Level Output − ns
100
80
20
0
140
180
200
60
160
120
40
PROPAGATION DELAY TIME,
LOW-TO-HIGH-LEVEL OUTPUT
vs
LOAD CAPACITANCE
C
L
− Load Capacitance − pF
RD = 10 Ω
RD = 0
RD = 24 Ω
100
80
20
0
140
180
200
60
160
120
40
0 1000 2000 3000 400
0
C
L
− Load Capacitance − pF
VCC1 = 5 V
VCC2 = 20 V
TA = 25°C
See Figure 1
RD = 24 Ω
RD = 10 Ω
PROPAGATION DELAY TIME,
HIGH-TO-LOW-LEVEL OUTPUT
vs
LOAD CAPACITANCE
RD = 0
kSVR − Propagation Delay Time,
tPLH
High-to-Low-Level Output − ns
kSVR − Propagation Delay Time,
tPLH
Figure 10 Figure 11
NOTE: For RD = 0, operation with CL > 2000 pF violates absolute maximum current rating.
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SLLS025A − JULY 1986
3−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
THERMAL INFORMATION
power dissipation precautions
Significant power may be dissipated in the SN75372 driver when charging and discharging high-capacitance
loads over a wide voltage range at high frequencies. Figure 5 shows the power dissipated in a typical SN75372
as a function of load capacitance and frequency. Average power dissipated by this driver is derived from the
equation
PT(AV) = PDC(AV) + PC(AV) = PS(AV)
where P DC(AV) is the steady-state power dissipation with the output high or low, P C(AV) is the power level during
charging or discharging of the load capacitance, and PS(AV) is the power dissipation during switching between
the low and high levels. None of these include energy transferred to the load, and all are averaged over a full
cycle.
The power components per driver channel are
PC(AV) [CV
2
Cf
t
HL tLH
tH
tL
T = 1/f
Figure 12. Output Voltage Waveformwhere the times are as defined in Figure 14.
PDC(AV) = PHtH + PLtL
T
PS(AV) = PLHtLH + PHLtHL
T
PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, C is the load capacitance.
VC is the voltage across the load capacitance during the charge cycle shown by the equation
VC = VOH − VOL
PS(AV) may be ignored for power calculations at low frequencies.
In the following power calculation, both channels are operating under identical conditions:
VOH =19.2 V and VOL = 0.15 V with VCC1 = 5 V, VCC2 = 20 V, VC = 19.05 V, C = 1000 pF, and the
duty cycle = 60%. At 0.5 MHz, PS(AV) is negligible and can be ignored. When the output voltage is high, ICC2
is negligible and can be ignored.
On a per-channel basis using data sheet values,
PDC(AV) +ƪ(5 V) ǒ2mA
2Ǔ)(20 V) ǒ0mA
2Ǔƫ(0.6) )ƪ(5 V) ǒ16 mA
2Ǔ)(20 V) ǒ7mA
2Ǔƫ(0.4)
PDC(AV) = 47 mW per channel
Power during the charging time of the load capacitance is
PC(AV) = (1000 pF) (19.05 V)2 (0.5 MHz) = 182 mW per channel
Total power for each driver is
PT(AV) = 47 mW + 182 mW = 229 mW
and total package power is
PT(AV) = (229) (2) = 458 mW.
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SLLS025A − JULY 1986
3−8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
driving power MOSFETs
The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The
input impedance of a FET consists of a reverse biased PN junction that can be described as a large capacitance
in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup
resistor is not satisfactory for high-speed applications. In Figure 12(a), an IRF151 power MOSFET switching
an inductive load is driven by an open-collector transistor driver with a 470-Ω pullup resistor. The input
capacitance (C iss) specification for an IRF151 is 4000 pF maximum. The resulting long turn-on time due to the
combination of Ciss and the pullup resistor is shown in Figure 12(b).
5 V
748
3
5
1
2
6
V0H − VOL − Gate Voltage − V
VOH
TLC555P
1/2 SN75447
470 Ω
48 V
M
VOL
t − Time − µs
(b)
(a)
IRF151
4
3
2
1
00 0.5 1 1.5 2 2.5
3
Figure 13. Power MOSFET Drive Using SN75447
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SLLS025A − JULY 1986
3−9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
A faster, more efficient drive circuit uses an active pullup as well as an active pulldown output configuration,
referred to as a totem-pole output. The SN75372 driver provides the high speed, totem-pole drive desired in
an application of this type, see Figure 13(a). The resulting faster switching speeds are shown in Figure 13(b).
5 V
TLC555P
1/2 SN75372
M
t − Time − µs
(b)
(a)
IRF151
48 V
4
3
2
1
00 0.5 1 1.5 2 2.5 3
V0H − VOL − Gate Voltage − V
VOH VOL
748
3
5
12
6
Figure 14. Power MOSFET Drive Using SN75372
Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as
shown by the equation
Ipk +VC
tr
where C is the capacitive load, and tr is the desired drive time. V is the voltage that the capacitance is charged
to. In the circuit shown in Figure 13(a), V is found by the equation
V = VOH − VOL
Peak current required to maintain a rise time of 100 ns in the circuit of Figure 13(a) is
IPK +(3 *0)4(10*9)
100(10*9)+120 mA
Circuit capacitance can be ignored because it is very small compared to the input capacitance of the IRF151.
With a VCC of 5 V, and assuming worst-cast conditions, the gate drive voltage is 3 V.
For applications in which the full voltage of VCC2 must be supplied to the MOSFET gate, the SN75374 quad
MOSFET driver should be used.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN75372D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372DRE4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN75372P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
SN75372PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor
or Sales Office
SN75372PSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372PSRE4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN75372PSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Jun-2010
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75372DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75372PSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75372DR SOIC D 8 2500 340.5 338.1 20.6
SN75372PSR SO PS 8 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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