Preliminary Product Information MOS Integrated Circuit 78K0/KB2 8-BIT SINGLE-CHIP MICROCONTROLLER The 78K0/KB2 products are 8-bit single-chip microcontrollers of the 78K0 series. These microcontrollers feature Single-voltage Self-programming Flash memory and many peripherals. FEATURES * 78K0 CPU core, 8-bit CISC architecture * Flash EEPROM and RAM sizes Item Program memory Data memory (Flash ROM) (RAM) Product name PD78F0503 32K bytes (Flash) 1K bytes PD78F0502 24K bytes (Flash) 1K bytes PD78F0501 16K bytes (Flash) 768 bytes PD78F0500 8K bytes (Flash) 512 byte Minimum instruction cycle 0.1s (20MHz@4.0V to 5.5V) 0.2s (10MHz@2.7V to 5.5V) * AD CONVERTER - 10-bit resolution A/D converter 4 ch * I/O PORT 0.4s ( 5MHz@1.8V to 5.5V) Total : 23 Clock CMOS I/O : 21 * MAIN CLOCK - Internal High-speed-oscillator 8MHz (Typ.) - Ceramic/Crystal Oscillator/External CLK (1MHz to 20MHz) (Instruction execution time = 100ns(min.) @20MHz) * WDT CLOCK - Internal Low-speed-oscillator 240KHz (Typ.) Peripherals. * On-Chip Power-On-Clear (POC) Circuit * Low-Voltage Detector (LVI) Circuit * Timer - 16bit Timer 1ch N-ch O.D I/O: 2 * Other - Self programming - On-chip debug function (PD78F0503D only) Interrupt - Internal 16ch - External 6ch Operation Voltage 1.8V to 5.5V Package 30-pin SSOP (7.62mm(300)) - 8bit Timer 4ch - Watchdog Timer (Operable with 240KHz Internal-Low-speed -oscillator) * Serial Interface - UART/CSI 1ch - UART (with LIN-bus) 1ch - IIC 1ch This information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion,, may withdraw the product prior to its production. Not all products and/ or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. ZUD-CC-04-0125-E Data Published Oct 2004 N CP(K) (c)NEC Electronics Corporation 2004 78K0/KB2 1. Block Diagram Fig. 78K0/KB2 Port0 P00 -P01 Port1 P10 -P17 8bit Timer (TMH0) Port2 P20 -P23 TOH1 8bit Timer (TMH1) Port3 P30 -P33 TO50 TI50 8bit Timer (TM50) Port6 P60 -P61 TO51 TI51 8bit Timer (TM51) Port12 P120 -P122 SCL0 SDA0 Multi master IIC (IIC0) RxD6 TxD6 UART-LIN (UART6) RxD0 TxD0 UART (UART0) TI000 TI010 TO00 TOH0 SI10 SO10 SCK10 16bit Timer (TM00) 3wire Serial I/F (CSI10) 78K0 CPU CORE RAM Flash EEPROM Watchdog Timer Reset CTL RESET ANI0 ANI3 AVREF AVSS 10bit AD converter Power On Clear (POC) FLMD0 System Control REGC VDD VSS EXLVI INTP0 INTP5 Low voltage Indicator (LVI) External Interrupt ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) Internal High-speed -oscillator (8MHz typ.) High-speed system clock OSC X1 X2/ EXCLK Internal Low-speed -oscillator (240kHz typ.) (c)NEC Electronics Corporation 2004 78K0/KB2 2. Pin Lay Out 78K0/KB2 30-pin plastic SSOP (7.62mm(300)) PD78F0500MC-5A4, PD78F0501MC-5A4 PD78F0502MC-5A4, PD78F0503MC-5A4 P21/ANI1 P20/ANI0 P01/TI010/TO00 P00/TI000 P120/INTP0/EXLVI RESET IC/FLMD0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCL0 P61/SDA0 P33/TI51/TO51/INTP4 ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30pin SSOP 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P22/ANI2 P23/ANI3 AVSS AVREF P10/SCK10/TXD0 P11/SI10/RXD0 P12/SO10 P13/TXD6 P14/RXD6 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P31/INTP2 P32/INTP3 (c)NEC Electronics Corporation 2004 78K0/KB2 3. Pin Function Table (1/2) PIN NAME Function VDD VSS RESET FLMD0 REGC P11 /SI10 /RXD0 P12 /SO10 P13 /TXD6 Positive power supply except for ports (except P20-P23) and AD converter Ground potential except for ports (except P20-P23) and AD converter System reset input Flash EEPROM programming mode setting Connecting regulator output stabilization capacitor. Connect to GND via a capacitor (0.47F) A/D converter analog power supply and power supply for P20-P23 Ground potential for A/D converter and P20 - P23. I/O port External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of16-bit timer/event counter 00 (TM00) I/O port Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 (TM00) 16-bit timer/event counter 00 output (TM00) I/O port Clock input/ output for serial interface (CSI10) Serial data output from asynchronous serial interface (UART0) I/O port Serial data input to serial interface (CSI10) Serial data input to asynchronous serial interface (UART0) I/O port Serial data output form serial interface (CSI10) I/O port Serial data output from asynchronous serial interface (UART6) P14 /RXD6 P15 /TOH0 P16 /TOH1 /INTP5 P17 /TI50 /TO50 I/O port Serial data input to asynchronous serial interface (UART6) I/O port 8-bit timer H0 output (TMH0) I/O port 8-bit timer H1 output (TMH1) External interrupt request input with specifiable valid edges I/O port External count clock input to 8-bit timer/event counter 50 (TM50) 8-bit timer/event counter 50 output (TM50) AVREF AVSS P00 /TI000 P01 /TI010 /TO00 P10 /SCK10 /TXD0 ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) (c)NEC Electronics Corporation 2004 78K0/KB2 Table(2/2) PIN NAME Function P20- P23 / ANI0- ANI3 P30/INTP1 P31/INTP2 P32/INTP3 P33 /TI51 /TO51 /INTP4 P60 /SCL0 P61 /SDA0 P120 /INTP0 /EXLVI P121 /X1 P122 /X2 /EXCLK I/O ports A/D converter analog input I/O port External interrupt request input with specifiable valid edges ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) I/O port External count clock input to 8-bit timer/event counter 51(TM51) 8-bit timer/event counter 51output (TM51) External interrupt request input with specifiable valid edges I/O port (N-ch Open drain) Clock input/ output for serial interface (IIC0) I/O port (N-ch Open drain) Serial data input/ output for serial interface (IIC0) I/O port External interrupt request input with specifiable valid edges Reference voltage input for Low voltage Indicator I/O port (An external oscillation circuit is not used) Connecting resonator for main system clock oscillation I/O port (An external oscillation circuit is not used) Connecting resonator for main system clock oscillation External clock input for main system clock (c)NEC Electronics Corporation 2004 78K0/KB2 4. Memory space 78K0/KB2 have 64kB linear address area. Common ROM Products ROM size PD78F0503 32KB PD78F0502 24KB PD78F0501 16KB PD78F0500 8KB Address Bank ROM Address Number of Bank - - - - - - - - 0000H-7FFFH (32KB) 0000H-5FFFH (24KB) 0000H-3FFFH (16KB) 0000H-1FFFH (8KB) 5. Clock 78K0/KB2 have 2 type internal oscillator and 2 type external resonator oscillation circuit. 78K0/KB2 can be operated Internal High-speed oscillator only. Internal Low-speed oscillator can connect to Watch dog timer and 8bit timer (TMH1) only for high secure. Fig. Clock connecting block image Internal Low-speed oscillator (240kHz typ) Watchdog timer 8bit timer (TMH1) Internal High-speed Oscillator (8MHz typ) MPX External resonator or External clock ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) High-speed system clock oscillation circuit (1-20MHz) MPX CPU Peripheral (c)NEC Electronics Corporation 2004 78K0/KB2 6. Outline of Functions of KB2 Internal Memory (Byte) PD78F0500 PD78F0501 PD78F0502 PD78F0503 8K 16K 24K 32 K - - - 512 768 Flash Memory Bank High Speed RAM 1K Extend RAM Main System Ceramic/Crystal Clock Internal oscillator - 1 to 20 MHz: VDD = 4.0 to 5.5 V - 1 to 10 MHz: VDD = 2.7 to 5.5 V - 1 to 5 MHz: VDD = 1.8 to 5.5 V - 8 MHz(TYP.) Sub System Clock - Internal Low Speed oscillator (For TMH1, WDT) - 240 kHz(TYP.) Minimum Instruction Cycle - 0.1 s I/O Total - CMOS I/O - N-ch O.D. Timer - 16 Bit Timer/Event Counter:1ch - 8 Bit Timer/Event Counter:2ch - 8 bit Timer:2ch - Watch Dog Timer:1ch Timer Output (Ceramic/ Crystal Operation fXH = 20 MHz VDD = 4.0 to 5.5 V) :23 :21 :2 -5(PWM:3) PCL output - Buzzer Output - A/D Converter - 10bit x 4ch Serial Interface - UART (with LIN-bus):1ch - CSI/ UART:1ch 2 - I C:1ch Multiplier/Divider Interrupt - Internal 16 External 6 Key Return - On Chip Debug Function Product name undecided Voltage Range VDD = 1.8 to 5.5 V Operation temperature Ta = -40C to +85C Package - 30pin SSOP(7.62mm(300)) ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) (c)NEC Electronics Corporation 2004 78K0/KB2 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) (c)NEC Electronics Corporation 2004 78K0/KB2 Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. * The information contained in this document is being issued in advance of the production cycle for the product. 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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5 02. 11-1 ZUD-CA-05-0060 Data Published Oct 2004 N CP(K) (c)NEC Electronics Corporation 2004