78K0/KB2
MOS Integrated Circuit
Preliminary Product Information
8-BIT SINGLE-CHIP MICROCONTROLLER
©NEC Electronics Corporation 2004
The 78K0/KB2 products are 8-bit singl e-chip microcontrollers of the 78K0 series.
These microcontrollers feature Sing le-voltage Self-programming Flash memory and many peripherals.
FEATURES
• 78K0 CPU core, 8-bit CISC architecture
• Flash EEPROM and RAM sizes
Item
Product name
Program memory
(Flash ROM)
Data memory
(RAM)
µ
PD78F0503 32K bytes (Flash) 1K bytes
µ
PD78F0502 24K bytes (Flash) 1K bytes
µ
PD78F0501 16K bytes (Flash) 768 bytes
µ
PD78F0500 8K bytes (Flash) 512 byte
Minimum instruction cycle
0.1
µ
s (20MHz@4.0V to 5.5V)
0.2
µ
s (10MHz@2.7V to 5.5V)
0.4
µ
s ( 5MHz@1.8V to 5.5V)
Clock
• MAIN CLOCK
- Internal High-speed-oscillator 8MHz (Typ.)
- Ceramic/Crystal Oscillator/External CLK (1MHz to 20MHz)
(Instruction execution time = 100ns(min.) @20MHz)
• WDT CLOCK
- Internal Low-speed-oscillator 240KHz (Typ.)
Peripherals.
• On-Chip Power-On-Clear (POC) Circuit
• Low-Voltage Detector (LVI) Circuit
• Timer
- 16bit Timer 1ch
- 8bit Timer 4ch
- Watchdog Timer (Operable with 240KHz Internal-Low-speed
-oscillator)
• Serial Interface
- UART/CSI 1ch
- UART (with LIN-bus) 1ch
- IIC 1ch
• AD CONVERTER
- 10-bit resolution A/D converter 4 ch
• I/O PORT
Total : 23
CMOS I/O : 21
N-ch O.D I/O: 2
• Other
- Self programming
- On-chip debug function (
µ
PD78F0503D only)
Interrupt
- Internal 16ch
- External 6ch
Operation Voltage
1.8V to 5.5V
Package
30-pin SSOP (7.62mm(300))
This information contained in this document is being issued in advance of the production cycle for the product. The
parameters for the product ma y change before final production or NEC Electronics Corporation, at its own discretion,,
may withdraw the produc t prior to its production. Not all prod ucts and/ or types are available in every countr y. Please
check with an NEC Electronics sales representative for availability and additional information.
ZUD-CC-04-0125-E
Data Published Oct 2004 N CP(K)
78K0/KB2
1. Block Diagram
Fig. 78K0/KB2
ANI0 -
ANI3
AVSS
AVREF 10bit AD
converter
SCK10
SI10
SO10 3wire
Serial I/F
(CSI10)
External
Interru
p
t
INTP0 -
INTP5
EXLVI Low voltage
Indicator
(
LVI
)
SCL0
SDA0 Multi master
IIC
(IIC0)
TxD0
RxD0 UART
(UART0)
TI51
TO51 8bit T imer
(TM51)
TI50
TO50 8bit T imer
(TM50)
RESET
Reset CTL
System
Control
FLMD0
REGC
VDD
VSS
Internal High-speed
-oscillator
(
8MHz t
yp
.
)
Power On
Clear
(POC)
High-speed system
clock OSC X1
Watchdog
Timer
16bit T imer
(TM00)
TO00
TI000
TI010
8bit T imer
(TMH0)
TOH0
8bit T imer
(TMH1)
TOH1
78K0
CPU CORE
RAM Flash
EEPROM
Port12
Port6
Port3
Port2
Port1
Port0
TxD6
RxD6 UART-LIN
(UART6)
P00 -P01
P10 -P17
P20 -P23
P30 -P33
P60 -P61
P120 -P122
X2/ EXCLK
Internal Low-speed
-oscillator
(
240kHz t
yp
.
)
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
2. Pin Lay Out
78K0/KB2
30-pin plastic SSOP (7.62mm(300))
µ
PD78F0500MC-5A4,
µ
PD78F0501MC-5A4
µ
PD78F0502MC-5A4,
µ
PD78F0503MC-5A4
30pinSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P21
/
ANI1
P20
/
ANI
0
P01
/
TI010
/
TO0
0
P00
/
TI00
0
P120
/
INTP0
/
EXLVI
RESE
IC
/
FLMD
0
P122
/
X2
/
EXCL
P121
/
X1
REG
C
VS
S
VS
S
VD
D
VD
D
P60
/
SCL
0
P61
/
SDA
0
P33
/
TI51
/
TO51
/
INTP
4
P32
/
INTP3
P31
/
INTP2
P30
/
INTP1
P17
/
TI50
/
TO5
0
P16
/
TOH1
/
INTP5
P15
/
TOH
0
P14
/
RXD6
P13
/
TXD6
P12
/
SO1
0
P11
/
SI10
/
RXD
0
P10
/
SCK10
/
TXD
0
AVRE
AVS
S
P23
/
ANI3
P22
/
ANI2
30pinSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P21
/
ANI1
P20
/
ANI
0
P01
/
TI010
/
TO0
0
P00
/
TI00
0
P120
/
INTP0
/
EXLVI
RESE
IC
/
FLMD
0
P122
/
X2
/
EXCL
P121
/
X1
REG
C
VS
S
VS
S
VD
D
VD
D
P60
/
SCL
0
P61
/
SDA
0
P33
/
TI51
/
TO51
/
INTP
4
P32
/
INTP3
P31
/
INTP2
P30
/
INTP1
P17
/
TI50
/
TO5
0
P16
/
TOH1
/
INTP5
P15
/
TOH
0
P14
/
RXD6
P13
/
TXD6
P12
/
SO1
0
P11
/
SI10
/
RXD
0
P10
/
SCK10
/
TXD
0
AVRE
AVS
S
P23
/
ANI3
P22
/
ANI2
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
3. Pin Function Table (1/2)
PIN NAME Function
VDD Positive power supply except for ports (except P20-P23) and AD converter
VSS Ground potential except for ports (except P20-P23) and AD converter
RESET System reset input
FLMD0 Flash EEPROM programming mode setting
REGC Connecting regulator output stabilization capacitor. Connect to GND via a
capacitor (0.47
µ
F)
AVREF A/D converter analog power supply and power supply for P20-P2 3
AVSS Ground potential for A/D converter and P20 - P23.
I/O port P00
/TI000 External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR 000, CR010) of16-bit
timer/event counter 00 (TM00)
I/O port
Capture trigger input to capture register (CR000) of 16-bittimer/event
counter 00 (TM00)
P01
/TI010
/TO00 16-bit timer/event counter 00 output (TM00)
I/O port
Clock input/ output for serial interface (CSI10)
P10
/SCK10
/TXD0 Serial data output from asynchronous serial interface (UART0)
I/O port
Serial data input to serial interface (CSI10)
P11
/SI10
/RXD0 Serial data input to asynchronous serial interface (UART0)
I/O port P12
/SO10 Serial data output form serial interface (CSI10)
I/O port P13
/TXD6 Serial data output from asynchronous serial interface (UART6)
I/O port P14
/RXD6 Serial data input to asynchronous serial interface (UART6)
I/O port P15
/TOH0 8-bit timer H0 output (TMH0)
I/O port
8-bit timer H1 output (TMH1)
P16
/TOH1
/INTP5 External interrupt request input with specifiable valid edges
I/O port
External count clock input to 8-bit timer/event counter 50 (TM50)
P17
/TI50
/TO50 8-bit timer/event counter 50 output (TM50)
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
Table(2/2)
PIN NAME Function
P20- P23
/ ANI0- ANI3 I/O ports
A/D converter analog input
P30/INTP1
P31/INTP2
P32/INTP3
I/O port
External interrupt request input with specifiable valid edges
I/O port
External count clock input to 8-bit timer/event counter 51(TM51)
8-bit timer/event counter 51output (TM51)
P33
/TI51
/TO51
/INTP4 External interrupt request input with specifiable valid edges
I/O port (N-ch Open drain) P60
/SCL0 Clock input/ output for serial interface (IIC0)
I/O port (N-ch Open drain) P61
/SDA0 Serial data input/ output for serial interface (IIC0)
I/O port
External interrupt request input with specifiable valid edges
P120
/INTP0
/EXLVI Reference voltage input for Lo w voltage Indicator
I/O port (An external oscillation circuit is not used) P121
/X1 Connecting resonator for main system clock oscillation
I/O port (An external oscillation circuit is not used)
Connecting resonator for main system clock oscillation
P122
/X2
/EXCLK External clock input for main system clock
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
4. Memory space
78K0/KB2 have 64kB linear address area.
Common ROM Bank ROM
Products ROM size Address Address
Number of
Bank
µ
PD78F0503 32KB 0000H-7FFFH
(32KB) - -
µ
PD78F0502 24KB 0000H-5FFFH
(24KB) - -
µ
PD78F0501 16KB 0000H-3FFFH
(16KB) - -
µ
PD78F0500 8KB 0000H-1FFFH
(8KB) - -
5. Clock
78K0/KB2 have 2 type internal oscillator and 2 type external reso nator oscillation circuit.
78K0/KB2 can be operated Internal High-speed oscillator only. Internal Low-speed oscillator can
connect to Watch dog timer and 8 bit timer (TMH1) only for high secure.
Fig. Clock connecting block image
Internal
High-speed
Oscillator
(
8MHz t
yp)
High-speed
system clock
oscillation circuit
(1-20MHz)
Watchdog timer
CPU
Peripheral
Internal
Low-speed
oscillator
(240kHz typ) 8bit timer (TMH1)
MPX
MPX
External resonator
or
External clock
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
6. Outline of Functions of KB2
µ
PD78F0500
µ
PD78F0501
µ
PD78F0502
µ
PD78F0503
Flash Memory 8 K 16K 24K 32 K
Bank - - - -
Internal
Memory
(Byte) High Speed RAM 512 768 1K
Extend RAM -
Ceramic/Crystal - 1 to 20 MHz: VDD = 4.0 to 5.5 V
- 1 to 10 MHz: VDD = 2.7 to 5.5 V
- 1 to 5 MHz: VDD = 1.8 to 5.5 V
Main System
Clock
Internal oscillator - 8 MHz(TYP.)
Sub System Clock -
Internal Low Speed oscillator
(For TMH1, WDT) - 240 kHz(TYP.)
Minimum Instruction Cycle - 0.1
µ
s (Ceramic/ Crystal Operation fXH = 20 MHz VDD = 4.0 to 5.5 V)
I/O Total :23
- CMOS I/O :21
- N-ch O.D. :2
Timer - 16 Bit Timer/Event Counter:1ch
- 8 Bit Timer/Event Counter:2ch
- 8 bit Timer:2ch
- Watch Dog Timer:1ch
Timer Output -5(PWM:3)
PCL output -
Buzzer Output -
A/D Converter - 10bit x 4ch
Serial Interface - UART (with LIN-bus):1ch
- CSI/ UART:1ch
- I2C:1ch
Multiplier/Divider -
Internal 16 Interrupt External 6
Key Return -
On Chip Debug Function Product name undecided
Voltage Range VDD = 1.8 to 5.5 V
Operation temperature Ta = -40°C to +85°C
Package - 30pin SSOP(7.62mm(300))
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distor tion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
Windows and Window s NT are either r egistered t radem arks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a tra demark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several
countries includin
g
the United States and Ja
p
an.
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)
78K0/KB2
Caution: This
p
roduct uses Su
p
erFlash®technolo
gy
licensed from Silicon Stora
g
e Technolo
gy,
Inc.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics products before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M5 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
©NEC Electronics Corporation 2004
ZUD-CA-05-0060
Data Published Oct 2004 N CP(K)