Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ Max Units Conditions
CIN 58pFV
IN = 0 V
COUT 68pFV
OUT = 0 V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The registers in the AT22V10 and AT22V10L are designed to
reset during power up. At a point delayed slightly from VCC
crossing 3.8 V, all registers will be reset to the low state. The
output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the uncer-
tainty of how VCC actually rises in the system, the following
conditions are required:
1) The VCC rise must be monotonic,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and
3) The clock must remain stable during tPR.Parameter Description Min Typ Max Units
tPR Power-Up
Reset Time 600 1000 ns
CLOCK
3.8 V
POWER
REGISTERED
OUTPUTS tS
tPR
tW
Erasure Characteristics
The entire fuse array of an AT22V10 or AT22V10L is erased
after exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 minutes
exposure using 12,000 µW/cm2 intensity lamps spaced one
inch away from the chip. Minimum erase time for lamps at
other intensity ratings can be calculated from the minimum
integrated erasure dose of 15 W•sec/cm2. To prevent unin-
tentional erasure, an opaque label is recommended to cover
the clear window on any UV erasable PLD which will be sub-
jected to continuous fluorescent indoor lighting or sunlight.
Preload of Registered Outputs
The registers in the AT22V10 and AT22V10L are provided
with circuitry to allow loading of each register asynchro-
nously with either a high or a low. This feature will simplify
testing since any state can be forced into the registers to con-
trol test sequencing. A VIH level on the I/O pin will force the
register high; a VIL will force it low, independent of the polarity
bit (C0) setting. The preload state is entered by placing an
11.5-V to
13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the
clock pin is pulsed high, the data on the I/O pins is placed into
the ten registers.
CLOCK
VH
OUTPUTS
DISABLED
PRELOAD
CLOCKEDIN
PRELOAD DATA
PRELOAD
REGISTERED
VOLTAGE
REMOVED
tD tD tDtD tD
OUTPUT
FORCEI/O’S
TO VIH ORVIL
PRELOAD ENA.
OUTPUTSDIS.
tDMIN
= 100 ns
Level forced on
registered output pin
during preload cycle
Register state
after cycle
VIH High
VIL Low
1-102 AT22V10/L