54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Binary Counters with Dual Clock General Description This circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs change together when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is held high. The counter is fully programmable; that is, each output may be preset to either level by entering the desired data at the inputs while the load input is low. The output will change independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which, when taken to a high level, forces all outputs to the low level; independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements of clock drivers, etc., required for long words. These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up and down counting functions. The borrow output produces a pulse equal in width to the count down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count down input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count down and count up inputs respectively of the succeeding counter. Features Y Y Y Y Y Fully independent clear input Synchronous operation Cascading circuitry provided internally Individual preset each flip-flop Alternate Military/Aerospace device (54LS193) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications. Connection Diagram Dual-In-Line Package TL/F/6406 - 1 Order Number 54LS193DMQB, 54LS193FMQB, 54LS193LMQB, DM54LS193J, DM54LS193W, DM74LS193M or DM74LS193N See NS Package Number E20A, J16A, M16A, N16E or W16A C1995 National Semiconductor Corporation TL/F/6406 RRD-B30M105/Printed in U. S. A. 54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock June 1989 Absolute Maximum Ratings (Note) Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C DM54LS and 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Recommended Operating Conditions Symbol DM54LS193 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 1) DM74LS193 Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 2 2 V V 0.7 0.8 V b 0.4 b 0.4 mA 4 0 25 20 8 mA 0 25 MHz 0 20 MHz Clock Frequency (Note 2) 0 tW Pulse Width of Any Input (Note 6) 20 20 ns tSU Data Setup Time (Note 6) 20 20 ns tH Data Hold Time (Note 6) 0 0 ns tREL Release Time (Note 6) TA Free Air Operating Temperature Electrical Characteristics Symbol 40 40 b 55 125 ns 0 70 over recommended operating free air temperature range (unless otherwise noted) Parameter Conditions Min Typ (Note 3) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min DM54 0.25 0.4 DM74 0.35 0.5 IOL e 4 mA, VCC e Min DM74 0.25 0.4 VOL C DM54 2.5 3.4 DM74 2.7 3.4 V V II Input Current @ Max Input Voltage VCC e Max, VI e 7V IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.4 mA IOS Short Circuit Output Current VCC e Max (Note 4) Supply Current VCC e Max (Note 5) ICC 0.1 DM54 b 20 b 100 DM74 b 20 b 100 Note 1: CL e 15 pF, RL e 2 kX, IA e 25 C and VCC e 5V. Note 2: CL e 50 pF, RL e 2 kX, IA e 25 C and VCC e 5V. Note 3: All typicals are at VCC e 5V, TA e 25 C. Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 5: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V. Note 6: TA e 25 C and VCC e 5V. 2 19 34 mA mA mA Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) RL e 2 kX Symbol Parameter From (Input) To (Output) CL e 15 pF Min Max 25 CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Count Up to Carry 26 30 ns tPHL Propagation Delay Time High to Low Level Output Count Up to Carry 24 36 ns tPLH Propagation Delay Time Low to High Level Output Count Down to Borrow 24 29 ns tPHL Propagation Delay Time High to Low Level Output Count Down to Borrow 24 32 ns tPLH Propagation Delay Time Low to High Level Output Either Count to Any Q 38 45 ns tPHL Propagation Delay Time High to Low Level Output Either Count to Any Q 47 54 ns tPLH Propagation Delay Time Low to High Level Output Load to Any Q 40 41 ns tPHL Propagation Delay Time High to Low Level Output Load to Any Q 40 47 ns tPHL Propagation Delay Time High to Low Level Output Clear to Any Q 35 44 ns 3 20 MHz Logic Diagram TL/F/6406 - 2 4 Timing Diagrams Typical Clear, Load, and Count Sequences TL/F/6406 - 3 Note A: Clear overrides load, data, and count inputs. Note B: When counting up, count-down input must be high; when counting down, count-up input must be high. 5 Physical Dimensions inches (millimeters) Ceramic Leadless Chip Carrier Package (E) Order Number 54LS193LMQB NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54LS193DMQB or DM54LS193J NS Package Number J16A 6 Physical Dimensions inches (millimeters) (Continued) 16-Lead Small Outline Molded Package (M) Order Number DM74LS193M NS Package Number M16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74LS193N NS Package Number N16E 7 54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 54LS193FMQB or DM54LS193W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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