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ST10F280
March 2003
■HIGH PERFORMANCE CPU WITH DSP FUNCTIONS
- 16-BIT CPU WITH 4-ST AGE PIPELINE.
- 50ns INSTRUCTION CYCLE TIME AT 40MHz CPU
CLOCK.
- MULTIPLY/ACCUMULATE UNIT (MAC) 16 X 16-BIT
MULTIPLICATION, 40-BIT ACCUMULATOR
- REPEAT UNI T.
- ENHANCED BOOLEAN BIT MANIPULATION FACILITIES.
- AD DI TI ONA L IN ST RUC T ION S T O SU P PO RT HLL
AND OPE RATING SYSTEMS.
- SINGLE-CYCLE CONTEXT SWITCHING SUPPORT.
■MEMORY ORGANIZATION
- 512K BYT E O N-C HI P FL AS H MEM O RY SINGLE
VO L TAG E WITH ER AS E/ PROGR AM CONTRO LL ER.
- 100K ERASING/PROGRAMMING CYCLES.
- 20 YE AR DAT A RETENT IO N TIM E
- UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
CODE AND DATA (5M BYTE WITH CAN).
- 2K BY TE ON -CH IP INT ER N AL RA M (IRA M ).
- 16K BYTE EXT ENSION RAM (XRA M).
■FAST AND FLEXIBLE BUS
- PROGRAMMABLE EXTERNAL BUS CHARACTERIS-
TICS FOR DIFFERENT ADDRES S RANGES.
- 8-BI T O R 16- BI T EX TE RN AL D AT A BU S.
- MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
ADDRESS/DATA BUSES.
- FIVE PROGRAMMABLE CHIP-SELECT SIGNALS.
- HOLD-ACKNOWL EDGE BUS ARBITRATION SUPPORT.
■INTERRUPT
- 8-CHANNEL PERIPHERAL EVENT CONTROLLER
FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA
TRANSFER.
- 16-PRIOR ITY-LEVEL INTERRU PT SYSTEM WITH 56
SOURCES, SAMPLE-RATE DOWN TO 25ns.
■TWO MULTI-FUNCTIONAL GENERAL PURPOSE
TIMER UNITS WITH 5 TIMERS.
■TW O 16-CH ANNEL CA PTURE/COMPARE UNITS
■A/D CONVERTER
- 2X16-CHANNEL 10-BIT.
- 4.85µS CONVERSION TIME
- ON E TIMER FOR ADC CHANNEL INJEC TI ON
■8-CHANNEL PWM UNIT
■SERIAL CHANNELS
- SYNCHRONOUS/ASYNC SERI AL CHANNEL
- HIGH-SPEED SYNCHRONOUS CHANNEL.
■FA IL-SAFE PROTECT ION
- PROGRAMMABLE WATCHDOG TIMER.
- OSCILLAT OR WATCHDOG.
■TWO CAN 2.0b INTERFACES OPERATING ON ONE
OR TWO CAN BUSSES (30 OR 2X15 MESSAGE
OBJECTS)
■ON-CHIP BOOTSTRAP LOADER
■CLOCK GENERATION
- ON -CH IP PL L .
- DIRECT OR PRESCALED CLOCK INPUT.
■UP T O 143 GENERAL PURPO SE I/O LI NE S
- INDIVIDUALLY PROGRAMMABLE AS INPUT, OUT-
PUT OR SPECIAL FUNCTION.
- PROGRAMMABLE THRESHOLD (HYSTERESIS).
■IDL E AN D POWE R DOWN M OD ES
■MA XI MUM CPU FREQUE NC Y 40M H z
■PACKAGE PBGA 208 BALLS (23mm x 23mm x
1.96 mm - PITCH 1.27mm).
■SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED
REGULATOR FOR 3.3 V COR E SUPPLY).
■TEMPERAT UR E RA NGE : -40 +125°C
PBGA 208 (23 x 23 x 1.96 - Pitch 1.27 mm)
(Plastic Bold Grid Array)
ORDER CODE: ST10F280-JT3
P4.7 CAN 2 _ T x D
P4.6 CAN 1 _ T x D
P4.5 CAN 1 _ RxD
P4.4 CAN 2 _ RxD
Port 0Port 1Port 4
Port 6 Port 5 Port 3
Port 2
GPT1
GPT2
ASC usart
BRG
CPU-Core and MAC Unit Internal
RAM
Watchdog
Inte rrupt C o ntroller
8
32 16
PEC
16
16
CAN1
Port 7 P o rt 8
External Bus
10- Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
512K Byte
and PLL
Flash Mem ory
XTAL1 XTAL2
2K B yte
15 88
8
16
3.3V Voltage
Regulator
16K Byte
XRAM
CAN2
XPORT9
16
XPWM
4
XTIMER
P7.7 Trigg e r fo r A D C
16
XPORT10
16
16
c hannel injection
XADCINJ
Ex ternal c on n e x ion
16-BIT MCU WI TH MAC UNIT, 512K BYTE FLASH MEMORY AND 18K BYTE RAM
PRODUCT PREVIEW
This is advance information on a new product now in development or undergoing evaluation. D etails are subject to change without notice.
ST10F280
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TABLE OF CONTENTS
1 - INTRO DUCTIO N .............. ........... ............ ................. ............ ........... ............ ............ ... 6
2 - BALL DATA ......... ............ ........... ............ ............ ............ ............ ............ ........... ........ 7
3 - FUNCTIONAL DESCRI PTION ....... ............ ....... ............ ........... ....... ............ ....... ........ 17
4 - MEMOR Y ORGANIZATION ....................................................................................... 18
5 - INTERNAL FLASH MEMORY ................ ........................ ............ ....... ............ ....... ..... 21
5.1 - OVERVIEW ................................................................................................................ 21
5.2 - OPERATIONAL OVERVIEW ...................................................................................... 21
5.3 - ARCHITECTURAL DESCRIPTION ............................................................................ 23
5.3.1 - Read Mode ................................................................................................................. 23
5.3.2 - Command Mode ......................................................................................................... 23
5.3.3 - Flash Status Register ................................................................................................. 23
5.3.4 - Flash Protection Register ........................................................................................... 25
5.3.5 - Instructions Descrip tion .............................................................................................. 25
5.3.6 - Reset Process ing and Initial State . ............................................................................. 29
5.4 - FLASH MEMORY CONF IGURATION ........................................................................ 29
5.5 - APPLICATION EXAMPLES ....................................................................................... 29
5.5.1 - Handling of Flash Add resses .. .................................................................................... 29
5.5.2 - Basic Flash Access Control ........................................................................................ 30
5.5.3 - Program ming Examples ............................................................................................. 31
5.6 - BOOTSTRAP LOADER ............................................................................................ 34
5.6.1 - Entering the Bootstrap Loade r .................................................................................... 34
5.6.2 - Memory Configuration After Reset ............................................................................. 35
5.6.3 - Loading the Startup Code ........................................................................................... 36
5.6.4 - Exiting Bootst rap Loader Mode ...................... ................... .............. ................... ........ 36
5.6.5 - Choosin g the Baud Rate for the BSL ... ...................................................................... 37
6 - CENTRAL PROCESSING UNIT (CPU) ..................................................................... 38
6.1 - MULTIPLIER-ACCUMULATOR UNIT (MAC) ............................................................. 39
6.1.1 - Features ..................................................................................................................... 40
6.1.1. 1 - Enhanced A ddres sing Capabilities. ................... ...................................... .................... 40
6.1.1.2 - Multiply-Accumulate Unit............................................................................................. 40
6.1.1 .3 - Pr o g r a m Cont r o l........... ............ ........... ............ ............ ............ ............ ............ ............ 40
6.2 - INSTRUCTION SET SUMM ARY ................................................................................ 41
6.3 - MAC COPROCESSOR SPECIFIC INSTRUCTIONS ................................................. 42
7 - EXTERNAL BUS CONTROLLER ......... ............ ....... ............ ....... ............ ........... ........ 46
7.1 - PROGRAMMABLE CHIP SELECT TIMING CONTROL ............................................ 46
7.2 - READY PROGRAMMABLE POLARITY ..................................................................... 47
8 - INTERRUPT SYSTEM .. ............ ............ ............ ............ ........... ............ ............ .......... 49
8.1 - EXTERNAL INTE RRUPTS ......................................................................................... 49
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8.2 - INTERRUPT REGIST ERS AND VECTORS L OCATION LIST .................................. 50
8.3 - INTERRUPT CONTROL REGISTERS ....................................................................... 52
8.4 - EXCEPTION AND ERROR TRAPS LIST ................................................................... 53
9 - CAPTURE/COMPARE (CAPCOM) UNITS ................................................................ 54
10 - GENERAL PURPOSE T IMER UNIT .......................................................................... 57
10.1 - GPT1 .......................................................................................................................... 57
10.2 - GPT2 .......................................................................................................................... 58
11 - PW M MODULE ............. ............ ............ ............ ............ ........... ............ ............ .......... 60
11.1 - STANDARD PW M MODULE ...................................................................................... 60
11.2 - NEW PW M MODULE : XPWM ................................................................................... 61
11.2.1 - Operatin g Modes ........................................................................................................62
11.2.1. 1 - Mode 0: Standard PW M Gen eration (Edge Aligned PW M)......................................... 62
11.2.1. 2 - Mode 1: Symm etrical PW M Gen eration (Cente r Aligned PW M) ................................. 63
11.2.1.3 - Burst Mode ................................................................................................................ 64
11.2 .1 .4 - Single Shot Mo d e .... ............ ............ ............ ............ ............ ........... ............ ............... 65
11.2.2 - XPWM Module Registers ........................................................................................... 66
11.2.3 - Interrupt Request Generation ..................................................................................... 68
11 .2.4 - XPWM Ou tput Signals .......................... ............................... ...................................... . 68
11.2.5 - XPOLAR Register (polarity of the XPWM channel) . ................................................... 69
12 - PARALLEL PORT S ............. ............ ............ ............ ............ ........... ............ ............ ... 70
12.1 - INTRODUCTION ........................................................................................................ 72
12.1.1 - Open Drain Mode ....................................................................................................... 72
12.1.2 - Input Threshold Control ............................................................................................ 73
12.1.3 - Output Drive r Control ................................................................................................73
12.1.4 - Alte rnate Port Functions ............................................................................................. 75
12.2 - PORT0 ........................................................................................................................ 76
12.2.1 - Alte rnate Functions of PO RT0 .................................................................................... 77
12.3 - PORT1 ........................................................................................................................ 79
12.3.1 - Alte rnate Functions of PO RT1 .................................................................................... 79
12.4 - PORT 2 ....................................................................................................................... 80
12.4.1 - Alternate Functions of Port 2 ..................................................................................... 81
12.5 - PORT 3 ....................................................................................................................... 84
12.5.1 - Alte rnate Functions of Port 3 ...................................................................................... 85
12.6 - PORT 4 ....................................................................................................................... 87
12.6.1 - Alte rnate Functions of Port 4 ...................................................................................... 88
12.7 - PORT 5 ....................................................................................................................... 92
12.7.1 - Port 5 Schmitt Trigger Analog Inputs . ......................................................................... 93
12.8 - PORT 6 ....................................................................................................................... 93
12.8.1 - Alte rnate Functions of Port 6 ...................................................................................... 94
12.9 - PORT 7 ....................................................................................................................... 95
12.9.1 - Alte rnate Functions of Port 7 ...................................................................................... 96
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12.1 0 - PORT 8 ............ ............ ............ ........... ............ ............ ............ ............ ............ ............ 99
12.10.1 - Alte rnate Functions of Port 8 ...................................................................................... 99
12.11 - XPORT 9 .................................................................................................................... 101
12.12 - XPORT 10 .................................................................................................................. 103
12.12.1 - Alte rnate Functions of XPort 10 .................................................................................. 103
12.12.2 - New Di st urb Protect i on on Analog Inputs ....... ..... .. .......... ....... ....... .. .......... ....... .. ........ 104
13 - A/D CONVERTER ....... ............ ........... ............ ............ ............ ............ ............ ............ 105
13.1 - A/D CONVERTER MODULE ...................................................................................... 105
13.2 - MULTIPLEXAGE OF TWO BLOCKS OF 16 ANALOG INPU TS ................................ 106
13.3 - XTIMER PERIPHERAL (TRIGGER FOR ADC CHANNEL INJECTION) ................... 107
13.3.1 - Main Features ............................................................................................................. 107
13.3.2 - Register Descrip tion ...................................................................................................108
13.3.2.1 - TCR : Timer Control Register...................................................................................... 108
13.3.2.2 - XTSVR :Timer Start Value R egister ............................................................................ 109
13.3 .2 .3 - XT EVR : Ti me r En d Value Register .... ............ ............ ............ ............ ............ ............ 109
13.3.2.4 - XTCVR : Timer Current Value Reg ister....................................................................... 109
13.3.2.5 - Registers Mapping..... ................... ................... ................... .............. ................... ........ 109
13.3.3 - Block Diagram ........................................................................................................... 110
13.3 .3 .1 - Clocks............. ........... ............ ............ ............ ............ ............ ........... ............ ............... 110
13.3 .3 .2 - Re g isters ... ............ ............ ........... ............ ............ ............ ............ ............ ................ ... 110
13.3.3.3 - Timer output (XADCINJ).............................................................................................. 111
14 - SERIAL CHANNELS .... ............ ............ ............ ............ ........... ............ ............ .......... 112
14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERF ACE (ASCO) .................... 112
14.1.1 - AS CO in Asynchronous Mode ... ......... ................... ................... ................... ............... 112
14.1.2 - AS CO in Synchronous Mode ..... ......... ................... ................... ................... ............... 114
14.2 - HIGH SPEED SYNCHRONOUS SERIAL CHANNEL (SSC) ............. ....... ............ ..... 116
15 - CAN MODULES .......... ............ ........... ............ ............ ............ ....... ............ ............ ..... 118
15.1 - MEMORY MAPPIN G .................................................................................................. 118
15.1.1 - CAN1 .......................................................................................................................... 118
15.1.2 - CAN2 .......................................................................................................................... 118
15.2 - CAN BUS CONFIGURATIONS .................................................................................. 1 18
15.3 - REGIS TER AND MESSAG E OBJ ECT ORGAN IZ AT ION . ............ ............ ............ ..... 11 9
15.4 - CAN INTERRUPT HANDLING ................................................................................. 1 21
15.5 - THE MESSAGE OBJECT .......................................................................................... 1 24
15.6 - ARBITRAT ION REGISTERS ...................................................................................... 1 26
16 - WATCHDOG TIMER ... ....... ............ ............ ........... ........ ........... ............ ............ .......... 127
17 - SYSTEM RESET ........................................................................................................ 129
17.1 - ASYNCHRONOUS RESE T (LONG HARDWARE RESET) ....................................... 129
17.2 - SYNCHRONOUS RESET (WARM RESET) .............................................................. 1 30
ST10F280
5/186
17.3 - SOFTWARE RESET .................................................................................................. 131
17.4 - WATCHDOG TIMER RESET ..................................................................................... 131
17.5 - RSTOUT PIN AND BIDIRECT IONAL RESET ............................................................ 131
17.6 - RESET CIRCUITRY ................................................................................................... 132
18 - POWER REDUCTION MODES ................................................................................. 135
18.1 - IDLE MODE ................................................................................................................135
18.2 - POWER DOWN M ODE .............................................................................................. 135
18.2.1 - Protected Power Down Mode .............. . ........... ........................................................... 136
18.2.2 - Interruptable Power Down Mode ................................................................................ 136
19 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 1 39
19.1 - IDENTIFICAT ION REGISTERS ................................................................................. 148
19.2 - SYSTEM CONFIGURATION REGISTERS ................................................................ 1 49
20 - ELECT RICAL CHARACTERI STI CS ......... ........... ............ ....... ............ ....... ............ ... 155
20.1 - ABSOLUTE MAXIMUM R ATINGS ............................................................................. 155
20.2 - PARAMETER INT ERPRETATION ............................................................................. 1 55
20.3 - DC CHARACTERISTICS ........................................................................................... 155
20.3.1 - A/D Converter Characteristics .................................................................................... 158
20.3.2 - Conversion Timing Control ....................................................................................... 1 59
20.4 - AC CHARACTERISTICS ............................................................................................ 1 60
20.4.1 - Test Waveforms .......................................................................................................160
20.4.2 - Definition of Internal Timing ........................................................................................ 160
20.4.3 - Clock Generation Modes . ........................................................................................... 1 61
20.4.4 - Prescaler O peration ....................................................................................................162
20.4.5 - Direct Drive ................................................................................................................. 1 62
20.4.6 - Oscillator Watchdog (OW D) ...................................................... . ................................ 1 62
20.4.7 - Phase Locke d Loop .................................................................................................... 162
20.4.8 - External Clock Drive XTAL1 ....................................................................................... 1 63
20.4.9 - Memory Cycle Variables ............................................................................................. 164
20.4.10 - Multiplexed Bus .......................................................................................................... 1 65
20.4.11 - Demultiplexe d Bus ...................................................................................................... 171
20.4.12 - CLKOUT and READY ................................................................................................. 1 77
20.4.13 - External Bus Arbitration ..............................................................................................179
20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing ........................................... 181
20.4.14.1 M aster Mode................................................................................................................ 181
20.4.14.2 Slave mode.................................................................................................................. 182
21 - PACKAGE MECHANICAL DATA ............... ....... ............ ....... ............ ....... ............ ... 183
22 - ORDERING IN FORMATION ...................................................................................... 184
ST10F280
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1 - INTR O DUCTION
The ST10F280 is a new derivative of the ST
Microelectronics ST10 family of 16-bit single-chip
CMOS microcontrollers. It combines high CPU
performance (up to 20 million instructions per
second) with high peripheral functionality and
enhanced I/O-capabilities. It al so provi des on-chip
high-speed single voltage FLASH memory,
on-chip high-speed RAM, and clock generation
via PLL.
ST10F280 is processed in 0.35µm CMOS
technology. The MCU core and the logic is
supplied with a 5V to 3.3V on chip voltage
regulator. The part is supplied with a single 5V
suppl y and I/Os work at 5V.
The device is upward compatible with the
ST10F269 device, with the following set of
differences:
– Two supply pins (DC1,DC2) on the PBGA-208
package are used for decoupling the internally
generated 3.3V core logic supply. Do not con-
nect these two p ins to 5. 0V external suppl y. In-
stead, these pins should be connected to a
decoupling capacitor (ceramic type, value
≥330nF).
– T he A /D Converter characteristics stay identical
but 16 new input channel are added. A bit in a
new register (XADCMUX) control the multiplex-
age between the first block of 16 channel (on
Port5) and the second block (on XPort10). The
conversion result registers stay identical and the
software management can determine the block
in u se . A new dedicated timer controls now the
ADC channel inject ion mode on the input CC 31
(P7.7). The output of this timer is visible on a
dedicated pin (XADCINJ) to emulate this new
functionnality.
– A second XPWM peripheral (4 new channels) is
added. Four dedicated pins are reserved for the
outputs (XPWM[0:3])
– A new general purpose I/O port named XPORT9
(16 bits) is added. Due to the bit addressing
management, it will be different from other
standard general purpose I/O ports.
Fi gure 1 : Logic Symbol
XTAL1
RSTIN
XTAL2
RSTOUT
NMI
EA
READY
ALE
RD
WR/WRL
Port 5
16-bit
Port 6
8-bit
Port 4
8-bit
Port 3
15-bit
Port 2
16-bit
Port 1
16-bit
Port 0
16-bit
V
DD
V
SS
Port 7
8-bit
Port 8
8-bit
V
AREF
V
AGND
XPort 9
16-bit
XPWM
4-bit
XADCINJ
XPort10
16-bit
DC1 DC2
Decoupling capacitor for internal regulator
ST10F280
ST10F280
7/186
2 - BALL DATA
The S T10F280 package is a PB GA of 23 x 23 x 1. 96 mm. T he pitch of the balls is 1.27 m m. The signa l
assignm ent of the 208 balls is described in Figure 2 f or the confi guration and in Tabl e 1 for the ball signal
assig nme nt. This package has 25 additional ther m al balls.
Fi gure 2 : Ball Configuration (bottom view)
K7
VSS
K8
VSS
K9
VSS
J7
VSS
J8
VSS
J9
VSS
H7
VSS
H8
VSS
H9
VSS
G7
VSS
G8
VSS
G9
VSS
K10
VSS
K11
VSS
J10
VSS
J11
VSS
H10
VSS
H11
VSS
G10
VSS
G11
VSS
VSS VSS VSS VSS VSS
U1 U2
VAREF
U3
VAGND
U4 U5 U6 U7 U8 U9 U10
VSS
U11
DC2
U12 U13 U14 U15 U16
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
R1 R2 R3 R4 R14 R15 R16
M1 M2 M3 M15 M16 M17
L1
VSS
L2 L3 L15 L16 L17
VDD
K1
VDD
K2 K3 K15 K16 K17
VSS
J1 J2 J3 J15 J16 J17
H1 H2 H3 H15 H16 H17
G1 G2 G3 G15 G16 G17
F1 F2 F3 F15 F16 F17
E1 E2 E3 E15 E16 E17
VSS
D1 D2 D3 D15 D16 D17
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16
A1 A2 A3 A4
RSTIN
A5
XTAL1
A6
XTAL2
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1716151413121110987654321
1716151413121110987654321
U17
T17
R17
C17
B17
A17
UU
VSS
DC1 VDD
M4
L4
K4
J4
H4
G4
E4
D4
M14
L14
K14
J14
H14
G14
E14
D14
P15 P16 P17
P14
D5 D6 D7 D8 D9 D10 D11 D12 D13
P5 P6 P7 P8 P9 P10 P11 P12 P13
N1 N2 N3 N4
F4 F14
L7 L8 L9 L10 L11
VDD VDD
VSS VDD
VSS VDD
VSS
VDD
VSS
VSS VDD VSS VDD
P3.15
VDD
VSS
RPD
XP10.3 XP10.2 XP10.1 XP10.0
XP10.4XP10.5XP10.6XP10.7
XP10.11 XP10.8 P5.6 P5.10 P5.14XP10.9XP10.10
XP10.13 XP10.12 P5.1 P5.3 P5.7 P5.11 P5.15
XP10.14 P5.0 P5.2 P5.4 P5.8 P5.12
XP10.15 P5.5 P5.9 P5.13
xpwm.0
xpwm.1
xpwm.2
xpwm.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P8.0
P8.1P8.2
P8.3P8.4
P8.5P8.6P8.7
P7.0P7.1P7.2P7.3
P7.4 P7.5 P7.6
P7.7 XADCINJ
P2.0
P2.1
P2.2
P2.3 P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8 P3.9
P3.10
P3.11 P3.12
P3.13
P4.0
P4.1
P4.2
P4.3
P4.4 P4.5
P4.6 P4.7
RD WR READY ALE
EAP0.0P0.1P0.2
P0.3P0.4P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
XP9.0
XP9.1
XP9.2
XP9.3
XP9.4
XP9.5
XP9.6
XP9.7
XP9.8
XP9.9
XP9.10
XP9.11
XP9.12
XP9.13
XP9.14
XP9.15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7P1.8
P1.9
P1.10
P1.11
P1.12
P1.13
P1.14 P1.15
VSS
RSTOUT
NMI
VSS
VSS
VSS
VSS VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS VSS VSS VSS
VSS VSS
R5 R6 R7 R8 R9 R10 R11 R12 R13
N15 N16 N17
N14
P1 P2 P3 P4
ST10F280
8/186
Table 1 : Ball D es c r iption
Symbol Ball
Number Type Function
P6.0 – P6.7 I/O Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. Port 6 outputs can be configured as push/pull or open
drain drivers.
The following Port 6 pins also serve for alternate functions:
E4 O P6.0 CS0 Chip Select 0 Output
D3 O P6.1 CS1 Chip Select 1 Output
B1 O P6.2 CS2 Chip Select 2 Output
C1 O P6.3 CS3 Chip Select 3 Output
D2 O P6.4 CS4 Chip Select 4 Output
E3 I P6.5 HOLD External Master Hold Request Input
F4 O P6.6 HLDA Hold Acknowledge Output
D1 O P6.7 BREQ Bus Request Output
P8.0 – P8.7 I/O Port 8 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. Port 8 outputs can be configured as push/pull or open
drain drivers. The input threshold of Port 8 is selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
E2 I/O P8.0 CC16IO CAPCOM2: CC16 Capture Input / Compare Output
F3 I/O P8.1 CC17IO CAPCOM2: CC17 Capture Input / Compare Output
F2 I/O P8.2 CC18IO CAPCOM2: CC18 Capture Input / Compare Output
G3 I/O P8.3 CC19IO CAPCOM2: CC19 Capture Input / Compare Output
G2 I/O P8.4 CC20IO CAPCOM2: CC20 Capture Input / Compare Output
H4 I/O P8.5 CC21IO CAPCOM2: CC21 Capture Input / Compare Output
H3 I/O P8.6 CC22IO CAPCOM2: CC22 Capture Input / Compare Output
H2 I/O P8.7 CC23IO CAPCOM2: CC23 Capture Input / Compare Output
P7.0 – P7.7 I/O Port 7 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. Port 7 outputs can be configured as push/pull or open
drain drivers. The input threshold of Port 7 is selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
J4 O P7.0 POUT0 PWM Channel 0 Output
J3 O P7.1 POUT1 PWM Channel 1 Output
J2 O P7.2 POUT2 PWM Channel 2 Output
J1 O P7.3 POUT3 PWM Channel 3 Output
K2 I/O P7.4 CC28IO CAPCOM2: CC28 Capture Input / Compare Output
K3 I/O P7.5 CC29IO CAPCOM2: CC29 Capture Input / Compare Output
K4 I/O P7.6 CC30IO CAPCOM2: CC30 Capture Input / Compare Output
L2 I/O P7.7 CC31IO CAPCOM2: CC31 Capture Input / Compare Output
ST10F280
9/186
XP10.0 – XP10.15 I XPort 10 is a 16-bit input-only port with Schmitt-Trigger characteristics.
The pins of XPor t10 also ser ve as the analog in put chann els (up to 16) for the
A/D converter, where XP10.X equals ANx (Analog input channel x).
M4
M3
M2
M1
N4
N3
N2
N1
P4
P3
P2
P1
R2
R1
T1
U1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
XP10.0
XP10.1
XP10.2
XP10.3
XP10.4
XP10.5
XP10.6
XP10.7
XP10.8
XP10.9
XP10.10
XP10.11
XP10.12
XP10.13
XP10.14
XP10.15
P5.0 – P5.15 I Port 5 is a 16-bit input-only port with Schmitt-Trigger characteristics.
The pins of Port 5 also ser ve as the analog inp ut chann els (up to 16) for the A/D
converter, where P5.x equals ANx (Analog input channel x),
or they serve as timer inputs:
T2 I P5.0
R3 I P5.1
T3 I P5.2
R4 I P5.3
T4 I P5.4
U4 I P5.5
P5 I P5.6
R5 I P5.7
T5 I P5.8
U5 I P5.9
P6 I P5.10 T6EUD GPT2 Timer T6 External Up / Down Control Input
R6 I P5.11 T5EUD GPT2 Timer T5 External Up / Down Control Input
T6 I P5.12 T6IN GPT2 Timer T6 Count Input
U6 I P5.13 T5IN GPT2 Timer T5 Count Input
P7 I P5.14 T4EUD GPT1 Timer T4 External Up / Down Control Input
R7 I P5.15 T2EUD GPT1 Timer T2 External Up / Down Control Input
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
10/186
P2.0 – P2.15 I/O Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. Port 2 outputs can be configured as push/pull or open
drain drivers. The input threshold of Port 2 is selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
T7 I/O P2.0 CC0IO CAPCOM: CC0 Capture Input / Compare Output
P8 I/O P2.1 CC1IO CAPCOM: CC1 Capture Input / Compare Output
R8 I/O P2.2 CC2IO CAPCOM: CC2 Capture Input / Compare Output
T8 I/O P2.3 CC3IO CAPCOM: CC3 Capture Input / Compare Output
T9 I/O P2.4 CC4IO CAPCOM: CC4 Capture Input / Compare Output
P9 I/O P2.5 CC5IO CAPCOM: CC5 Capture Input / Compare Output
R9 I/O P2.6 CC6IO CAPCOM: CC6 Capture Input / Compare Output
U9 I/O P2.7 CC7IO CAPCOM: CC7 Capture Input / Compare Output
T10 I/O
IP2.8 CC8IO CAPCOM: CC8 Capture Input / Compare Output,
EX0IN Fast External Interrupt 0 Input
R10 I/O
IP2.9 CC9IO CAPCOM: CC9 Capture Input / Compare Output,
EX1IN Fast External Interrupt 1 Input
P10 I/O
IP2.10 CC10IO CAPCOM: CC10 Capture Input / Compare Output,
EX2IN Fast External Interrupt 2 Input
T11 I/O
IP2.11 CC11IO CAPCOM: CC11 Capture Input / Compare Output,
EX3IN Fast External Interrupt 3 Input
R11 I/O
IP2.12 CC12IO CAPCOM: CC12 Capture Input / Compare Output,
EX4IN Fast External Interrupt 4 Input
U12 I/O
IP2.13 CC13IO CAPCOM: CC13 Capture Input / Compare Output,
EX5IN Fast External Interrupt 5 Input
P11 I/O
IP2.14 CC14IO CAPCOM: CC14 Capture Input / Compare Output,
EX6IN Fast External Interrupt 6 Input
T12 I/O
I
I
P2.15 CC15IO CAPCOM: CC15 Capture Input / Compare Output,
EX7IN Fast External Interrupt 7 Input
T7IN CAPCOM2 Timer T7 Count Input
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
11/186
P3.0 - P3.13,
P3.15 I/O Por t 3 is a 15-bit (P 3.14 is missi ng) bidirecti onal I/O por t. It i s bit-wise pro gra m-
mable for input or output via direction bits. For a pin configured as input , the out-
put driver is put into hig h-impedan ce state. Por t 3 outputs ca n be config ured as
push/pull or open drain drivers. The input threshold of Por t 3 is selectable (TTL
or special).
The following Port 3 pins also serve for alternate functions:
R12 I P3.0 T0IN CAPCOM Timer T0 Count Input
T13 O P3.1 T6OUT GPT2 Timer T6 Toggle Latch Output
P12 I P3.2 CAPIN GPT2 Register CAPREL Capture Input
R13 O P3.3 T3OUT GPT1 Timer T3 Toggle Latch Output
T14 I P3.4 T3EUD GPT1 Timer T3 External Up / Down Control Input
P13 I P3.5 T4IN GPT1 Timer T4 Input for Count / Gate /
Reload / Capture
R14 I P3.6 T3IN GPT1 Timer T3 Count / Gate Input
P14 I P3.7 T2IN GPT1 Timer T2 Input for Count / Gate /
Reload / Capture
R15 I/O P3.8 MRST SSC Master-Receive / Slave-Transmit I/O
R16 I/O P3.9 MTSR SSC Master-Transmit / Slave-Receive O/I
N14 I/O P3.10 TxD0 ASC0 Clock / Data Output (Asynchronous / Synchronous)
P15 O P3.11 RxD0 ASC0 Data Input (Asynchronous) or I/O (Synchronous)
P16 O P3.12 BHE External Memory High Byte Enable Signal,
WRH External Memory High Byte Write Strobe
M14 I/O P3.13 SCLK SSC Master Clock Output / Slave Clock Input
T17 O P3.15 CLKOUT System Clock Output (=CPU Clock)
P4.0 – P4.7 I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. The input threshold is selectable (TTL or special).
P4.6 & P4.7 outputs can be configured as push-pull or open-drain drivers.
In case of an external bus configuration, Port 4 can be used to output the seg-
ment address lines:
N16 O P4.0 A16 Least Significant Segment Address Line
M15 O P4.1 A17 Segment Address Line
L14 O P4.2 A18 Segment Address Line
M16 O P4.3 A19 Segment Address Line
L15 O
IP4.4 A20 Segment Address Line
CAN2_RxD CAN2 Receive Data Input
L16 O
IP4.5 A21 Segment Address Line
CAN1_RxD CAN1 Receive Data Input
K14 O
OP4.6 A22 Segment Address Line, CAN_TxD
CAN1_TxD CAN1 Transmit Data Output
K15 O
OP4.7 A23 Most Significant Segment Address Line
CAN2_TxD CAN2 Transmit Data Output
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
12/186
RD J14 O External Memory Read Strobe. RD is activated for every external instruction or
data read access.
WR/WRL J15 O External Memory Write Strobe. In WR-mode this pin is activated for every
external data write access. In WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data write access on an 8-bit bus.
See WRCFG in register SYSCON for mode selection.
READY/
READY J16 I Ready Input. The active level is programmable. When the Ready function is
enabled, the selected inactive lev el at this pin during an external memory access
will force the insertion of memory cycle time waitstates until the pin returns to the
selected active level.
ALE J17 O Address Latch Enable Output. Can be used f or latching the address into external
memory or an address latch in the multiplexed bus modes.
EA H17 I External Access Enable pin. A low level at this pin during and after Reset forces
the ST10F280 to begin instruction ex ecution out of external memory. A high le vel
forces execution out of the internal Flash Memory.
PORT0:
P0L.0 - P0L.7,
P0H.0 - P0H.7
I/O PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise
programmable for input or output via direction bits. For a pin configured as input,
the output driver is put into high-imped ance state.
In case of an exter nal bus configu ration, PORT0 ser ves as the addre ss (A) and
address/data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: D0 - D7 D0 - D7
P0H.0 – P0H.7: I/O D8 - D15
Multiplexed bus modes:
Data Path Width: 8-bit 16-bit
P0L.0 – P0L.7: AD0 - AD7 AD0 - AD7
P0H.0 – P0H.7: A8 - A15 AD8 - AD15
H16 I/O P0L.0
H15 I/O P0L.1
H14 I/O P0L.2
G16 I/O P0L.3
G15 I/O P0L.4
G14 I/O P0L.5
F16 I/O P0L.6
E17 I/O P0L.7
F15 I/O P0H.0
E16 I/O P0H.1
F14 I/O P0H.2
D17 I/O P0H.3
E15 I/O P0H.4
D16 I/O P0H.5
C17 I/O P0H.6
E14 I/O P0H.7
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
13/186
XPORT9.0 -
XPORT9.15 I/O XPort 9 is a 16-b it bidirect ional I/O por t. It is bit-wise programmable for in put or
output via direction bits. For a pin configured as input, the output driver is put into
high-impedance state. XPort 9 outputs can be configured as push/pull or open
drain drivers.
D15 I/O XPORT9.0
C16 I/O XPORT9.1
D14 I/O XPORT9.2
C15 I/O XPORT9.3
B16 I/O XPORT9.4
D13 I/O XPORT9.5
C14 I/O XPORT9.6
B15 I/O XPORT9.7
A15 I/O XPORT9.8
B14 I/O XPORT9.9
C13 I/O XPORT9.10
D12 I/O XPORT9.11
B13 I/O XPORT9.12
C12 I/O XPORT9.13
D11 I/O XPORT9.14
B12 I/O XPORT9.15
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
14/186
PORT1:
P1L.0 - P1L.7,
P1H.0 - P1H.7
I/O PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise
programmable for input or output via direction bits. For a pin configured as input,
the output dri ver is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after switching from a
demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins
also serve for alternate functions:
C11 I/O P1L.0
B11 I/O P1L.1
D10 I/O P1L.2
C10 I/O P1L.3
B10 I/O P1L.4
A10 I/O P1L.5
D9 I/O P1L.6
C9 I/O P1L.7
C8 I/O P1H.0
D8 I/O P1H.1
A7 I/O P1H.2
B7 I/O P1H.3
C7 I P1H.4 CC24IO CAPCOM2: CC24 Capture Input
D7 I P1H.5 CC25IO CAPCOM2: CC25 Capture Input
C5 I P1H.6 CC26IO CAPCOM2: CC26 Capture Input
C6 I P1H.7 CC27IO CAPCOM2: CC27 Capture Input
XTAL1 A5 I XTAL1: Input to the oscillator amplifier and input to the internal clock generator
XTAL2 A6 O XTAL2: Output of the oscillator amplifier circuit.
To clo ck the device from an external source, drive XTAL1, while leaving XTAL2
unconnected. Minimum and maximum high/low and rise/fall times specified in
the AC Characteristics must be observed.
RSTIN A3 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a spec-
ified duration while the oscillator is running resets the ST10F280. An internal pul-
lup resistor permits power-on reset using only a capacitor connected to VSS.
In bidire ctiona l re set m ode (en abled by s etting bit BDR STEN in SYS CON reg is-
ter), the RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT B4 O Internal Reset Indication Output. This pin is set to a low level when the part is
executing either a hardware, a software or a watchdog timer reset. RSTOUT
remains low until the EINIT (end of initialization) instruction is executed.
NMI C4 I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU
to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when
the PWRDN (power down) instruction is executed, the NMI pin must be low in
order to force the ST10F280 to go into power down mode. If NMI is high and
PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal
mode.
If not used, pin NMI should be pulled high externally.
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
15/186
XPWM.0 D4 O XPWM Channel 0 Output
XPWM.1 C3 O XPWM Channel 1 Output
XPWM.2 B2 O XPWM Channel 2 Output
XPWM.3 C2 O XPWM Channel 3 Output
XADCINJ L3 O Output trigger for ADC channel injection
VAREF U2 - Reference voltage for the A/D converter.
VAGND U3 - Reference ground for the A/D converter.
RPD M17 I/O Timing pin for the return from powerdown circuit and synchronous/asynchronous
reset selection.
DC1 G1 O 3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be connected
between this pin and nearest VSS pin.
DC2 U11 O 3.3V Decoupling pin: a decoupling capacitor of ~330 nF must be connected
between this pin and VSS nearest pin.
VDD A2
A9
A12
A14
E1
K1
U8
U15
P17
L17
G17
- Digital Supply Voltage: + 5 V during normal operation, idle mode and power
down mode
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
16/186
VSS A1
A4
A8
A11
A13
A16
A17
B3
B5
B6
B8
B9
B17
D5
D6
F1
F17
G4
H1
K16
K17
L1
L4
N15
N17
R17
T15
T16
U7
U10
U13
U14
U16
U17
- Digital Ground.
Table 1 : Ball Description (continued)
Symbol Ball
Number Type Function
ST10F280
17/186
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F280 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
block diagram gives an overview of the different
on-chi p components and the high bandwidth inter-
nal bus structure of the ST10F 280.
Fi gure 3 : Block Diagram
P4.7 CAN2_TxD
P4.6 CAN1_TxD
P4.5 CAN1_RxD
P4.4 CAN2_RxD
Port 0
Port 1Po rt 4
Port 6 Port 5 Port 3
Port 2
GPT1
GPT2
ASC usart
BRG
CP U-Core and MAC Unit Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7 Port 8
External Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
51 2K Byte
and PLL
Flash Mem ory
XTAL1 XTAL2
2K Byte
15 88
8
16
3.3V Voltage
Regulator
16K Byte
XRAM
CAN2
XPORT9
16
XPWM
4
XTIMER
P7.7 Trigger for ADC
16
XPORT10
16
16
XADCINJ
channel injection
Exter nal connexion
ST10F280
18/186
4 - MEMO RY ORGANI ZATION
The memory s pace of the ST 10F280 is configured
in a unified memory architecture. Code memory,
data memory, registers and I/O ports are orga-
nized within the same linear address space of
16M Bytes. The entire memory space can be
accessed bytewise or wordwise. Particular por-
tions of the on-chip memory have additionally
been mad e directly bit addressable.
FLASH: 512K Bytes of on-chip single voltage
FLASH memory.
IRAM: 2K Bytes of on-chip internal RAM
(dual-por t) is provided as a storage for data, sys-
tem stack, general purpose register banks and
code. The register bank can consist of up to 16
wordwide (R0 to R15) and/or by te wide (RL0, RH0,
…, RL7, RH7) general purpose registers. Base
addres s is 00’F600h, upper addres s is 00’FDFFh.
XRAM: 16K By tes of on-chip extension RAM (sin-
gle port XRA M) is provided as a storage for da ta,
use r s tack and code. The X R AM is a single bank,
connected to t he i nternal XB US and are accessed
like an external memory in 16-bit demultiplexed
bus-mode without waitstate or read/write delay
(50ns access at 40MHz CPU clock). Byte and
word access is allowed.
The XRAM address range is 00’8000h - 00’BFFFh
if enabled (XPEN set bit 2 of SYSCON register-,
and X RAMEN set bit 2 of XPERCON register-). If
bit XR AMEN or XPEN is cl e a r ed , the n a ny access
in the address range 00’8000h 00’BFFFh will be
directed to external memory interface, using the
BUSCONx register corresponding to address
matching ADDRSELx register
As the XRAM appears like external memory, it
cannot b e used for the ST10F280’s system stack
or register banks. The XRAM is not provided for
single bi t storage and th erefore is not bit addres s-
able.
SFR/ESFR: 1024 b yt es (2 * 512 bytes) of address
spa ce is res erved for the special function register
areas. SFRs are wordwide registers which are
used for controlling and monitoring functions of
the differen t on-chip units.
CAN1: Address range 00’EF00h 00’EFFFh is
reserved for the CAN1 Module access . The CAN1
is enabled by setting XPEN bit 2 of the SYSCON
register and bit 0 of the new XPERCON register.
Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (byte accesses
are possible). Two waitstates give an access time
of 100 ns at 40MHz CPU clock. No tristate wait-
stat e is used.
CAN2: Address range 00’EE00h 00’EEFFh is
reserved for the CAN2 Module access . The CAN2
is enabled by setting XPEN bit 2 of the SYSCON
register and bit 1 of the new XPERCON register.
Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (byte accesses
are possible). Two waitstates give an access time
of 100 ns at 40MHz CPU clock. No tristate wait-
stat e is used.
In order to meet the needs of designs where more
memory is required than is provided on chi p, up to
16M Bytes of external RAM and/or ROM can be
con nected to the m icrocont roller. If one o r the two
CAN modules are used, Port 4 can not be pro-
grammed to output all 8 segment address lines.
Thus, only 4 segm ent address li nes can be used,
reduc ing the exter nal mem ory space to 5M Bytes
(1M Byte per CS line).
XPWM: Address range 00’EC00h 00’ECFFh is
reserved for the XPWM Module access. The
XPWM is enabled by setting XPEN bit 2 of the
SYSCON registe r and bit 4 of the new XPERCON
register. Accesses to the XPWM Module use
demultiplexed addresses and a 16-bit data bus
(byte accesses are poss ible ). Two waitstates give
an acces s time of 100 ns at 40M Hz CPU clock. No
tri state waitstate is used.
XPORT9, XTIMER, XPORT10, XADCMUX :
Address range 00’C000h 00’C3FFh is reserved
for the XPORT9, XPORT10, XTIMER and
XADCMUX peripherals access. The XPORT9,
XTIMER, XPORT10, XADCMUX are enabled by
setting XPEN bit 2 of the SYSCON register and
the bit 3 of the ne w XPERCON regist er . Accesses
to the XPORT9, XTIMER, XPORT10 and
XADCMUX modules use a 16-bit demultiplexed
bus mode without waitstate or read/write delay
(50ns access at 40MHz CPU clock). Byte and
word access is allowed.
Vis ibility of XBUS Peripheral s
The XBUS peripherals can be separately selected
for being visible to the user by means of corre-
spo nding selection bits in the X P ERCON register.
If not selected (not activated with XPERCON bit)
before the global enabling with XPEN-bit in
SYSCON register, the corresponding address
space, port pins and interrupts are not occupied
by the peripheral, thus the peripheral is not visible
and not available. SYSCON register is described
in Section 19.2 - Sys tem Configuration Registers.
ST10F280
19/186
Fi gure 4 : ST10F2 80 On-c hip Memo ry Mapping
14
07
06
05
04
00’4000
01
00
00’0000
02
00’C000
00’FFFF
SFR : 51 2 Bytes
00’FE00
00’FDFF
IRAM : 2K Bytes
00’F600
* Blocks 0, 1 a nd 2 may be remapped from segment 0 to segment 1 by se t ting SYSCON-ROMS1 (before EINIT)
RAM, SFR and X-pheripherals are
mapped into the address space.
Segme n t 4Segme n t 3Se gmen t 2Segment 1Segment 0
Data
Page
Number
Absolute
Memory
Address
00’6000
00’F1FF
ESFR : 512 Bytes
00’F000
00’EFFF
CAN1 : 2 56 Byt es
00’EF00
00’EEFF
CAN2 : 2 56 Byt es
00’EE00
00’C3FF
XPORT9 XTIMER
00’C000
03
00’ECFF
XPWM
00’EC00
Block2 = 8K Bytes
Internal
Flash
Memory
Block1 = 8K Bytes
Block0 = 16K Bytes
01’0000
01’8000
02’0000
03’0000
0C
04’0000
10
05’0000
Block6 = 64K Bytes
Block5 = 64K Bytes
Block4 = 64K Bytes
Block3 = 32K Byte s
Block2*
Block1*
Block0*
Data Page Number and Absolute Memory Address are hexad ecimal v alues.
08
08’0000
20
Block10 = 64K By tes
Se gment 8
09’0000
00’8000
00’BFFF
XRAM = 16K Byt es
XPORT10
XADCMUX
ST10F280
20/186
XPERCON (F02 4h / 12h ) ESFR Reset Value: - - 05h
Note: - When both CAN and XPWM are disab l ed via XPERCON setting, then any access in the address
range 00’EC00h 00’EFFFh will be directed to external memory interface, using the BUSCONx
register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as
General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General
Pur pos e I/O when CAN1 is not enabled.
- The default XPER selection after Reset is : XCAN1 is enabled, XCAN2 is disabled, XRAM is
enabled, XPORT9, XTIM ER, XPO RT10, XPWM, XADCMUX are disabled.
- Register XPERCON cannot be changed after the global enabling of XPeripherals, i.e. after
sett ing o f bit XPEN i n SYS CON r egi ster.
15141312111098765 4 3 2 1 0
-----------XPWMENXPERCONEN3XRAMENCAN2ENCAN1EN
RW RW RW RW RW
Bit Function
CAN1EN 0
1
CAN1 Enable Bit
Accesses to the on- chip CAN 1 XPer ipheral a nd its fu nctions are disabled. P4.5 a nd P4.6 pins
can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to
external memory if CAN2EN and XPWM bits are cleared also.
The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN 0
1
CAN2 Enable Bit
Accesses to the on- chip CAN 2 XPer ipheral a nd its fu nctions are disabled. P4.4 a nd P4.7 pins
can be used as general purpos e I/Os. Addres s range 00’EE00h-00’EEFFh is only di rected to
external memory if CAN1EN and XPWM bits are cleared also.
The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAMEN 0
1
XRAM Enable Bit
Accesses to the on-chip 16K Byte XRAM are disabled, external access performed.
The on-chip 16K Byte XRAM is enabled and can be accessed.
XPERCONEN3 0
1
XPORT9, XTIMER, XPORT10, XADCMUX Enable Bit
Accesses to the XPORT9, XTIME R, XPORT10, XADCMUX peripherals are disabled, external
access performed.
The on-chip XPORT9, XTIMER, XPORT10, XADCMUX peripherals are enabled and can be
accessed.
XPWMEN 0
1
XPWM Enable Bit
Accesses to the on-chip XPWM are disabled, external access performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ‘0’ also
The on-chip XPWM is enabled and can be accessed.
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5 - INTERNAL FLASH MEMORY
5.1 - Overview
– 512K Byte on-chip Flash memory
– Two possibilities of Flash mapping into the CPU
address space
– Flash memory can be used for code and data
storage
– 32-bit, zero waitstate read access (50ns cycle
time at fCPU = 4 0 MHz)
– Erase-Program Controller (EPC) similar to
M29F400B S TM ’s stand-alone Flash m emo ry
• W ord-by-Word P rogrammabl e (16µs t ypical)
• Data polling and Toggle Protocol for EPC
Status
• Int ernal Power-On detec tion circuit
– M em ory Erase in blocks
• O ne 16K B yte, tw o 8K By te, o ne 3 2K Byte,
seven 64K Byte blocks
• Each block can be erased separately
(1.5 sec ond typical)
• C hip erase (8.5 second typical )
• Each block can be separately protected
against pr ogramming and erasing
• Each protected block can be temporary unpro-
tected
• When enabled, the read protection prevents
access to data in Flash memory using a pro-
gram running out of the Flash memory space.
Access to data of internal Flash can only be per-
formed with an inner pr otected program
– E ras e Su spend and Resume Modes
• Read and Program another Block during erase
suspend
– S ing le V oltage operation , no need of dedicat ed
supply pin
– Low Power Consum ption:
• 4 5mA max . Read current
• 6 0mA m ax. Program or Erase current
• Automati c Stand-by-mode (50 µA maximum)
– 100,000 Erase-Program Cycles per block,
20 yea r data retention time
– Operating tempera ture: -40 to +125oC
5.2 - Operational Overview
Read Mode
In standard mode (the normal operating mode)
the Flash appears like an on-chip ROM with the
same timing and functionality. The Flash module
offers a fast access time, allowing zero waitstate
access with CPU frequency up to 40MHz.
Instruction fetches and data operand reads are
performed with all addressing modes of the
ST10F280 instruction set.
In order to optimize the programming time of the
internal Flash, blocks of 8K Bytes, 16K Bytes,
32K Bytes, 64K Bytes can be used. But the si ze of
the blocks does not apply to the whole memory
spa ce, see details in Table 2.
Table 2 : 512K Byte Flash Mem ory Block Organ isation
Block Addresses (Segment 0) Addresses (Segment 1) Size (K Byte)
0
1
2
3
4
5
6
7
8
9
10
00’0000h to 00’3FFFh
00’4000h to 00’5FFFh
00’6000h to 00’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh
04’0000h to 04’FFFFh
05’0000h to 05’FFFFh
06’0000h to 06’FFFFh
07’0000h to 07’FFFFh
08’0000h to 08’FFFFh
01’0000h to 01’3FFFh
01’4000h to 01’5FFFh
01’6000h to 01’7FFFh
01’8000h to 01’FFFFh
02’0000h to 02’FFFFh
03’0000h to 03’FFFFh
04’0000h to 04’FFFFh
05’0000h to 05’FFFFh
06’0000h to 06’FFFFh
07’0000h to 07’FFFFh
08’0000h to 08’FFFFh
16
8
8
32
64
64
64
64
64
64
64
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Instruction s and Command s
All operations besides normal read operations are
initiated and controlled by command sequences
wr i tte n to the Fl a sh C om ma n d I nter fac e ( CI) . T h e
Command Interface (CI) interprets words written
to the Flash memory and enables one of the
foll owi ng operations:
– R ead memor y array
– P rogram Word
– Block Erase
– Chip Erase
– E ras e Su spend
– E ras e Resum e
– B lock Pro tection
– B lock Tem porary Unprot ection
– Code Protection
Commands are composed o f several write cycles
at specific addresses of the Flash memory. The
different write cycles of such command
sequences offer a fail-safe feature to protect
against an inadvertent wri te.
A command only starts when the Command
Interface has decoded the last write cycle of an
operation. Until tha t last wr ite is perfor med, Flas h
memo ry r emains in Read Mo de
Notes: 1. As it is not possible to perform write
operations in t he Flash while fetching c ode
from Flash, the Flash commands must be
written by instructions executed from
internal R A M or external me mory.
2. Command write cycles do not need to
be consecutively received, pauses are
allowed, save for Block Erase command.
During this operation all Erase Confirm
commands must be sent to complete any
block erase operation before time-out
period expires (typically 96µs). Command
sequencing must be followed exactly. Any
inval i d combination of commands will reset
the Command Interface to Read Mode.
Status R egister
This register is used to flag the status of the
memory and the result of an operation. This
register can be accessed by read cycles during
the Erase-Program Controller (EPC) operation.
Erase Operation
This Flash memory features a block erase
architecture with a chip er ase cap abi lit y too. Erase
is accomplished by executing the six cycle erase
command sequence. Additional command write
cycles can then be perfor med to erase more than
one bloc k in parall el. When a time-out period elaps
(96
µ
s) after the last cycle, the Erase-Program
Controller (EPC) automatically starts and times the
erase pulse and executes the erase operation.
There is no need to program the block to be
erased with ‘0000h’ before an erase operation.
Termination of operation is indicated in the Flash
status register. After erase operation, the Flash
memor y locations are read as 'FFFFh’ value.
Erase Suspend
A block erase operation is typically executed
within 1.5 second f or a 64K Byte bloc k. Erasure of
a memory block may be suspended, in order to
read data from another block or to program dat a in
anoth er block, and then resumed.
In-System P rogramming
In-system programming is fully supported. No
spec ial pr ogramming voltage is required. Because
of the automatic execution of erase and
programming algorithms, write operations are
reduced to transferri ng commands and data to the
Flash and reading the status. Any code that
programs or erases Flash mem ory lo cations (that
writes data to the Flash) must be executed from
memory outside the on-chip Flash memory itself
(on-chip RAM or external memory).
A boot mechanism is provided to support
in-system progra mming. It works using serial link
via USART interface and a PC compatible or
other programming host .
Read/W rite Protection
The Flash module supports read and write
protection in a very comfortable and advanced
protection functionality. If Read Protection is
installed, the whole Flash memory is protected
against any "external" read access; read
accesses are only possible with instructions
fetched directly from program Flash memor y. For
update of the Flash m emory a temporary disable
of Fl ash Read Protection is supported.
The device also features a block write protection.
Software locking of selectable memory blocks is
provided to protect code and data. This feature
will dis able b oth program and e ras e operations in
the selected block(s) of the memory. Block
Protection is accomplished by block specific
lock-bit which are programmed by executing a
four cycle command sequence. The locked state
of blocks is indicated by specific flags in the
according block status registers. A bloc k may only
be temporarily unlocked for update (write)
operations.
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Wi th the two possibilities for write protection whole
memory or block specific a flexible installation of
write protection is supported to protect the Flash
memory or parts of it from unauthorized
programming or erase accesses and to provide
virus-proof protection for all system code blocks.
All write protection also is enabled during boot
operation.
Pow er Su pply, Reset
The F lash modul e uses a si ngle power supply for
both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations from 5V supply.
Once a program or erase cycle has been com-
pleted, the device resets to the standard read
mode. At power-on, the Flash memory has a
setup phase of some microseconds (dependent
on t he power s upply ramp-up). During this phase,
Flash can not be read. Thus , if EA pi n i s high (ex e-
cution will s tart from Flash m emory), the CPU wil l
remains in reset state until the Flash can be
accessed.
5.3 - Arch i tectural Description
The Flash module distinguishes two basic
operating modes, the standard read mode and the
command mode. The initial state after power-on
and after reset i s the standard read mode.
5.3.1 - Read Mode
The Flash module enters the standard operating
mode, the read mode:
– After Reset command
– A f ter every completed erase operation
– A f ter every completed programm ing operation
– After every other completed command
execution
– Few microseconds after a CPU-reset has
started
– After incorrect address and data values of
command sequences or writing them in an
improper sequence
– After incorrect write access to a read protected
Flash memory
The read mode remains active until the last
command of a command sequence is decoded
which starts directly a Flash array op eration, such
as:
– eras e one or several blocks
– program a word into Flash array
– prot ect / temporary unprotect a block.
In the standard read mode read accesses are
directly controlled by the Flash memory array,
delivering a 32-bit double Word from the
addressed position. Read accesses are always
aligned to double Word boundaries. Thus, both
low order address bit A1 and A0 are not used in
the Fla sh array for read ac cess es. The high order
address bit A18/A17/A16 define the physical
64K Bytes segment being accessed within the
Flash array.
5.3.2 - Command Mode
Every operat i on besides standard read operations
is initiated by commands written to the Flash
command register. The addresses used for
command cycles define in conjunction with the
actual state the specific step within command
sequences . Wit h the last command of a command
sequence, the Erase-Program Controller (EPC)
starts the execution of the command. The EPC
stat us is indicated during com man d execut ion by:
– T he Stat us Register,
– The Ready/Busy signal .
5.3.3 - Flash Status Register
The Flash Status register is used to flag the status
of the Flash memory and the result of an
operation. This register can be accessed by Read
cycles during the program-Erase Controller
operations. The program or erase operation can
be controlled by data polling on bit FSB.7 of
Status Regist er, detection of Toggle on FSB.6 and
FSB.2, or Error on FSB.5 and Erase Timeout on
FSB.3 bit. Any read attempt i n Flash during EPC
operation will automatically output these five bits.
The EPC sets bit FSB.2, FSB.3, FSB.5, FSB.6
and FSB.7. Other bit are reserved for future use
and sho uld be masked.
ST10F280
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Flash S tatus (see note for address)
Note: The Address of Flash Status Register is the address of the word being programmed when
Programming operation is in progress, or an address within block being erased when Erasing
operation is in progress.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- FSB.7 FSB.6 FSB.5 - FSB.3 FSB.2 - -
RRR R R
FSB.7 Flash Status bit 7: Data Polling Bit
Programming Operation: this bit outputs the complement of the bit 7 of the word being
prog ram m e d, an d after com ple t ion , w ill ou t pu t the b it 7 of the wo rd progr a mm ed .
Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion.
If the bloc k selected for erasure is (are) protected, FSB.7 will be set to ‘0’ f or about 100 µs, and
then return to the pre vious addres sed memory data value.
FSB.7 will also flag the Erase Suspend Mode by switching from ‘0’ to ‘1’ at the start of the
Erase Suspend.
During P rogram operation in Erase Susp end M ode, FSB.7 will have the same behaviour as in
nor m al Program execution outside the Suspend mod e.
FSB.6 Flash St at us bi t 6: Toggl e Bit
Programming or Erasing Operations: successive read operations of Flash Status register will
deliver complementar y values. FSB.6 will toggle each time the Flash Status register is read .
The Program operation is completed when two successive reads yield the same value. The
next read will output the bit last programmed, or a ‘1’ after Erase operatio n
FSB.6 will be set to‘1’ if a read operation is attempted on an Erase Suspended block. In
addition , an Erase Suspend/R esu me comma nd w ill caus e FS B.6 to toggl e.
FSB.5 Flash Status bit 5: Erro r Bit
This bit is set to ‘1’ when there is a failure of Program, block or ch ip erase operations.This bit
will also be set if a user tries to program a bit to ‘1’ to a Flash location that is currently
programmed wit h ‘0’.
The error bit resets after Read/Reset instruction.
In case o f succ ess, the Error bit w ill be s et to ‘0’ during Program or Erase and then will o u tput
the bit la st programmed or a ‘1’ after erasing
FSB.3 Flash Status bit 3: Erase Time-out Bit
This bit is cleared by the EPC when the last Block Era se co mmand has been en tered to the
Command Interface and it is awaiting the Erase start. When the time-out period is finished,
after 96 µs, FS B.3 returns back to ‘1’.
FSB.2 Flash St at us bi t 2: Toggl e Bit
This toggle bit, together with FSB .6, can be used to determ ine the chip status during the Erase
Mode or Erase Suspend Mode. It can be used also to identify the block being Erased
Suspended. A R ead operation wil l cause FSB.2 to Toggle du ring the Erase Mode. If the Flash
is in Erase Suspend Mode, a Read operation from the Erase suspended block or a Progra m
operation into the Erase susp ended block will cause FSB.2 to toggle.
When the Fl ash is in Prog ram Mode during Erase Suspend, FSB.2 will be read as ‘1’ if addr ess
used is the address of the word being progra mmed.
After Erase completion with an Error status, FSB.2 will toggle when reading the faul ty sector.
ST10F280
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5.3.4 - Flash Protection Register
The Flash Protection register is a non-volatile register that contains the protection status. This register
can be read by using the Read Protection Status (RP) command, and programmed by using the dedi-
cated S et Protection com ma nd.
Flash Protection Register (PR)
5.3.5 - Instructions Description
Twelve instructions dedicated to Flash memory
accesses are defined as follow:
Read/Reset (RD). The Read/Reset instruction
consist of one write cycle with data XXF0h . it can
be optionally preceded by two CI enable
coded
cycles (data xxA8h at address 1554h + data
xx54h at address 2AA8h). Any successive read
cycle followin g a Read/Reset instruction will read
the memory array. A Wait cycle of 10µs is
necessary after a Read/Reset command if the
mem ory was in program or Erase mode.
Program Word (PW). This instruction uses four
wri te cy cl es. Afte r the t wo Cl enabl e coded cycl es,
the Program Word command xxA0h is written at
address 1554h. The followi ng write cycl e will latch
the address and data of the word to be
pro gram med. Mem ory programming can be do ne
only by writing 0's instead of 1's, otherwise an
error occurs. During programming, the Flash
Status is checked by reading the Flash Status bit
FSB.2, FSB.5, FSB.6 and FSB.7 which show the
status of the EPC. FSB.2, FSB.6 and FSB.7
determine if programming is on going or has
comple ted, and FSB.5 allows a check to be made
for any possible error.
Block Erase (BE). This instruction uses a
minimum of six command cycles. The erase
enable command xx80h is written at address
1554h after the two-cycle CI enable sequence.
The erase confirm cod e xx30h must be written at
an address related to the block to be erased
pre ceded by the executi on of a s econd CI enabl e
sequence. Additional erase confirm codes must
be given to erase m ore than on e block in p arallel.
Additional erase confirm commands must be
wr itten within a def ined time-ou t perio d. The input
of a new Block Erase command will restart the
time-ou t period.
W hen this time-out period has elapsed, the erase
starts. The status of the internal timer can be
monitored through the level of FSB.3, if FSB.3 is
‘0’, the Block Erase command has been giv en and
the timeout is running; if FSB.3 is ‘1’, the timeout
has ex pired and the EPC is erasing the block(s).
If the second comm and given is not an erase con-
firm or if the coded cycles are wrong, the instruc-
tion abort s, and the device is reset to Read Mode .
1514131211109876543 210
CP ----BP10 BP9 BP8 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0
RW RW RW RW RW RW RW RW RW RW RW RW
BPx Block x Protection bit (x = 0...10)
‘0’: the Block Protection is enabled for block x. Programming or erasing the block is not
possible, unless a Block Temporary Unprotection command is issued.
1’: the Block Protection is disabled for block x.
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the
Block Protection using the Block Temporary Unprotection instruction.
CP Code Protection Bit
‘0’: the Flash Code Protection is enabled. Read accesses to the Flash for execution not
performed in the Flash itself are not allowed, the returned value will be 009Bh, whatever the
content of the Flash is.
1’: the Flash Code Protection is disabled: read accesses to the Flash from external or internal
RAM are allowed
Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Protection
command but then cannot be set to ‘1’ again. It is therefore possible to temporarily disable the
Code Protection using the Code Temporary Unprotection instruction.
ST10F280
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It is not necessary to program the block with
0000h as the EPC will do this automatically bef ore
the erasing to FFFFh. Read operations after the
EPC has started, output the Flash Status Regis-
ter. Du rin g the execution of the erase by t he E PC,
the device accepts only the Erase Suspend and
Read/Reset instructions. Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The To ggle bit FSB.2 and
FSB.6 toggle during the erase operation. They
stop when erase is completed. After completion,
the Error bit FSB.5 returns ‘1’ i f there has been an
erase failure because erasure has not completed
even after the maximum number of erase cycles
have been executed by the EPC, in this case, it
will be necessary to input a Read/Reset to the
Command Interf ace in order to reset the EPC.
Chip Erase (CE). This instruction uses six write
cycles. The Erase Ena ble command xx80h, must
be written at address 1554h after CI-Enable
cycles. The Ch ip Erase com mand xx10h must be
given on the sixth cycle after a second C I-Enabl e
sequence. An error in command sequence will
reset the CI to Read mode. It i s NOT necessary to
program the block with 00 00h as the EPC will do
this automatically before the erasing to FFFFh.
Read operations after the EPC has st arted output
the Flas h Status Register. During the execution of
the erase by the EPC, Data Polling bit FSB.7
returns ‘0’ while the erasure is in progress, and ‘1’
when it has completed. The FSB.2 and FSB.6 bit
toggle during the erase operation. They stop when
erase is f inished. The FSB.5 error bit returns "1" in
case of failure of the erase operation. The error
flag is set after the maximum number of erase
cycles have been executed by the EPC. In this
case, it will be necessary to i nput a Read/Reset to
the Comma nd Interface in order to reset the EPC.
Erase Suspend (ES). This instruction can be
used to suspend a Block Erase operation by
giving the command xxB0h without any specific
address. No CI-Enable cycles is required. Erase
Suspend operation allows reading of data from
another block and/or the programming in another
block while erase is in progress. If thi s command
is given during t he t ime-out peri od, it will terminate
the time-out period in addition to erase Suspend.
The Toggle Bit FSB.6, when monitored at an
address that belongs to the block being erased,
stops togg ling when Erase Suspend Com mand is
effective, It happens between 0.1µs and 15µs
after the Erase Suspend Command has been
written. The Flash will then go in normal Read
Mode, and read from blocks not being erased is
valid, while read from block being erased will
output FSB.2 toggling. During a Suspend phase
the o nly instructions valid are Erase Resum e and
Program Word. A Read / Reset instruction d uring
Erase s uspend wi ll definitely abor t th e Erase a nd
result in invalid data in the block being erased.
Erase Resume (ER). This instruction can be
given when the memory is in Erase Suspend
State. Erase can be resumed by writing the
command xx30h at any address without any
Cl-enable sequence .
Program during Erase Suspend. The Program
Word instruction during Erase Suspend is allowed
only on bl oc ks that ar e not Er as e-suspended. This
instruction is the same than the Program Word
instruction.
Set Protect ion (SP). T his instruct i on can be used
to enable both Block Protection (to protect each
block independently from accidental Erasing-Pro-
gramming Operation) and Code Protection (to
avoid code dump). The Set Protection Command
must be given after a special CI-Protection Enab le
cycles (see instruction table). The following Write
cycle, will progr am the Pro tec tion Registe r . To pro-
tect the bloc k x (x = 0 to 10), the data bit x must be
at ‘0 ’. To protec t the cod e, bit 15 of t he data must
be ‘0’. Enabling Block or Code Protection is per-
manent and can be cleared only by STM. Block
Temporary Unprotection and Code Temporary
Unprotec tion instruct ions are a v ailable to all ow the
customer to update the code.
Note: 1. The new value programmed in
prot ection register will only become active
after a reset.
2. Bit that are already at ’0’ in protection
register must be confirmed at ’0’ also in
data latched during the 4th cycle of set
protection command, otherwise an error
may o ccu r.
Read Protection Statu s (RP). This inst ruction is
used to read the Block Protection status and the
Code Protection status. To read the protection
register (see Table 3), the CI-Protection Enable
cycles must be executed followed by the
command xx90h at address x2A54h. The
following Read Cycles at any odd word address
will output the Bl ock Protection Status. The Read/
Reset command xxF0h must be written to reset
the protection interface.
Note: After a modification of protection register
(using Set Protection command), t he Read
Protection Status will return the new PR
value only aft er a reset.
ST10F280
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Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the
blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block
Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The
Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset
comm and x xF0h.
Set Code Prote ction (SCP). This kind o f protection allows the customer to protect the propr ietary co de
written in Flash. If installed and active, Flash Code Protection prevents data operand accesses and
program branches into the on-chip Flash area from any location outside the Flash memory itself. Data
operand accesses and branches to Flash locations are only and exclusively allowed for instructions
ex ecuted from the Flash memory itself. Every read or jump to Flash performed from another memory (lik e
internal RAM, external memory) while Code Prot ection is enabled, will give the opcod e 009Bh related to
TRAP #00 ill egal instruction. The CI-Prot ection Enab le cycl es must be sent to set the Code Prot ec tion. By
wr iting da ta 7FFF h at any odd word address, the Code Protecte d status is stored in the Flash Prot ecti on
Register (PR). Protection is permanent and cannot be cleared by the user. It is possible to temporarily
disable the Code Protection using Code Te mpo rary Unprotec tion instr uction.
Note: Bi ts that are already at ’ 0’ in protection register m us t be c onfirmed at ’0’ also in data l at ched during
the 4th cycle of set protection comm and, othe rwise an error may occur.
Code Temporary Unprotection (CTU). This instruction must be used to temporary disable Code
Protection. This instruction is effective only if executed from Flash memory space. To restore the
protection status, without using a reset, it i s necess ary to use a Code Temporar y P ro tection inst ruction.
Syste m reset will reset also the Code Temporary Unprotected status. The Code Temporary Unprotection
comm and consists of the following wr ite cycle:
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside memory space, Rn is a regis ter loaded with data 0FFF Fh.
Code Tem pora ry P rotection ( C TP). This i nstruction al lo ws t o restore Code Protection. This operation is
effective only if executed from Flash memory and is necessary to restore the protection status after the
use of a Code Temporary Unprotecti on instructi on.
The Code Tem porary Protection command c onsist s of the fol lowing write cycle:
MOV MEM, Rn ; This instruction MUST be executed from Flash memory space
W here MEM is an absolute address inside memory space, Rn is a regis ter loaded with data 0FFF Bh.
Note that Code Temporary Unprotection instruction must be used when it is necessary to modify the
Flash with protected code (SCP), since the write/erase routines must be executed from a memory
external to Flash space. Usually, the wr ite/erase routines, executed in RAM, ends w ith a ret urn t o Flash
spa ce where a CTP instruction restore the protection.
ST10F280
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Table 3 : Instr uctions
Notes 1. Address bi t A14, A15 and a bove are don’t c are for coded address inputs.
2. X = Do n’ t Care.
3. WA = Write Address: ad dress of me m ory location t o be progra m m ed.
4. WD = Write Data: 16-bit dat a to be program m ed
5. Optional , add iti onal block s addresses m ust be entered within a t i me-out delay (96 µs) after l ast w rite entry, t i meout st atus can be
veri fied through FSB.3 val ue. When full command i s entered, read Dat a Poll i ng or Toggle bit until Erase is co m pl eted or su spended.
6. Read Data Polling or Tog gle bit until Eras e completes.
7. WP R = Write protec tion regi ster. To prot ect co de, bi t 15 of WPR must be ‘0’. To protec t block N (N=0,1,...), bit N of WPR must be
‘0’. Bit that are already at ‘0’ in protection register mu st also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0 ’).
8. MEM = any add ress insid e the F lash m emor y s pace. Ab so lute add res sing m ode m ust be use d (MOV MEM, Rn) , and ins tru ction
must be executed from Flash m emory spa ce.
9. Odd word addr ess = 4n-2 w here n = 0, 1, 2, 3. .., ex. 0002h, 0006h.. .
Instruction Mne Cycle 1st
Cycle 2nd
Cycle 3rd
Cycle 4th Cycle 5th
Cycle 6th
Cycle 7th
Cycle
Read/Reset RD 1+ Addr.1X 2Read Memory Array until a new write cycle is initiated
Data xxF0h
Read/Reset RD 3+ Addr.1x1554h x2AA8h xxxxxh Read Memory Array until a new write
cycle is initiated
Data xxA8h xx54h xxF0h
Program Word PW 4 Addr.1x1554h x2AA8h x1554h WA 3Read Data Polling or
Toggle Bit until Program
completes.
Data xxA8h xx54h xxA0h WD 4
Block Erase BE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h BA BA’ 5
Data xxA8h xx54h xx80h xxA8h xx54h xx30h xx30h
Chip Erase CE 6 Addr.1x1554h x2AA8h x1554h x1554h x2AA8h x1554h Note 6
Data xxA8h xx54h xx80h xxA8h xx54h xx10h
Erase Suspend ES 1 Addr.1X2Read until Toggle stops, then read or program all data needed
from block(s) not being erased then Resume Erase.
Data xxB0h
Erase Resume ER 1 Addr.1X2Read Data P olling or Toggle bit until Erase completes or Erase
is supended another time.
Data xx30h
Set Block/Code
Protection SP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9
Data xxA8h xx54h xxC0h WPR 7
Read
Protection
Status RP 4
Addr.1x2A54h x15A8h x2A54h Any odd
word
address 9Read Protection Register
until a new write cycle is
initiated.
Data xxA8h xx54h xx90h Read
PR
Block
Temporary
Unprotection BTU 4 Addr.1x2A54h x15A8h x2A54h X2
Data xxA8h xx54h xxC1h xxF0h
Code
Temporary
Unprotection CTU 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFFh
Code
Temporary
Protection CTP 1 Addr.1MEM 8Write cycles must be executed from Flash.
Data FFFBh
ST10F280
29/186
– Generally, command sequences cannot be
written to Flash by in structions fe tched from the
Flash itself. Thus, the Flash commands m ust be
written by instructions, executed from internal
RAM or external memo ry.
– Command cycles on t he CPU interface need not
to be consecutively receive d (pauses allowed).
The CPU interface delivers dummy read data for
not used cycles within command se quences .
– All addresses of command cycles shall be
defined only with Register-indirect addressing
mode in the acco rding move inst ru cti o ns. Direct
addressing is not allowed for command
sequences. Address segment or data page
pointer are taken in to accoun t for the com ma nd
address value.
5.3.6 - Reset Processing and Initial State
The Flash m odule distingui shes two kinds of CPU
reset types
The lengtheni ng of CPU reset:
– Is not reported to external devices by
bidirectional pin
– Is not enabled in case of external start of CPU
after reset.
5.4 - Flash Memory Configuration
The default memory configuration of the
ST10F280 Memory is determined by the state of
the EA pin at reset. This value is stored in the
Internal ROM Enable bit (named ROMEN) of the
SYSCON register.
When ROMEN = 0, the interna l Flash is disabled
and external ROM is used for startup control.
Flash m em ory can la ter be enabled by setting t he
ROMEN bit of SYSCON to 1. The code
performing this setting must not run from a
seg men t of the extern al ROM to be replaced by a
segment of the Flash memory, otherwise
unexpected behaviour may occu r.
For example, if external ROM code is located in
the first 32K Bytes of segment 0, the first
32K Bytes of the Flash must then be enabled in
seg men t 1. This is done by s etting the ROMS1 bit
of SYSCON to 0 before or simultaneously with
setting of ROMEN bit. This must be done in the
externally supplied program before the execution
of the EINIT instruct ion.
If progra m execution starts from external me mory,
but access to the Flash memory mapped in
segment 0 is later required, then the code that
performs the setting of ROMEN bit must be
executed either in the segment 0 but above
addres s 00’8000h, or from the inter nal RAM.
Bit ROMS1 only affects the mapping of the first
32K Bytes of the Flash memor y. All other parts of
the Flash memory (addresses 01’8000h
08’FFFFh) remain unaf f ect ed.
The SGT DIS Segmentation Disable / E nabl e m ust
also be set to 0 to allow the use of the full
512K Bytes of on-chip memory in addition to the
external boot memory. The correct procedure on
changing the segment ation registers must also be
obs erved to prevent an unwant ed trap condition:
– Instructions that configure the internal memory
must only be executed from external memory or
from the internal RAM.
– An Absolute Inter-Segment Jump (JMPS)
instruction must be executed after Flash
enabling, to the next instruction, even if this next
instruction is located in the consecut ive address.
– Whenever the internal Memory is disabled,
enabled or remapped, the DPPs must be
explicitly (re)loaded to enable correct data
accesses to the internal memory and/or external
memory.
5.5 - Application Examples
5.5.1 - Handling of Flash Addresses
All comman d, Block, Data and registe r addresses
to the Flash have to be located within the active
Flash memory space. The active space is that
address range to which the physical Flash
addresses are mapped as defined by the user.
When using data page pointer (DPP) for block
addresses make sure that address bit A15 and
A14 of the block address are reflected in both
LSBs of the selected DPPS.
Note: - For Command Instructions, address bit
A14, A15, A16, A17 and A18 are don’t
care. This simplify a lot the application
software, because it minimize the use of
DPP registers when using Command in
the Command Interface.
- Direct addressing is not allowed for
Command sequence operations to the
Flash. Only Register-indirect addressing
can be used for command, block or
write- dat a accesses.
ST10F280
30/186
5.5.2 - Basic Flash Access Control
When accessing the Flash all command write addresses have to be located within the active Flash
memory space. The active Flash memory space is that logical address range which is covered by the
Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that
address bi t A15 and A14 of the command addresses are reflected in both LSBs of t he selected data page
pointer (A15 DPPx.1 and A14 DPPx.0).
In case of the command write address es, address bit A14, A 15 and above are don’t care. Thus, command
wr ites can be performed by onl y us ing one DPP registe r. T his a llow to have a more sim ple and com pac t
application sof tware.
Another advantageou s possibi lity is to use the extended s egm ent instru ction fo r addressin g.
Note: The direct addressing mode is not allowed for write access to the Flash address/command
register. Be aware that the C compiler may use this kind of addressing. For write accesses to
Flash modu le always the indirect add ressing mode has to be selected.
The following basic instruction sequences show examples for di fferent addressing possibilities.
Princi ple example of address generation f or Flash comman ds and registers:
W hen using data page pointer (D PP0 is this examp le)
MOV DPP0,#08h ;adjust data page pointers according to the
;addresses: DPP0 is used in this example, thus
;ADDRESS must have A14 and A15 bit set to ‘0’.
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address 2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwn,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV [Rwm],Rwn;indirect addressing
W hen using the extended segm ent instr uctio n:
MOV Rwm,#ADDRESS ;ADDRESS could be a dedicated command sequence
;address (2AA8h, 1554h ... ) or the Flash write
;address
MOV Rwo,#DATA ;DATA could be a dedicated command sequence data
;(xxA0h,xx80h ... ) or data to be programmed
MOV Rwn,#SEGMENT ;the value of SEGMENT represents the segment
;number and could be 0, 1, 2, 3 or 4 (depending
;on sector mapping) for 256KByte Flash.
EXTS Rwn,#LENGTH ;the value of Rwn determines the 8-bit segment
;valid for the corresponding data access for any
;long or indirect address in the following(s)
;instruction(s). LENGTH defines the number of
;the effected instruction(s) and has to be a value
;between 1...4
MOV [Rwm],Rwo;indirect addressing with segment number from
;EXTS
ST10F280
31/186
5.5.3 - Programmin g Exa mples
Most of the microcontroller programs are written in the C language where the data page pointers are
automati cally set by the compiler. But because the C compile r ma y use the not allow ed direct addressing
mode for Flash writ e addresses, it is necessary to program the organisational Flas h accesses (comm and
seq uences) with assembler in-line routines which use indirect addressing.
Example 1 Performing the comm and Read/Res et
We assume that in the initialization pha se the l owest 32K Bytes of Flash memory (sector 0) have been
mapp ed to segm ent 1.
According t o the usual way of ST10 data addressi ng with data page pointers , address bit A15 and A14 of
a 16-bi t command write address select the data page pointer (DPP) w hich contain s the upp er 10-bit for
building the 24-bit physical data address. Address bit A13...A0 represent the address offset. As the bit
A14... A18 are "don’t care" when written a Flash command in the Command Interface (CI), we can choose
the mos t convenian t DPPx register for address hand ling.
The following examples are making usage of DPP0. We just have to make sure, that DPP0 points to
active Flash memory space.
To be independent of mapping of sector 0 we choose for all DPPs which are used for Flash address
handling, to point to segment 2.
For this reason we load DPP0 with value 08h (00 0000 l000b).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SCXT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0F0h ;load register R7 with Read/Reset command
MOV [R5], R7 ;command cycle 3. Address is don’t care
POP DPP0 ;restore DPP0 value
In the example above the 16-bit registers R5 and R6 are used as auxilary registers for indirect
addressing.
Example 2 Performing a Program Word c om man d
We assume that in the initialization pha se the l owest 32K Bytes of Flash memory (sector 0) have been
mapp ed to se gme nt 1.The dat a to be wri tten is lo aded i n register R13, the a ddress to be programme d is
loaded in register R11/R12 (segment number in R11, segment offset in R12).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #0A0h ;load register R7 with Program Word command
MOV [R5], R7 ;command cycle 3
ST10F280
32/186
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment to be programmed
;R12 contains the segment offset address to be
;programmed
;R13 contains the data to be programmed
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R13 ;command cycle 4: the EPC starts execution of
;Programming Command
Data_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
MOV R6, R7 ;save it in R6 register
;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.7)
XOR R7, R13
JNB R7.7, Prog_OK
;Check if FSB.5 = 1 (Programming Error)
JNB R6.5, Data_Polling
;Programming Error: verify is Flash programmed
;data is OK
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = Data.7
XOR R7, R13
JNB R7.7, Prog_OK
;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Prog_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When programming operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Prog_OK:
....
....
ST10F280
33/186
Example 3 Performing t he Block Erase com man d
We assume that in the initialization pha se the l owest 32K Bytes of Flash memory (sector 0) have been
mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased
(segment number in R11, segment of fset in R12, f or example R11 = 01h, R12= 4000h wil l erase the bloc k
1 first 8K byte block).
MOV R5, #01554h ;load auxilary register R5 with command address
;(used in command cycle 1)
MOV R6, #02AA8h ;load auxilary register R6 with command address
;(used in command cycle 2)
SXCT DPPO, #08h ;push data page pointer 0 and load it to point ;to
;segment 2
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 1
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 2
MOV R7, #080h ;load register R7 with Block Erase command
MOV [R5], R7 ;command cycle 3
MOV R7, #0A8h ;load register R7 with 1st CI enable command
MOV [R5], R7 ;command cycle 4
MOV R7, #054h ;load register R7 with 2cd CI enable command
MOV [R6], R7 ;command cycle 5
POP DPP0 ;restore DPP0: following addressing to the Flash
;will use EXTended instructions
;R11 contains the segment of the b lock to be erased
;R12 contains the segment offset address of the
;block to be erased
MOV R7, #030h ;load register R7 with erase confirm code
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;command cycle 6: the EPC starts execution of
;Erasing Command
Erase_Polling:
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV R7, [R12] ;read Flash Status register (FSB) in R7
;Check if FSB.7 = ‘1’ (i.e. R7.7 = ‘1’)
JB R7.7, Erase_OK
;Check if FSB.5 = 1 (Erasing Error)
JNB R7.5, Erase_Polling ;Programming failed: Flash remains in Write
;Operation.
;To go back to normal Read operations, a Read/Reset
;command
;must be performed
Erase_Error:
MOV R7, #0F0h ;load register R7 with Read/Reset command
EXTS R11, #1 ;use EXTended addressing for next MOV instruction
MOV [R12], R7 ;address is don’t care for Read/Reset command
... ;here place specific Error handling code
...
...
;When erasing operation finished succesfully,
;Flash is set back automatically to normal Read Mode
Erase_OK:
....
....
ST10F280
34/186
5 .6 - Boot st rap Loa der
The built-in bootstrap loader (BSL) of the
ST10F280 provides a mechanism to load the
startup program through the serial interface after
reset. In this case, no external memor y or internal
Flash memory is required for the initialization
code starting at location 00’0000h (see Figure 5).
The bootstrap loader moves code/data into the
internal RAM, but can also transfer data via the
serial interface into an external RAM using a
second level loader routine. ROM Memory
(internal or external) is not necessary, but it
may be used to provide lookup tables or
“core-code” like a set of general purpose
sub routines for I/O operations, number cru nching,
system initialization, etc.
The bootstrap loader can be used to load the
complete application software into ROMless
systems, to load temporary software into
complete systems for testing or calibration, or to
load a programming rout i ne for Flash devices.
The BSL mechanism can be used for standard
system startup as well as for special occasions
like system maintenance (firmer update) or
end-of-line programming or testing.
5.6.1 - Entering the Bootstrap Loader
The ST10F280 e nters BSL mod e when pin P0L. 4
is s ampled low at t he end o f a hardware rese t. In
this case the built-in bootstrap l oader is activated
independent of the selected bus mode.
The bootstrap loader code is stored in a special
Boot-ROM. No part of the standard mask Memory
or Flash Memory area is required for this.
After entering BSL mode and the respective
initialization the ST10F280 scans the RxD0 l ine to
receive a zero Byte, one start Bit, eight ‘0’ data
Bits and one stop Bi t .
From the duration of this zero Byte it calculates
the corresponding Baud rate f a ctor with respect to
the current CPU clock, initializes the serial
interface ASC0 accordingly and switches pin
TXD0 to output.
Using this Baud rate, an identification Byte is
returned to the host that provides the loaded dat a.
This identification Byte identifies the device to be
booted. Identification byte is D5h for the
ST10F280.
Fi gure 5 : Bootstrap Loader Sequence
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSTIN
TXD0
Internal Boot Memory (BSL) routine 32 Byte user software
2)
3)
RxD0
CSP:IP
4)
6)
P0L.4
1) BSL initialization time
2) Zero Byte (1 start Bit, eight ‘0’ data Bits, 1 stop Bit), sent by host.
3) Identification Byte (D5h), sent by ST10F280.
4) 32 Bytes of code / data, sent by host.
5 ) Caution: T XD0 is onl y driven a certain tim e a fter reception of the zero Byt e.
6) Int e rnal Boo t ROM.
1)
5)
ST10F280
35/186
W hen the S T1 0F280 has ent ered BS L m ode, the following configuration is automat ically set (values that
deviate from the normal reset val ues, are
marked
):
In this case, the watchdog timer is disabled, so the
bootstrap loading sequence is not time limited.
Pin TXD0 is configured as output, so the
ST10F280 can return the identification Byte.
Even if the internal Flash is enabled, no c ode c an
be execu ted out of it.
The h ardware that activate s the B SL during reset
may be a simple pull-down resistor on P0L.4 for
systems that use this feature upon every
hardware reset.
A switchable solution (via jumper or an external
signal) can be used for systems that
only temporarily use the bootstrap loader (see
Figure 6).
After sending the identification Byte the
ASC0 receiver is enabled and is ready to
receive the initial 32 Bytes from the host. A half
duplex connection is therefore sufficient to feed
the BSL .
5.6.2 - Memor y Configuration After Reset
The configuration (and the accessibility) of the
ST10F280’s memory areas after reset in
Bootstrap-Loader mode differs from the standard
case. Pin EA is n ot evaluated when BSL mode is
selec ted, and accesses to t he inter nal Flash area
are partly redirected, while the ST10F280 is in
BSL mode (see Figure 7). All code fetches are
made from the special Boot-ROM, while data
accesses read from the internal user Flash. Data
accesses will return undefined values on
ROMless devices.
The code in the Boot-ROM is not an invariant
feature of the ST10F280. User software should
not try to execute code from the internal Flash
area while the BSL mode is still active, as these
fetches will be redirected to the Boot-ROM. The
Boot-ROM will also “move” to segment 1, when
the internal Flash area is mapped to segment 1
(see Figure 7).
Watchdog Timer:
Disabled
Register SYSCON: 0E00h
Context Pointer CP: FA00h Register STKUN: FA40h
Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C
Register S0CON:
8011h
Register BUSCON0: acc. to startup configuration
Register S0BG: Acc. to ‘00’ Byte P3.10 / TXD0: ‘1’
DP3.10: ‘1’
Fi gure 6 : Hardware Provisi ons to Activate the B SL
RPOL.4
8kΩ
Circuit 1
POL.4 POL.4 Normal Boot
BSL
External
Signal
RPOL.4
8kΩ
Circuit 2
ST10F280
36/186
Fi gure 7 : Memory Configuration After Reset
5.6.3 - Loading the Startu p Code
After sending the identification Byte the BSL
enters a loop to receiv e 32 Bytes via A SC0. These
Byte are stored sequentially into locations
00’FA40h through 00’FA5Fh of the internal RAM.
So up to 16 instructions may be placed into the
RAM area. To execute the loaded code the BSL
then jum ps to location 00’FA40h, which is the first
loaded inst ruct ion.
The bootstrap loading sequence is now
ter minated, the ST10 F280 remains in BSL mo de,
howe ver. Most probably the initially loaded routine
will load additional code or data, as an average
application is likely to require substantially more
than 16 instructions. This second receive loop
may directly use the pre-initialized interfa ce ASC0
to receive data and store it to arbitrary
user -defined locations.
This sec ond level of loade d code may be t he f ina l
application code. It may also be another, more
sophisticated, loader routine that adds a
transmission protocol to enhance the integrity of
the loaded code or data. It may also contain a
code sequence to change the system
conf i guration and enable t he bus i nterface to store
the receiv ed data int o ext ernal memory.
This process m ay go t hrough several iterations or
may directly execute the final application. In all
cases the ST10F280 will still run in BSL mode,
that m eans with the watchdo g timer disable d and
limi t ed access to the internal Flash area.
All code fetches from the internal Flash area
(00’0000h...00’7FFFh or 01’0000h...01’7FFFh, if
mapped to segment 1) are redirected to the
special Boot-ROM. Data fetches access will
access the i nternal Boot -R OM of th e ST10F280, if
any is available, but will return undefined data on
ROMless devices.
5.6.4 - Exiting Bootstr ap Lo ader Mode
In order to execute a program in normal mode, the
BSL mode must be terminated first. The
ST 10F280 exit s BSL mode upon a software reset
(ignores the level on P0L.4) or a hardware reset
(P0L.4 mu st be h igh). After a res et the ST 10F2 80
will start executing from location 00’0000h of the
internal Flash or the external memory, as
programm ed via pi n EA.
16 MBytes 16 MBytes 16 MBytes
BSL mode active Yes (P0L.4=’0’) Yes (P0L.4=’0’) No (P0L.4=’1’)
EA pin High Low Access to application
Code fetch from internal
Flash area Test-Flash access Test-Flash access User Flash access
Data fetch from internal
Flash area User Flash access User Flash access User Flash access
IRAM
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
disabled
internal
enabled
Flash
1
0
User
Flash
Test
Flash
Segment
2
255
Access to:
external
bus
enabled
internal
enabled
Flash
IRAM 1
0User
Flash
Segment
2
255
Access:
depends on
reset config
EA, Port0
depends on
reset config
EA, Port0
IRAM
ST10F280
37/186
5.6.5 - Choosing the Baud Rat e for the BS L
The calculation of the serial Baud rate for ASC0
from the length of the first zero Byte that is
received, allows the operation of the bootstrap
loader of the ST10F280 wi th a wide range of Baud
rates. However, the upper and lower limits hav e to
be kept, in order to insure proper data transfer.
The ST10F280 uses timer T6 to measure the
length of the initial zero Byte. The quantization
uncertainty of this measurement implies the first
deviation from the real Baud rate, the next
deviation is implied by the computation of the
S0BR L reloa d value f rom the timer c ontents. The
formula below sho ws the association:
For a correct data transfer from the host to the
ST10F280 the maximum deviation between the
internal initialized Baud r ate for ASC0 and the real
Baud rate of the host shoul d be below 2.5%. The
deviation (FB, in pe rcen t) betwee n ho st Ba ud rat e
and ST10F280 Baud rate can be calculated via
the for m ula below:
Note: Function (FB) does not consider the
tolerances of os cillators and other devices
supporting the serial communicati on.
This Baud rate deviation is a nonlinear function
depending on the CPU clock and the Baud rate of
the host. The maxima of the function (FB)
increase with the host Baud rate due to the
smaller Baud rate pre-scaler factors and the
impl ied higher quant ization error (see Figure 8).
The minimu m Baud rate (BLow in the Figure 8) is
determined by the maximum count capacity of
timer T6, when measuring the zero Byte, and it
depends on the CPU clock. Using the maximum
T6 count 216 in the formula the minimum Baud
rate can be calculated. The lowest standard Baud
rate i n this case woul d be 1200 Baud . Baud rates
below BLow would cause T6 to overflow. In this
case AS C 0 cannot be initialized properly.
The maximum Baud rate (BHigh in the Figure 8)
is the highest Baud rate where the deviation still
does not exceed the limit, so all Baud rates
between BLow and BHigh are below the deviation
limi t . The maximum standard Baud rate that fulfills
this requirement is 19200 Baud.
Higher Baud rates, however, may be used as
long as the actual deviation does not exceed the
limit. A cer tain Baud rate (marked ’I’ in Figure 8)
may violate the deviation limit, while an even
higher Baud rate (marked ’II’ in Figure 8) stays
very well below it. This depends on the host
interface.
fCPU
32 S0BRL 1+()×
------------------------------------------------
BST10F280 =
S0BRL T6 36–
72
--------------------
=T6 9
4
--- fCPU
BHost
-----------------
×=
,
FBBContr BHost
–
BContr
-------------------------------------------- 100×=%,
FB2.5≤%
Fi gure 8 : Baud Rate Deviation Between Hos t and ST10F280
BLow
2.5%
FB
BHigh
I
II BHOST
ST10F280
38/186
6 - CENTRAL PROCESSING UNIT (CPU)
The CPU includes a 4-stage instruction pipeline, a
16-bit arithmetic and logic unit (ALU) and dedi-
cated SFRs. A dditional hardware has been added
for a separate multiply and d ivide unit, a b it- mask
generator and a barrel shifter.
Most of the ST10F280’s instructions can be exe-
cuted in one instruc tion cycle which requires 50ns
at 40MHz CPU clock. For example, shift and
rotate instructions are processed in one instruc-
tion cycle inde penden t o f the num ber o f b its to be
shifted.
Multiple-cycle instructions have been optimized:
branches are carried out in 2 cycles, 16 x 16 bit
multiplicat ion in 5 cycles and a 32/16 bit division in
10 cycles .
The jump cache reduces the execution time of
repeatedly performed jumps in a loop, from
2 cycles to 1 cycle.
The CP U uses a bank of 16 word registers to run
the current cont ext. This bank of General Purpose
Registers (GPR) is physically stored within the
on-chip Internal RAM (IRAM) area. A Context
Pointer (CP) register determines the base
address of the active register bank to be accessed
by the CPU.
The num ber of register bank s is only restricted by
the available Internal RAM space. For easy
parameter passing, a register bank may overlap
others.
A system stack of up to 1024 bytes is provided as
a storage for temporary data. The system stack is
allocated in the on-chip RAM area, and it is
accessed by the CPU via the stack pointer (SP)
register.
Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer
value upon each stack acc ess for the det ection of
a stac k overflow or underflow.
Fi gure 9 : CPU Block Diagram (MAC Unit not included)
32
Internal
RAM
2K Byte
General
Purpose
Registers
R0
R15
MDH
MDL
Barrel-Shift
Mul./Div.-HW
Bit- M a s k G e n.
ALU
16-Bit
CP
SP
STKOV
STKUN
Exec . U n it
Instr. Ptr
4-Stage
Pipeline
PSW
SYSCON
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
Data Pg. Ptrs Code Seg. Ptr.
CPU
512K Byte
Flash
memory
16
16
Bank
n
Bank
i
Bank
0
ST10F280
39/186
The System Configuration Register SYSC ON
This bit-addressable register provides general system configuration and control functions. The reset
value for register SYSCO N depends on the state of the PORT0 pins during reset.
SYSCON (FF12h / 89h) SF R Reset Value: 0xx0h
Notes: 1. Thes e bi t are set di rectly or in di rectly according to P O RT 0 and EA pin co nfiguration duri ng re set sequence.
2. R egister SYSCON cannot b e changed a fter execution of the EINIT instruction.
6.1 - Multiplier-accumul ator Unit (MAC)
The MAC co-processor is a specialized co-pro-
cessor added to the ST10 CPU Core in order to
improve the performances of the ST10 Family in
signal proces sing algor ithms.
Signal pr oces sing needs at leas t three specialized
units operating in parallel to achieve maximum
performanc e :
– A Multiply - Ac c umula te U nit ,
– An Address Generation Unit, able to feed the
MAC Unit with 2 operands per cy cle,
– A Rep eat Unit, to execute series of multiply-ac-
cumulate instructions.
The existing ST10 CPU has been modified to
include new addressing capabilities which enable
the CPU to supply the new co-processor with up
to 2 operands per instruction cy cle.
This new co-processor (so-called MAC) contains
a fast multiply-accumu late unit and a repeat unit.
The co-processor instructions extend the ST10
CPU instruction set with multiply, multiply-accu-
mulate, 32-bit signed arithm etic operations.
A new transfer instruction CoMOV has also been
added to take benefit of the ne w addressing capa-
bilities.
1514131211109876543210
STKSZ ROM
S1 SGT
DIS ROM
EN BYT
DIS CLK
EN WR
CFG CS
CFG PWD
CFG OWD
DIS BDR
STEN XPEN VISI
BLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
Bit Function
XPEN 0
1
XBUS Peripheral Enable Bit
Accesses to the on-chip X-Peripherals and their functions are disabled
The on-chip X-Peripherals are enabled and can be accessed.
BDRSTEN 0
1
Bidirectional Reset Enable
RSTIN pin is an input pin only. SW Reset or WDT Reset have no effect on this pin
RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS 0
1
Oscillator Watchdog Disable Control
Oscillato r Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If
there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (2 to 10MHz).
OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current..
PWDCFG 0
1
Power Down Mode Configuration Control
Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low, oth-
erwise the instructio n has no effect. To exit Power Down Mode, a n external reset must occurs by
asserting the RSTIN pin.
Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin.
CSCFG 0
1
Chip Select Configuration Control
Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
Unlatched Chip Slect lines : CSx change with rising edge of ALE
ST10F280
40/186
6.1.1 - Features
6.1.1.1 - Enhanced Addressing Cap abilities
– New addressi ng m ode s inclu ding a double in di-
rect addressing mode with pointer post-modifi-
cation.
– Parallel Data Move : this mechanism allows one
operand move during Multiply-Accumulate in-
structions without penalty.
– New t ranfer instructions CoSTOR E (for fast ac-
cess to the MAC SFRs) and CoMOV (for fast
memory to memory table transfer).
6.1.1.2 - Mul tip ly-Acc um u late Unit
– One-cyc le execution for all MAC operations.
– 16 x 16 signed/unsigned parallel multiplier.
– 40-bit signed arithmetic unit with automatic sat-
uration mode.
– 40-bit ac c u m u lat o r.
– 8-bi t left/right shifter.
– Full inst r uct ion set with multiply and mu lt iply - ac -
cumulate, 32-bit signed arithmetic and com pare
instructions.
6.1.1.3 - Program Control
– Repeat Unit : allows some MAC co-processor in-
structions to be re peated up to 8192 tim es. Re-
peated instructions ma y be interrupted.
– M A C interrupt (Class B Trap) on MAC condition
flags.
Fi gure 1 0 : M AC Unit Architecture
Note: * Shared with standard ALU.
Operand 2Op er an d 1
Con tr ol Un it
Repeat Unit
ST10 CPU
Interrupt
Controller
MSW
MRW
MAH MAL
MCW
Flags MAE
Mux
8-b it Le ft/Righ t
Shifter
Mux
Mux
Sign Extend
16 x 16
Concatenation
signed/unsigned
Multiplier
40-bit Signed Arithmetic Unit
0h 0h08000h
40
16
40 40
32 32
16
40
40
40
40
40
Scaler
AB
40
GPR Pointers *
IDX0 Pointer
IDX1 Pointer
QR0 GPR Offset Register
QR1 GPR Offset Register
QX0 IDX Offset Register
QX1 IDX Offset Register
ST10F280
41/186
6.2 - Instruction Set S u mm ar y
The Table 4 lists the instr ucti ons of the ST10F280. The various addres sing m odes, instruc tion ope ration,
paramet ers for condi tional execution of instruct ions, opcodes and a d etailed descr iption of each instruc-
tion can be foun d in the “ST10 Family P rogramming Manual”.
Table 4 : Instruction Set Summary
Mnemonic Description Bytes
ADD(B) Add word (byte) operands 2 / 4
ADDC(B) Add word (byte) operands with Carry 2 / 4
SUB(B) Subtract word (byte) operands 2 / 4
SUBC(B) Subtract word (byte) operands with Carry 2 / 4
MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B) Complement direct word (byte) GPR 2
NEG(B) Negate direct word (byte) GPR 2
AND(B) Bitwise AND, (word/byte operands) 2 / 4
OR(B) Bitwise OR, (word/byte operands) 2 / 4
XOR(B) Bitwise XOR, (word/byte operands) 2 / 4
BCLR C lear direct bit 2
BSET Set direct bit 2
BMOV(N) Move (negated) direct bit to direct bit 4
BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4
BCMP Compare direct bit to direct bit 4
BFLDH/L Bitwise modify masked high/low byte of bit-addressable direct word memory
with immediate data 4
CMP(B) Compare word (byte) operands 2 / 4
CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4
CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4
PRIOR Determine number of shift cycles to normalize direct word GPR and store result
in direct word GPR 2
SHL / SHR Shift left/right direct word GPR 2
ROL / ROR Rotate left/right direct word GPR 2
ASHR Arithmetic (sign bit) shift right direct word GPR 2
MOV(B) Move word (byte) data 2 / 4
MOVBS Move byte operand to word operand with sign extension 2 / 4
MOVBZ Move byte operand to word operand with zero extension 2 / 4
JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4
JMPS Jump absolute to a code segment 4
J(N)B Jump relative if direct bit is (not) set 4
JBC Jump relative and clear bit if direct bit is set 4
ST10F280
42/186
6.3 - MAC Co processor Specific Instructio ns
The following table gives an over view of the MAC
instruction set. All the mnemonics are listed with
the addressing modes that can be used wi th each
instruct ion.
For each combination of mnemonic and address-
ing mode this table indicates if it is repeatable or
not
New addressing capabilities enable the CPU to
supply the MAC with up to 2 operands per instruc-
tion cycle. MAC instructions: multiply, multi-
ply-accumul at e, 32-bit signed arithmeti c operations
and the CoMOV transfer instruction have been
added to the standard instruction set. Full details
are provided in the ‘ST10 Family Programming
Manual’. Double indirect addressing requires two
poin ters. A ny GPR c an be us ed fo r one pointer, the
other pointer is provided by one of two specific
SFRs IDX0 and IDX1. Two pairs of offset registers
QR 0/ QR 1 an d QX0/ QX 1 ar e as so cia te d wit h ea ch
pointer (GPR or I DX
i
).
The GPR pointer allows access to the entire
mem ory space, but IDXi are limited t o the in ter nal
Dual-P ort RAM, e xcept for the CoMOV i nstructi on.
JNBS Jump relative and set bit if direct bit is not set 4
CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4
CALLS Call absolute subroutine in any code segment 4
PCALL Push direct word register onto system stack and call absolute subroutine 4
TRAP Call interrupt service routine via immediate trap number 2
PUSH, POP Push/pop direct word register onto/from system stack 2
SCXT Push direct word register onto system stack and update register with word
operand 4
RET Return from intra-segment subroutine 2
RETS Return from inter-segment subroutine 2
RETP Return from intra-segment subroutine and pop direct
word register from system stack 2
RETI Return from interrupt service subroutine 2
SRST Software Reset 4
IDLE Enter Idle Mode 4
PWRDN Enter Power Down Mode (supposes NMI-pin being low) 4
SRVWDT Service Watchdog Timer 4
DISWDT Disable Watchdog Timer 4
EINIT Signify End-of-Initialization on RSTOUT-pin 4
ATOMIC Begin ATOMIC sequence 2
EXTR Begin EXTended Register sequence 2
EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4
EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4
NOP Null operation 2
Table 4 : Instruction Set Summary
Mnemonic Description Bytes
ST10F280
43/186
Mnemonic Addressing Modes Repeatability
CoMUL
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
CoMULu
CoMULus
CoMULsu
CoMUL-
CoMULu-
CoMULus-
CoMULsu-
CoMUL, rnd
CoMULu, rnd
CoMULu s, rnd
CoMULsu, rnd
CoMAC
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoMACu
CoMACus
CoMACsu
CoMAC-
CoMACu-
CoMACus-
CoMACsu-
CoMAC, rnd
CoMACu, rnd
CoMACus, rnd
CoMACsu, rnd
CoMACR
CoMACRu
CoMACRus
Rwn, Rwm
[IDXi⊗], [Rwn⊗]
Rwn, [RWm⊗]
No
No
No
CoMACRsu
CoMACR, rnd
CoMACRu, rnd
CoMACRus, rnd
CoMACRsu, rnd
CoNOP
[Rwm⊗] Yes
[IDXi⊗]Yes
[IDXi⊗], [Rwm⊗] Yes
CoNEG -NoCoNEG, rnd
CoRND
CoSTORE Rwn, CoReg No
[Rwn⊗], Coreg Yes
CoMOV [IDXi⊗], [Rwm⊗] Yes
ST10F280
44/186
CoMACM
[IDXi⊗], [Rwm⊗] Yes
CoMACMu
CoMACMus
CoMACMsu
CoMACM-
CoMACMu-
CoMACMus-
CoMACMsu-
CoMACM, rnd
CoMACMu, rnd
CoMACMus, rnd
CoMACMsu, rnd
CoMACMR
CoMACMRu
CoMACMRus
CoMACMRsu
CoMACMR, rnd
CoMACMRu, rnd
CoMACMRus, rnd
CoMACMRsu, r nd
CoADD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
Yes
Yes
CoADD2
CoSUB
CoSUB2
CoSUBR
CoSUB2R
CoMAX
CoMIN
CoLOAD
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
CoLOAD- No
CoLOAD2 No
CoLOAD2- No
CoCMP
CoSHL Rwm
#data4
[Rwm⊗]
Yes
No
Yes
CoSHR
CoASHR
CoASHR, rnd
CoABS
-
Rwn, Rwm
[IDXi⊗], [Rwm⊗]
Rwn, [Rwm⊗]
No
No
No
Mnemonic Addressing Modes Repeatability
ST10F280
45/186
The Tab le 5 shows the vari ous combinations of pointer post-modif ication f or each of these 2 new address-
ing mod es. In t his docum ent the symbol s “[Rwn⊗]” and “[IDXi⊗]” refe r to these addressing modes.
Table 5 : Pointer P ost-modification Combinations for IDXi and Rwn
Symbol Mnemonic Address Pointer Operation
“[IDXi⊗]” stand s for [IDXi] (IDXi) ← (IDXi) (no-op)
[IDXi+] (IDXi) ← (IDXi) +2 (i=0,1)
[IDXi] (IDXi) ← (IDXi)2 (i=0,1)
[IDXi + QXj] (IDXi) ← (IDXi) + (QXj) (i, j =0,1)
[IDXi QXj] (IDXi) ← (IDXi) (QXj) (i, j =0,1)
“[Rwn⊗]” stands for [Rwn] (Rwn) ← (Rwn) (no-op)
[Rwn+] (Rwn) ← (Rwn) +2 (n=0-15)
[Rwn-] (Rwn) ← (Rwn)2 (k=0-15)
[Rwn+QRj] (Rwn) ← (Rwn) + (QRj) (n=0-15;j =0,1)
[Rwn QRj] (Rwn) ← (Rwn) (QRj) (n=0-15; j =0,1)
Table 6 : MA C Registers Referenced as ‘CoReg‘
Registers Description Address in Opcode
MSW MAC-Unit Status Word 00000b
MAH MAC-Unit Accumulator High 00001b
MAS “limited” MAH /signed 00010b
MAL MAC-Unit Accumulator Low 00100b
MCW MAC-Unit Control Word 00101b
MRW MAC-Unit Repeat Word 00110b
ST10F280
46/186
7 - EXTERNAL BUS CONTROL LER
All of the external memory accesses are per-
formed by the on-chi p ex ternal bus controller.
The EB C can be programmed to single chip mode
when no external memory is required, or to one of
four diff erent e xternal memory access modes:
– 16-/18-/20-/24-bit addresses 16-bit da ta, demul-
tiplexed
– 16-/18-/20-/24-bit addresses 16-bit data, multi-
plexed
– 16-/18-/20-/24-bit addresses 8-bit data, multi-
plexed
– 16-/18-/20-/24-bit addresses 8 -bit data, demulti-
plexed
In demul tiplexed bus modes addresses are output
on PORT1 a nd data is input/output on PORT0 or
P0L, respectively. In the multiplexed bus modes
both addresses and data use PORT0 for input/
output.
Timing characteristics of the external bus inter-
face (memory cycle time, memory tri-state time,
length of ale and read write delay) are program-
mable giving the choice of a wide range of memo-
r ies and exter nal peripherals.
Up to 4 independent address windows may be
defined (using register pairs ADDRSELx / BUS-
CONx) to access different resources and bus
characteristics.
These address windows are arranged hierarchi-
cally where BUSCON4 overrides BUSCON3 and
BUSCON2 overrides BUSCON1. All accesses to
locations not co vered by these 4 address windows
are controlled by BUSCON0.
Up to 5 external CS signals (4 windows plus
default) can be generated in order to save exter-
nal glue logic. Access to very slow memories is
sup ported by a ‘ R eady’ function .
A HOLD/HLDA protocol is available for bus arbi-
tration which shares external resources with other
bus masters. The bus arbitration is enabled by
setting bit HLDEN in register PSW. After setting
HLDEN once, pins P6.7...P6.5 (BREQ, HLDA,
HOLD) are automatically control led by the EBC. In
mast er mode (defau lt after reset) the HLDA pin is
an output.
By setting bit DP6.7 to’1’ the slave mode is
selected where pin HLDA is switched to input.
This directly connects the slave controller to
anoth er master controller without glue logic.
For applications which require less ex ternal m em -
ory space, the address s pace can be restricted t o
1 MByt e, 256 KByte or to 64 KByte . Port 4 outputs
all 8 address lines if an address space of 16
MByt es is used, otherwi se f our, two or no address
lines.
Chip select timing can be made programmable.
By default (after reset) , t he CSx lin es c han ge half
a CPU clock cycle after the rising edge of ALE.
With the CSCFG bit set in the SYSCON
register the CSx lines change with the risi ng edge
o f ALE.
The activ e le vel of the READY pin can be set by bit
RDYPOL in the BUSCONx registers. When the
READY fun ction is enabled for a specific address
window, each bus cycle within the window must
be terminated with the active level defined by bit
RDY PO L in the assoc iated BUSCON regist er.
7.1 - Programmab le Ch ip Se l ect Ti mi ng Co ntrol
The S T10F280 allows the user to adjust the posi-
tion of the CSx lines changes. By default (after
reset), the CSx lines are changing half a CPU
clock c ycle ( 12.5 ns at fCPU = 40MHz) after the ris-
ing edge of ALE.
With the CSCFG bit set in the SYSCON register,
the CSx lines are changing with the rising edge of
ALE, t hus the CSx li nes are changing at the same
time t he address lines are c hanging. S ee Section
19.2 - System Configuration Registers for
detailled descr iption of SYSCON register.
ST10F280
47/186
Fi gure 1 1 : Chip S elec t D e l a y
7.2 - READY Programmable Polarity
The ac tiv e le vel of the READY pin can be selected by software via the RDYPOL bit in the BUSCONx reg-
isters. When the READY function is enab led f or a specific addr ess wi ndow, each bus cycle within this wi n-
dow must be terminated with the active level defined by this RDYPOL bit in the associted BUSCON
register.
BU SCON 0 (FF0Ch / 86h) SFR Reset Value: 0xx0h
BU SCON1 (FF14h / 8Ah ) SF R Reset Value: 000 0h
BU SCON2 (FF16h / 8Bh ) SF R Reset Value: 000 0h
1514131211109876543210
CSW
EN0 CSRE
N0 RDY
POL0 RDY
EN0 -BUS
ACT0 ALE
CTL0 -BTYP MTT
C0 RWD
C0 MCTC
RW RW RW RW RW RW RW RW RW RW
1514131211109876543210
CSW
EN1 CSR
EN1 RDY
POL1 RDY
EN1 - BUS
ACT1 ALE
CTL1 - BTYP MTT
C1 RWD
C1 MCTC
RW RW RW RW RW RW RW RW RW RW
1514131211109876543210
CSW
EN2 CSR
EN2 RDY
POL2 RDY
EN2 - BUS
ACT2 ALE
CTL2 - BTYP MTT
C2 RWD
C2 MCTC
RW RW RW RW RW RW RW RW RW RW
No rmal CSx
RD
Address (P1)
ALE
Segmen t (P 4)
Normal Demu ltiplexed
Bus Cycle
ALE Lengthen Demulti pl exed
Bus Cycle
Un l atched C Sx
WR
Read/Write
Delay
Data Data
Data Data
BUS (P0)
BUS (P0)
Read/Write
Delay
ST10F280
48/186
BU SCON3 (FF18h / 8Ch ) SF R Reset Value: 000 0h
BU SCON4 (FF1Ah / 8Dh)
SFR Reset Value: 0000h
1514131211109876543210
CSW
EN3 CSR
EN3 RDY
POL3 RDY
EN3 - BUS
ACT3 ALE
CTL3 - BTYP MTT
C3 RWD
C3 MCTC
RW RW RW RW RW RW RW RW RW RW
1514131211109876543210
CSW
EN4 CSR
EN4 RDY
POL4 RDY
EN4 - BUS
ACT4 ALE
CTL4 - BTYP MTT
C4 RWD
C4 MCTC
RW RW RW RW RW RW RW RW RW RW
Bit Function
RDYPOLx 0
1
Ready Active Level Control
The active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY pin,
The active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY pin.
ST10F280
49/186
8 - INTERRUP T SYST EM
The interrupt response time for internal program
execution is from 125ns to 300ns at 40MHz CPU
clock.
The ST10F280 architecture supports several
mechanisms for fast and flexible response to
service requests that can be generated from
various sources (internal or external) to the
microcontroller. Any of these interrupt requests
can be serviced by the Interrupt Controller or by
the Peripheral Event Cont roller (PEC).
In contrast to a standard interrupt service where
the c urrent program ex ecution is suspended and a
branch to the interrupt vector table is performed,
just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service
implies a single Byte or Word data transfer
between any two memory locations with an
additional increment of either the PEC source or
destination pointer. An individual PEC transfer
counter is implicitly decremented for each PEC
ser v i ce except when perfor mi ng in the cont inuous
transfer mode. When t his counter reaches zero, a
standard interrupt is performed to the
corresponding source related vector location.
PEC services are very well suited to perform the
transmission or the reception of blocks of data.
The ST10F280 has 8 PEC channels, each of
them offers such fast i nterrupt-driven data transfer
capabilities.
An interrupt control register which contains an
inte rrupt request flag, a n interrupt enable flag and
an interrupt priority bitfield is dedicated to each
existing interrupt source. Thanks to its related
register, each source can be programmed to one
of sixteen interrupt priority levels. Once starting to
be processed by the CPU, an interrupt service
can only be interrupted by a higher prioritized
service request. For the standard interrupt
processing, each of the possi ble interrupt sources
has a dedicated vector location.
Software interrupt s are supported by means of the
‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
8.1 - External Interrupts
Fast external interrupt inputs are provided to
service external interrupts with high precision
requirements. These fast interrupt inputs feature
pro grammable edge dete ction (rising edge, falling
edge or both edges).
Fast external interrupts may also have interrupt
sources selected from other peripherals; for
example the CANx controller receive signal
(CANx_RxD) can be used to interru pt the syst em.
This new fun ction is c ontrolled usi ng th e ‘Exter nal
Interrupt Source Selection ’ register EXISEL.
EXISEL (F1D Ah / EDh) ESFR Reset Value: 0000h
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interru pt x Source Selection (x=7...0)
‘00’: Input from associated P ort 2 pi n.
‘01’: Input f rom “alternate source”.
‘10’: Input f rom Port 2 pin ORed with “alternate source”.
‘11’: Input f rom Port 2 pin ANDed with “alt ernate source”.
EXIxSS Port 2 pin Alternate Source
0 P2.8 CAN1_RxD
1 P2.9 CAN2_RxD
2...7 P2.10...15 Not used (zero)
ST10F280
50/186
EXICON (F1C0h / E0h ) ESFR Reset Value: 0000h
8.2 - Interrupt Registers and Vecto rs Location List
Table 7 shows all the available ST10F280 interrupt sources and the corresponding hardware-related
interrupt flags, vectors, vec tor locations and trap (interrupt) numbers:
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
Table 7 : Interrupt Sources
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
CAPCOM Register 0 CC0IR CC0IE CC0INT 00’0040h 10h
CAPCOM Register 1 CC1IR CC1IE CC1INT 00’0044h 11h
CAPCOM Register 2 CC2IR CC2IE CC2INT 00’0048h 12h
CAPCOM Register 3 CC3IR CC3IE CC3INT 00’004Ch 13h
CAPCOM Register 4 CC4IR CC4IE CC4INT 00’0050h 14h
CAPCOM Register 5 CC5IR CC5IE CC5INT 00’0054h 15h
CAPCOM Register 6 CC6IR CC6IE CC6INT 00’0058h 16h
CAPCOM Register 7 CC7IR CC7IE CC7INT 00’005Ch 17h
CAPCOM Register 8 CC8IR CC8IE CC8INT 00’0060h 18h
CAPCOM Register 9 CC9IR CC9IE CC9INT 00’0064h 19h
CAPCOM Register 10 CC10IR CC10IE CC10INT 00’0068h 1Ah
CAPCOM Register 11 CC11IR CC11IE CC11INT 00’006Ch 1Bh
CAPCOM Register 12 CC12IR CC12IE CC12INT 00’0070h 1Ch
CAPCOM Register 13 CC13IR CC13IE CC13INT 00’0074h 1Dh
CAPCOM Register 14 CC14IR CC14IE CC14INT 00’0078h 1Eh
CAPCOM Register 15 CC15IR CC15IE CC15INT 00’007Ch 1Fh
CAPCOM Register 16 CC16IR CC16IE CC16INT 00’00C0h 30h
CAPCOM Register 17 CC17IR CC17IE CC17INT 00’00C4h 31h
CAPCOM Register 18 CC18IR CC18IE CC18INT 00’00C8h 32h
CAPCOM Register 19 CC19IR CC19IE CC19INT 00’00CCh 33h
CAPCOM Register 20 CC20IR CC20IE CC20INT 00’00D0h 34h
ST10F280
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CAPCOM Register 21 CC21IR CC21IE CC21INT 00’00D4h 35h
CAPCOM Register 22 CC22IR CC22IE CC22INT 00’00D8h 36h
CAPCOM Register 23 CC23IR CC23IE CC23INT 00’00DCh 37h
CAPCOM Register 24 CC24IR CC24IE CC24INT 00’00E0h 38h
CAPCOM Register 25 CC25IR CC25IE CC25INT 00’00E4h 39h
CAPCOM Register 26 CC26IR CC26IE CC26INT 00’00E8h 3Ah
CAPCOM Register 27 CC27IR CC27IE CC27INT 00’00ECh 3Bh
CAPCOM Register 28 CC28IR CC28IE CC28INT 00’00F0h 3Ch
CAPCOM Register 29 CC29IR CC29IE CC29INT 00’0110h 44h
CAPCOM Register 30 CC30IR CC30IE CC30INT 00’0114h 45h
CAPCOM Register 31 CC31IR CC31IE CC31INT 00’0118h 46h
CAPCOM Timer 0 T0IR T0IE T0INT 00’0080h 20h
CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h
CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh
CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh
GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h
GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h
GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h
GPT2 Timer 5 T5IR T5IE T5INT 00’0094h 25h
GPT2 Timer 6 T6IR T6IE T6INT 00’0098h 26h
GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h
A/D Conversion Complete ADCIR ADCIE ADCINT 00’00A0h 28h
A/D Overrun Error ADEIR ADEIE ADEINT 00’00A4h 29h
ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah
ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h
ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh
ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch
SSC Transmit SCTIR SCTIE SCTINT 00’00B4h 2Dh
SSC Receive SCRIR SCRIE SCRINT 00’00B8h 2Eh
SSC Error SCEIR SCEIE SCEINT 00’00BCh 2Fh
PWM Channel 0...3 PWMIR PWMIE PWMINT 00’00FCh 3Fh
CAN1 Interface XP0IR XP0IE XP0INT 00’0100h 40h
CAN2 Interface XP1IR XP1IE XP1INT 00’0104h 41h
XPWM XP2IR XP2IE XP2INT 00’0108h 42h
PLL Unlock/OWD XP3IR XP3IE XP3INT 00’010Ch 43h
Table 7 : Interrupt Sources (continued)
Source of Interrupt or PEC
Service Request Request
Flag Enable
Flag Interrupt
Vector Vector
Location Trap
Number
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Hardware traps are exceptions or error cond itions
that ar ise du ring run -time. They cau se imme diate
non-maskable system reaction similar to a
standard interrupt service (branching to a
dedicated v ector table location).
The occurrence of a hardware trap is additiona lly
signified by an individual bit in the trap flag
register (TFR). Except when another higher
prior itized trap service is in progress, a hardware
trap will interrupt any other program execution.
Hardware trap s ervices cannot not be in terrupted
by standard interrupt or by P EC interrupts.
8.3 - Interrupt Control Registers
All interrupt control registers are identically
organized. The lower 8 bit of an interrupt control
register contain the complete interrupt status
information of the associated source, which is
required during one round of prioritization, the
upper 8 bit of t he respectiv e register are reserved.
All interrupt control registers are bit-addressable
and all bit can be read or written via software.
This allows each interrupt source to be
programmed or m odified with j ust one instruction.
When accessing interrupt control registers
through instructions which operate on Word data
types, their upper 8 bit (15...8) will return zeros,
when read, and will discard written data.
The la yout of the Interrupt Control registers shown
below applies to each xxIC register, where xx
stands for the mnemonic for the respective
source.
xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h
1514131211109876543210
--------xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
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8.4 - Exception and E rr o r Traps List
Table 8 shows all of the possible exception s or error conditions that can arise during run-time :
* - All the class B traps ha v e the same trap number (and vector) and the same lower priority compare to the class A traps and to the r e se ts.
- Eac h class A tra ps has a dedi cated trap numbe r (and vector). They are prior i tized in the s econd prior i ty l evel.
- Th e resets have the hi ghest pr i ority l evel and the same trap number.
- Th e PSW.ILVL CPU priority is forc ed to t he hi ghest l evel (15) when these exeptions are serviced.
Table 8 : Exceptions or Error Conditions that Can Arise During Run- time
Excep tion Cond ition Tr ap Flag Tr ap
Vector Vector Location Trap Number Trap *
Priority
Reset Functions MAXIMUM
Hardware Reset RESET 00’0000h 00h III
Software Reset RESET 00’0000h 00h III
Watchdog Timer Overflow R ESE T 0 0’00 00h 00h III
Class A Hardware Traps
Non-Maskable Interrupt NMI NMITRAP 00’0008h 02h II
Stack Overflow STKOF STOTRAP 00’0010h 04h II
Stack Underflow STKUF STUTRAP 00’0018h 06h II
Class B Hardware Traps
Undefined Opcode UNDOPC BTRAP 00’0028h 0Ah I
Protected Instruction Fault PRTFLT BTRAP 00’0028h 0Ah I
Illegal Word Operand Access ILLOPA BTRAP 00’0028h 0Ah I
Illegal Instruction Access ILLINA BTRAP 00’0028h 0Ah I
Illegal External Bus Access ILLBUS BTRAP 00’0028h 0Ah I
MAC Trap MACTRP BTRAP 00’0028h 0Ah I
MINIMUM
Reserved [2Ch –3Ch] [0Bh – 0Fh]
Software Traps
TRAP Instruction Any [00’0000h– 00’01FCh]
in steps of 4h Any [00h – 7Fh] Current
CPU Priority
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9 - CAPTURE/COMPARE (CAPCOM) UNITS
The ST10F280 has two 16 channels CAPCOM
units as described in Figure 12. These support
genera tion and control of timing se quences on up
to 32 channels with a maximum resolution of
200ns at 40MHz CPU clock. The CAPCOM units
are typically used to handle high sp eed I/O tasks
such as pulse and waveform generation, pulse
width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording
relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload
registers provide two independent time bases for
the capt ure/compare register arr ay (See Figure 13
and Figure 14).
The input clock for the timers is programmable to
several prescaled values of the internal system
clock, or may be derived from an overflow/
underflow of timer T6 in module GPT2. This
provides a wide range of variation for the timer
period and resolution and allows precise
adjust ments to application specific requirem ents.
In addition, external count inputs for CAPCOM
timers T0 and T7 allow event scheduling for the
capture/compare registers relative to external
events.
Each of the two capture/compare register arrays
contain 16 dual purpose capture/compare
registers, each of which may be individually
allocated to eit her CAPCOM t i mer T0 or T1 (T7 or
T8, respectively), and programmed for capture or
compare functions. Each of the 32 registers has
one associa ted por t pin which serves as an input
pin for triggering the capture function, or as an
output pin to indicate the occurrence of a compare
event. Figure 12 shows the basi c structure of the
two CAPCOM units.
Note The CAPCOM2 unit provides 16 captur e i nputs, but only 12 compare outputs. CC24I to CC27I are inputs onl y.
Fi gure 1 2 : CAP CO M Unit Block Diagram
Pin Tx
Input
Control
2
n
n = 3...10
GPT2 Tim er T6
Pin
TxIN
CPU
Clock
Mode
Control
(Capture
or
Compare)
16
Capture inputs
Co m p are ou tpu ts
Pin
Ty
Input
Control
2
n
n = 3...10
GPT2 Timer T6
Over / Underflow
CPU
Clock
Reload Register TxREL
CAPCO M Timer Tx
Interrupt
Request
Sixteen 16-bit
(Capture/Compare)
Registers
Over / Underflow
CAPCO M Timer Ty
Reload Register TyREL
16
Capture / Compare *
In te rru p t Re q u e sts
Interrupt
Request
x = 0, 7
y = 1, 8
ST10F280
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Fi gure 1 3 : Block Diagram of CAPCOM Timers T0 and T7
Fi gure 1 4 : Block Diagram of CAPCOM Timers T1 and T8
Note: When an external input signal is
connected to the input lines of both T0 and
T7, these timers count the input signal
synchronously. Thus the two timers can be
regarded as one t imer whose contents can
be compared with 32 capture registers.
When a capture/compare register has been
selec ted for capture mode, the current contents of
the allocated timer will be latched (captured) into
the capture/compare register in response to an
external event at the por t pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is
generated.
Either a positive, a negative, or both a positive
and a negative external signal tr ansition at t he pin
can be selected as the triggering event. The
cont ents of all regis ters which have been selected
for one of the five compare modes are
continuously compared with the contents of the
a lloc a t ed tim er s.
When a match occurs between the timer value
and the value in a capture /compare register,
specific actions will be taken based on the
selected compare mode (see Tabl e 9).
The input frequencies fTx, for the timer input
selector Tx, are determined as a function of the
CPU clocks. The timer input frequencies,
resolution and periods which result from the
selected pre-scaler option in TxI when using a
40MHz CP U clock are listed in the Table 10.
The numbe rs for the timer periods are based on a
reload value of 0000h. Note that some numbers
may b e rounded to 3 significant figures.
Pin
X
Txl
CPU
Clock
TxR
MUX
GPT2 Timer T6
Over / Underflow
Edge S ele ct
TxIN
Txl
Txl TxM
Input
Control
Reload Register TxREL
CAPCOM Tim er Tx TxIR Interrupt
Request
x = 0, 7
X
Txl
CPU
Clock
TxR
MUX
GPT2 Timer T6
Over / Underflow
TxM
Reload Register TxREL
CAPCO M Timer Tx TxIR Interrupt
Request
x = 1, 8
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Table 9 : Compare Modes
Compare Modes Function
Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible
Mode 1 Pin toggles on each compare match; several compare events per timer period are possible
Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated
Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer
period is generated
Double Register
Mode Two registers operate on one pin; pin toggles on each compare match; seve ral compare events
per timer period are possible.
Table 10 : CAPCOM Timer Input Frequencies, Resolution and Periods
fCPU = 40MHz Timer Input Selection TxI
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler for
f
CPU 8 16 32 64 128 256 512 1024
Input Frequency 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
ST10F280
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10 - GENERAL PURPOSE TI MER UNIT
The GPT unit is a flexible multifunctional timer/
counter structure which is used for time related
tasks such as event timing and counting, pulse
width and duty cycle measurements, pulse
generation, or pulse multiplication. The GPT unit
contains five 16-bit timers organized into two
separate modules GPT1 and GPT2. Each timer in
each module may operate independently in
several different modes, or may be concatenated
with another timer of the same module.
10.1 - GPT1
Each of the three timers T2, T3, T4 of the GPT1
module can be configured individually for one of
four basic modes of operat ion: timer, gate d time r ,
counter mode and incremental interface
mode.
In timer mode, the input cloc k f or a t imer is derived
from the CPU clock, divided by a programmable
prescaler.
In counte r m ode, the timer is clo cked in reference
to exter nal events.
Pulse width or duty cycle measurement is
supported in gated timer mode where the
operation of a timer is controlled by the ‘gate’ level
on an external input pin. For these purposes, each
timer has one associated port pin (TxIN) which
serv es as gate or cloc k input.
Table 11 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T3 and to the auxiliary
timers T 2 and T4 in Tim er and Gated Timer Mode .
The count direction (up/down) for each timer is
programmable by software or may be altered
dynamically by an external signal on a port pin
(TxEUD).
In Incremental Interface Mode, the GPT1 timers
(T2, T3, T4) can be directly connected to the
incremental position sensor signals A and B by
thei r respective inputs TxIN and TxEUD.
Direction and count signals are internally derived
from these two input signals so that the contents
of the respective timer Tx corresponds to the
sensor position. The third position sensor signal
TOP0 can be connected to an interrupt input.
Timer T3 has out put t oggle lat ches (TxOTL) which
changes state on each timer ov er flow / underflow.
The st ate of this latch m ay be output on por t p ins
(TxOUT) for time out monitoring of external
hardware components, or may be used internally
to clock timers T2 and T4 for high resolution of
long duration measurem ent s.
In addition to their basic operating modes, timers
T2 and T4 may be c onfigured as reload or capture
registers for timer T3. When used as capture or
reload registers, timers T2 and T4 are stopped.
The cont ents of timer T3 is captured into T2 or T4
in response to a signal at their associated input
pi ns ( TxIN).
Timer T3 is reloaded with the contents of T2 or T4
triggered either by an external signal or by a
selectable state transition of its toggle latch
T3OTL. When both T2 and T4 are configured to
alte rn ately reloa d T 3 on opposite state tra nsitions
of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated
without software intervention.
Table 11 : GPT1 Timer Input Frequencies, Resol ution and Periods
fCPU = 40MHz Timer Input Selection T2I / T3I / T4I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 8 16 32 64 128 256 512 1024
Input Freq 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz 39.1kHz
Resolution 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs 25.6µs
Period maximum 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms 1.678s
ST10F280
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Fi gure 1 5 : Block Diagram of GPT1
10.2 - GPT2
The GPT2 module provides precise event control
and time measurement. It i ncludes tw o timers (T5,
T6) and a capture/reload register ( CA PREL). Both
timers c an be clocked wit h an input clo ck which is
derived from the CPU clock via a programmable
prescaler or with external signals. The count
direction (up/down) for each timer is
pro gram mable by software or may additionally be
alter ed dynamically by an e xternal signal on a port
pin (TxEUD). Concatenation of the timers is
supported via the output toggle latch (T6OTL) of
timer T6 which changes its state on each timer
overf lo w/underflow.
The st ate of this latch may be used to c lock timer
T5, or it ma y be output on a port pin (T6OUT). The
overflow / underflow of timer T6 can additionally
be used to clock the CAPCOM timers T0 or T1,
and t o cause a reload f rom the CAPREL re gister.
The CAPREL register may capture the contents of
timer T5 bas ed on an external signal transition on
the corresp ondin g port pin (CA P IN), an d tim er T 5
may optionally be cleared after the capture
procedure. This allows absolute time differences
to be measured or pulse multiplication to be
performed without software overhead.
The capture trigger (timer T5 to CAPREL) may
also be generated upon transitions of GPT1 timer
T3 inputs T3IN and/or T3EUD. This is
advantageous when T3 operates in Incremental
Interface Mode.
Table 12 lists the timer input frequencies,
resolution and periods for each pre-scaler option
at 40MHz CPU clock. This also applies to the
Gated Timer Mode of T6 and to the aux iliary ti mer
T5 in Timer and Gated Timer Mod e.
2
n
n=3 ...1 0
2
n
n=3 ...1 0
2
n
n=3...10
T2EUD
T2IN
CPU Clock
CPU Clock
CPU Clock
T3IN
T4IN
T3EUD
T4EUD
T2
Mode
Control
T3
Mode
Control
T4
Mode
Control
GPT1 Timer T2
GPT1 Timer T3
GPT1 Timer T4
T3OTL
Reload
Capture
U/D
U/D
Reload
Capture
Interrupt
Request
Interrupt
Request
Interrupt
Request
T3OUT
U/D
Table 12 : GPT2 Timer Input Frequencies, Resol ution and Period
fCPU = 40MHz Timer Input Selection T5I / T6I
000b 001b 010b 011b 100b 101b 110b 111b
Pre-scaler factor 4 8 16 32 64 128 256 512
Input Freq 10MHz 5MHz 2.5MHz 1.25MHz 625kHz 312.5kHz 156.25kHz 78.125kHz
Resolution 100ns 200ns 400ns 0.8µs 1.6µs 3.2µs 6.4µs 12.8µs
Period maximum 6.55ms 13.1ms 26.2ms 52.4ms 104.8ms 209.7ms 419.4ms 838.9ms
ST10F280
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Fi gure 1 6 : Block Diagram of GPT2
2n n=2...9
2n n=2...9
T5EUD
T5IN
CPU Clock
CPU Clock
T6IN
T6EUD
T5
Mode
Control
T6
Mode
Control
GPT2 Timer T5
GPT2 Timer T6
U/D
Interrupt
Request
U/D
GPT2 CAPREL
T60TL
Toggle FF
T6OUT
CAPIN
Reload Interrupt
Request
to CAPCOM
Timers
Capture
Clear
Interrupt
Request
ST10F280
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11 - PWM MOD U LE
11.1 - Standard PW M Module
The pulse width mo dulation module c an generate
up to four PWM output signals using edge-al i gned
or centre-aligned PWM. In addition, the PWM
module can generate PWM burst signals and
single shot outputs . The Tabl e 13 shows the PWM
frequenc ies for different resolutions.
The level of the output signals is selectable and
the PWM module can generate interrupt requests.
Fi gure 1 7 : Block Diagram of PWM Mod ule
Table 13 : P WM Unit Frequencie s and Resolution at 40MHz CPU Clock
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 156.25kHz 39.06kHz 9.77kHz 2.44Hz 610.35Hz
CPU Clock/64 1.6 µs 2.44Hz 610.35Hz 152.58Hz 38.15Hz 9.54Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz
CPU Clock/64 1.6 µs 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz
PPx Period Register
Comparator
PTx
16-bit Up/Down Counter
Shadow Register
PWx Pulse Width Register
Input
Run
Control
Clock 1
Clock 2
Comparator
*
*
*
Up/Down/
Clear Control
Match
Output Control
Match
Write Control
*User readable / writeable register
Enable POUTx
ST10F280
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11. 2 - Ne w PWM Module : XPWM
The new Pul se Width Modulation (XPWM) Module
of the ST10F280 is mapped on the XBUS inter-
face (Address range 00’EC00h-00’ECFFh) and
allows the generation of up to 4 independent
PWM signals.The XPWM is enabled by setting
XPEN bit 2 of the SYSCON register and bit 4 of
the new XPE RCON regist er. The frequency r ange
of these XPWM signals for a 40MHz CPU clock is
from 9.6H z up to 20 MHz for edge aligned sign als.
For center aligned signals the frequency range is
4.8Hz up to 10MHz (see detailed description).
The m ini mum values depend on t he wi dth (16 bit)
and the resolution (CLK/1 or CLK/64) of the
XPWM t imers. T he maxi mum values as sum e t hat
the XPWM output signal changes with every cycle
of the respective timer. In a real application the
maximum XPWM frequency will depend on the
required resolution of the XPWM output signal
(see Figure 18).
The Pulse Width Modulation Module consists of
4 independe nt PWM channel s. Each channe l has
a 16-bit up/down counter XPTx, a 16-bit period
register XPPx with a shadow latch, a 16-bit pu lse
width register XPWx with a shadow latch, two
comparators , and the necessary c ontrol logi c. The
operation o f all four channels is controlled by two
common control registers, XPWMCON0 and
XPWM C ON1, and the interrupt control and status
is handled by one interrupt control register
XP2IC, which is also common for all channels
(see Figure 19).
Fi gure 1 9 : XP WM Channel B lo ck Diagram
Fi gure 1 8 : S FRs and Port Pins As sociated with t he XPWM Module
Data Registers
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXPP0
YYYYY YYYYYYYYYYYXPW0
YYYYY YYYYYYYYYYYXPP1
YYYYY YYYYYYYYYYYXPW1
YYYYY YYYYYYYYYYYXPP2
YYYYY YYYYYYYYYYYXPW2
YYYYY YYYYYYYYYYYXPP3
YYYYY YYYYYYYYYYYXPW3
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXPT0
YYYYY YYYYYYYYYYYXPT1
YYYYY YYYYYYYYYYYXPT2
YYYYY YYYYYYYYYYYXPT3
Co unte r Regi sters
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXPWMCON0
YY- Y- - - -YYYYYYYYXPWMCON1
----- -------YYYYXPOLAR
----- - - -YYYYYYYYXP 2IC E
Control Registers and Interrupt Control
Output on dedicated pins
XPWM0
XPWM1
XPWM2
XPWM3
XPPx
XPWx
XPTx
XPWMCONx
XPOLARx
XPWM Period Register x
XPWM Pulse WIdth Register x
XPWM Counter R egister x
XPWM Control Register 0/1
XPWM Output Polarity Control Register 0/1
XP2IC XPWM Interrupt Control Register
Y
-
E
This bit has a XPWM function
This bit has no XP WH function or is not implemnented
This register belongs to ESFR area
:
:
:
XPPx Period Register
Comparator
XPTx
16-bit Up/Down Counter
Shadow Register
XPWx Pulse Width Register
Input
Run
Control
Clock 1
Clock 2
Comparator
*
*
*
Up/Down/
Clear Control
Match
Output Cont rol
Match
Writ e Control
*User readabl e / wri teable register
Enable XPOUTx
ST10F280
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11.2.1 - Operating Modes
The X PW M module provides four d ifferent operat-
ing mod es:
– Mode 0 Standard PWM generation (edge
aligned PWM) availab le on all four channels
– Mode 1 Symmetrical PWM generation (center
aligned PWM) availab le on all four channels
– Burst mod e combines channels 0 and 1
–
Single shot mode
available on cha nnels 2 and 3
Note: The output signals of the XPWM module
are XORed with the outputs of the
respective bits of XPOLAR register. After
reset these bits are cleared, so the PWM
signals are directly driv en to the output pins.
By setting the respective bits of XPOLAR
register to ‘1’ the PWM signal may be
inverted (XORed with ‘1’) before being
driven to the output pin. The descriptions
below refer to the standard case after reset,
i.e. direct driv ing.
11.2.1 . 1 - Mode 0: Standa rd PW M Generati on
(Edge Aligned PWM)
Mode 0 is selected by clearing the respective bit
XPMx in register XPW MCON1 to ‘0’. In this mode
the timer XPTx of the respective XPWM channel
is always counting up until it reaches the value in
the associated period shadow register. Upon the
next count pulse the timer is reset to 0000h and
continues counting up with subsequent count
pulses. The XPWM output signal is switched to
high level when the timer contents are eq ual to or
greater than the contents of the pulse width
shadow register. The signal is switched back to
low level when the respective timer is reset to
0000h, i.e. belo w the pulse wi dth shadow register.
The period of the resulting PWM signal is deter-
mined by the value of the respective XPPx
shadow register plus 1, counted in units of the
timer resolution.
PWM_PeriodMode0 = [XPPx] + 1
The duty cycle of the XPWM output signal is con-
trolled by the value in the respective pulse width
shadow register. This mechanism allows the
selection of duty cycles from 0% to 100% including
the boundaries. For a value of 0000h the output
will remain at a high level, representing a duty
cycle of 100%. For a v alue higher than the value in
the period register the output will remain at a low
level, which corres ponds to a dut y cycle of 0%.
The Figure 20 illustrates the operation and output
wavefor ms of a X PWM chann el in mode 0 for dif-
ferent v alues in the pulse wi dth register.
This mode is referred to as Edge Aligned PWM,
because the value in the pulse width (shadow)
register only effects the positive edge of the out-
put sig nal. The negative edge is always fixed and
related to the cl earing of the tim er.
Fi gure 2 0 : Operation and Output Waveform in Mode 0
7
67
6
5
34
2
1
0
7
6
5
34
2
1
01
0
XPPx
Period=7
XPTx Count
Value
XPWx Pulse
Width=0
XPWx=1
XPWx=2
XPWx=4
XPWx=6
XPWx=7
XPWx=8
Latch Shadow Registers
Interrupt Request
LSR LSR
Duty Cycle
100%
87.5%
75%
50%
25%
12.5%
0%
LSR
ST10F280
63/186
11.2.1.2 - Mode 1: Symmetrical PWM
Gener ation (Center Aligned PWM)
Mode 1 is selected by setting the respective bit
XPMx in register XPW MCON1 to ‘1’. In this mode
the timer XPTx of the respective XPWM channel
is counting up until it reaches the value in the
associa ted per iod shadow register.
Upon the next count pulse the count direction is
reversed a nd the timer star ts counting down now
with subsequent count pulses until it reaches the
value 0000H. Upon the next count pulse the count
direction is reversed again and the count cycle is
repeated with the followi ng count pulses.
The XPWM output signal is switched to a high
level when the timer contents are equal to or
greater than the contents of the pulse width
sha dow register while the timer is counting up.
The signal is switched back to a low level when
the resp ective timer has counte d down to a value
below the contents of the pulse width shadow reg-
ister. So in mode 1 this PWM value controls both
edges of the output signal.
Note that in mode 1 the per iod o f the P WM signal
is twice the per iod of the timer:
PWM_PeriodMode1 = 2 * ([XPPx] + 1)
The f igure be low illustrates the operation and out -
put wavefor ms of a XPWM channel in mode 1 for
different v al ues in the pulse width register.
This m ode is re ferred to a s Center Aligned PW M,
because the value in the pulse width (shadow)
register effects both edges of the output signal
symmetrically.
Fi gure 2 1 : Operation and Output Waveform in Mode 1
1
7
6
5
34
2
1
01
0
XPPx
Period=7
XPTx Count
Value
XPWx Pulse
Width=0
XPWx=1
XPWx=2
XPWx=4
XPWx=6
XPWx=7
XPWx=8
Latch Shadow Registers
Interrupt Reques
Change Count LSR
Duty Cycle
100%
87.5%
75%
50%
25%
12.5%
0%
0
2
7654321
Direction
LSR
ST10F280
64/186
11.2.1.3 - Burst Mode
Burst m ode i s select ed by setting bit P B01 in reg-
ister XPWMCON1 to ‘1’. This mode co mbines the
signals from XPWM channels 0 and 1 onto the
port pin of channel 0. The output of channel 0 is
replaced with the l ogical AND of channels 0 and 1.
The output of channel 1 can still be used at its
associa ted output pin (if enabled).
Each of the two channels can either operate in
mode 0 or 1.
Note: It is guaranteed by design, that no
spur ious s pikes will occur at the output pin
of channel 0 in this mode. The output of
the AND gate will be transferred to the
output pin synchronously to internal
clocks.
XORing of the PWM signal and the port
output lat ch value is done aft er the ANDing
of channel 0 and 1.
Fi gure 2 2 : Operation and Output Waveform in Burst Mode
XPP0
Period
Value
XPT0
Count
Value
Channel 0
XPP1
XPT1
Channel 0
Channel 1
Resulting
Output
XPOUT0
ST10F280
65/186
11.2.1.4 - Single Sh ot Mode
Single shot mode is selected by setting the
respective bit PSx in regi ster XPWMCO N1 to ‘1’.
This mode is available for XPWM channels 2
and 3.
In this mode the timer XPTx of the respective
XPWM channel is started via software and is
cou nting up until it reaches the value in the asso-
ciated period shadow register. Upon the next
count pulse the timer is cleared to 0000h and
stopped via hardware, i.e. the respective PT Rx bit
is cleared. The XPWM output signal is swi tched to
high level when the timer contents are eq ual to or
greater than the contents of the pulse width
shadow register. The signal is switched back to
low level whe n t he respect ive timer is cl eared, i.e.
is below the pulse width shadow register. Thus
starting a XPWM timer in single shot mode pro-
duc es one single pulse on the respective por t pin,
provided that the pulse width value is between
0000h and the period value. I n order to generate a
further pul se, the timer has to be started again v ia
software by set ting bit PTRx (see Figure 23).
After starting the t imer (i. e. PTR x = ‘1’) the out put
pulse may be modified via software. Writing to
timer XPTx changes the positive and/or negative
edge of the output signal, depending on whether
the pulse has already started (i.e. the output is
h igh ) o r not (i.e. the output is still lo w) . This (m ult i-
ple) re-triggering is always possible while the
timer is running, i.e. after the pulse has started
and before t he timer is stopped.
Loading counter XPTx directly with the value in
the re specti v e XPPx shado w regist er wil l abort the
current PWM pulse upon the next clock pulse
(coun ter is cleared and stoppe d by hardware).
By setting the period (XPPx), the timer start value
(XPTx) and th e pulse width value (XPWx) appro-
priately, the pulse width (tw) and the optional
pulse delay (td) may be varied i n a wide range.
Fi gure 2 3 : Operation and Output Waveform in Single Shot Mod e
7
6
5
34
2
1
0
XPPx
Period=7
XPTx Count
Value
XPWx Pulse
Width=4
Set PTRx
by Software PTRx Reset
by Hardware
PTx stopped
7
6
5
34
2
1
0
Set PTRx
by Software LSR
for Next Pulse
6
5
34
2
1
0
XPPx
Period=7
XPTx Count
Value
XPWx Pulse
Width=4
7
6
5
4
tD
Retrigger after
Write PWx value to PTx
1
0
7
6
5
4
tD
Trigger before Pulse has started :
Write PWx value to PTx;
LSR
tW
tW
Shortens Delay Time tD
Pulse has started :
ST10F280
66/186
11.2.2 - XPWM Module Registers
The XPWM module is controlled via two sets of
registers. The waveforms are selected by the
channel specific registers XPTx (timer), XPPx
(period) and XP Wx ( puls e width).
Three common registers control the operating
modes and the general functions (XPWMCON0
and X PW M CON1) of t he P WM mo dule a s well as
the interru pt behavior (XP2IC ).
Up/Down Counters XPTx
Each cou nter XPTx of a PWM chan nel is clo cked
either directly by the CPU clock or by the CPU
clock divided by 64. Bit PTIx in register
XPWMCON0 selects the respective clock source.
A XPWM counter counts up or down (controlled
by hardware), while its respective run control bit
PTRx is set. A timer is started (PTRx = ’1’) via
software and is stopped (PTRx = ’0’) either via
hardware or software, dep ending on its operating
mode. Control bit PTRx enables or disables the
clock input of count er XPTx rather than controlling
the XPW M output signal.
Note For the register locations please refer to
the Table 14.
Table 15 s um ma rizes t he X P WM freque nc ies that
result from various combinations of operating
mode, counter resolution (input clock) and pulse
wi dth res oluti on.
Period Reg isters XPPx
The 16- bit period register XP Px of a XPWM c han-
nel determines the period of a PWM cyc le , i.e . the
frequenc y of the PWM s ignal. This register is buff-
ered with a sh adow reg ister. The shadow register
is loaded f rom the respec tive XPPx registe r at the
beginning of every new PWM cycle, or upon a
write access to XPPx, while the timer is stopped.
The CPU accesses the XPPx register while the
hardware compares the contents of the shadow
register with the contents of the associated
counter XPTx. When a match is found between
cou nter and X PPx shadow register, the c ounter is
either reset to 0000h, or the count direction is
switched from counting up to counting down,
depending on the selected operati ng mode of that
XPWM c ha nnel. For the regi ster locations refer to
the Table 14.
Pulse Width Registers XPWx
This 16-bit register holds the actual PWM pulse
width value which corresponds to the duty cycle of
the PWM signal. This register is buffered with a
shadow register. The CPU accesses the XPWx
register while the hardware compares the con-
tents of the shadow register with the contents of
the associated counter XPTx. The shadow regis-
ter is loaded from the respective X PWx register at
the beginning of ever y new PWM cycle, or upon a
write access to XPWx, while the timer is
stopped.When the counter v alue is great er than or
equal t o the sha dow regis ter value, t he PWM s ig-
nal is set, otherwise it is reset. The output of the
comparators may be described by the boolean
formula:
PWM output signal = [XPTx]
≥
[XPWx sha dow latch].
This type of comparison allows a fle xib le contr ol of
the PWM signal. For the register locations refer t o
theTable 14.
Table 14 : XPWM Module Channel Specific
Register Addresses
Register Address Register Address
XPW0 EC30h XPT0 EC10h
XPW1 EC32h XPT1 EC12h
XPW2 EC34h XPT2 EC14h
XPW3 EC36h XPT3 EC16h
These registers are not
bit-addressable.
XPP0 EC20h
XPP1 EC22h
XPP2 EC24h
XPP3 EC26h
Table 15 : XPWM Frequency
Mode 0 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 156.25kHz 39.06kHz 9.77kHz 2.44Hz 610.35Hz
CPU Clock/64 1.6µs 2.44Hz 610.35Hz 152.58Hz 38.15Hz 9.54Hz
Mode 1 Resolution 8-bit 10-bit 12-bit 14-bit 16-bit
CPU Clock/1 25ns 78.12kHz 19.53kHz 4.88kHz 1.22kHz 305.17Hz
CPU Clock/64 1.6µs 1.22kHz 305.17Hz 76.29Hz 19.07Hz 4.77Hz
ST10F280
67/186
XPWM Con trol Registers
Register XPWMCON0 controls the function of the timers of the four XPWM channels and the channel
spe cific interrupts. Having the control bits organized in functional groups allows e.g . to star t or stop all 4
XPWM timers simultaneou sly with one bitfield instruct ion. Note: This register is not bi t-addressable.
XPWMCO N0 ( EC 0 0h) Reset Value: 0000h
Register XPWMCON1 controls the operating modes and the outputs of the four XPWM channels. The
basic operating mode for each channel (standard=edge aligned, or symmetrical=center aligned PWM
mode) i s selected by the mode bits XPMx. Burst mode (channels 0 and 1) and s ingle shot mode (channel
2 or 3) are selected by separate control bits. The output signal of each XPWM channel is individually
enabled by bit PENx. If the output is not enabl ed the respect ive pin can only be used to generate an inter-
rupt request. Not e: This regi ster is not bit-addressable.
XPWMCO N1 ( EC 0 2h) Reset Value: 0000h
1514131211109876543210
PIR3 PIR2 PIR1 PIR0 PIE3 PIE2 PIE1 PIE0 PTI3 PTI2 PTI1 PTI0 PTR3 PTR2 PTR1 PTR0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
PTRx 0
1
XPWM Timer x Run Control Bit
Timer XPTx is disconnected from its input clock
Timer XPTx is running
PTIx 0
1
XPWM Timer x Input Clock Selection
Timer XPTx clocked with CLKCPU
TimerX PTx clocked with CLKCPU / 64
PIEx 0
1
XPWM Channel x Interrupt Enable Flag
Interrupt from channel x disabled
Interrupt from channel x enabled
PIRx 0
1
XPWM Channel x Interrupt Request Flag
No interrupt request from channel x
Channel x interrupt pending (must be reset via software)
1514131211109876543210
PS3 PS2 -PB01 ----
PM3 PM2 PM1 PM0 PEN3 PEN2 PEN1 PEN0
RWRW-RW----RWRWRWRWRWRWRWRW
Bit Function
PENx 0
1
XPWM Channel x Output Enable Bit
Channel x output signal disabled, generate interrupt only
Channel x output signal enabled
PMx 0
1
XPWM Channel x Mode Control Bit
Channel x operates in mode 0, edge aligned PWM
Channel x operates in mode 1, center aligned PWM
PB01 0
1
XPWM Channel 0/1 Burst Mode Control Bit
Channels 0 and 1 work independently in respective standard mode
Outputs of channels 0 and 1 are ANDed to XPWM0 in burst mode
PSx 0
1
XPWM Channel x Single Shot Mode Control Bit
Channel x works in respective standard mode
Channel x operates in single shot mode
ST10F280
68/186
11.2.3 - Interrupt Request Generation
Each of the four channels of the XPWM module can generate an individual interrupt request. Each of
these “c hannel in terrupts” can acti vat e t he common “module interrupt”, which actually interrupts the CPU.
This common m odule interrupt is controlled by the XPWM Module Interrup t Control register XP2IC( Xpe-
ripherals 2 control register). The interrupt service routine can determine the active channel interrupt(s)
from the channel specific interr upt request flags PIRx in register XPWMC ON0. The interr upt reque st flag
PIRx of a channel is set at the beginning of a new PW M cycle, i.e. upon loading the shadow registers.
This indi cat es that registers XPPx and X PWx are now ready to receive a new value. If a channel interrupt
is enabled via its respective PIEx bit, also the common interru pt request flag XP2IR in register XP2IC is
set, provided that it is enabled via the c om mo n interrupt enable bit XP2IE .
Note: T he channel interrupt reques t flags (PIRx in register XPWMCO N0) are not automatically cleared
by hardware upon entry into the interrupt service routine, so they must be cleared via software.
The module interrupt request flag XP2IR is cleared by hardware upon entry into the service
routine, regardless of how many channel interrupts were active. However, it will be set again if
during execution of the service rout ine a new channel interr upt request is generated.
XP2IC (F196h / CBh) ESFR Reset Val ue: - - 00h
Note: Refer to the general Interrupt Control Register description for a n explanat ion of the con trol fields.
11. 2 .4 - XPWM Out pu t Signals
The output signals of the four XPWM channels are XPWM3...XPWM0. The output signal of each PWM
channel is individuall y enabled by control bit PENx in register XPWM CON1.
The X PWM signals are X ORed with the out puts of the register XPOL AR(3...0) before being driven to the
outpu t pins. This allows driving t he XP WM s ignal direct ly to the out put pin (X POLA R.x=’0’) o r drivi ng t he
inver ted X PW M signal (XPOLAR. x=’1’).
151413121110987 6543210
--------XP2IR XP2IE ILVL GLVL
RW RW RW RW
Fi gure 2 4 : XPWM Out put Signal Gene ration
Latch XPOLAR.3
PWM 3
Pin XPW M3
Latch XPOLAR.2
PWM 2
Pin XPW M2
Lat ch XPO LAR.1
PWM 1
Pin XPW M1
Latc h XPOLAR.0
PWM 0
Pin XPW M0
&
XPWMCON1.PEN3
XPWMCON1.PEN2
XPWMCON1.PEN0
XPWMCON1.PEN1
XOR
XOR
XOR
XOR
XPWMCON1.PB01
ST10F280
69/186
11.2.5 - XPOLAR Register (polarity of the XPWM channel )
XPOLAR (EC04h) Reset Value: 0000h
S oft wa r e Co nt ro l of the XPW M Outputs
In an application the XPWM output signals are
generally controlled by the XPWM module. How-
ever, it may be nec essar y to influence the level of
the XPWM output pins via software either to ini-
tialize the system or to react on some extraordi-
nary condition, e.g. a system fault or an
emergency.
Clear ing the timer run bit PT Rx stops the associ-
ated counter and leaves the respective output at
i ts curre nt leve l .
The individual XPWM channel outputs are con-
trolled by comparators according to the f ormula:
– PWM output signal = [PTx] ≥ [PWx shadow
latch].
So whenever software changes registers XPTx,
the respectiv e output will reflect the condition after
the change. Loading timer XPTx with a value
greater than or equal to the value in XPW x im m e-
diately sets the respective output, a XPTx value
below the XPWx value clears the respective out-
put.
Note To prevent further PWM pulses from
occurring after such a software
intervention the respective counter must
be stopped first.
1514131211109876543210
------------
XPOLAR.3 XPOLAR.2 XPOLAR.1 XPOLAR.0
RW RW RW RW
Bit Function
XPOLAR.x 0
1
XPOLAR Channel x polarity Bit
Polarity of Channel x is normal
Polarity of Channel x is inverted
ST10F280
70/186
12 - PARALLEL PORTS
In order to accept or generate single external con-
trol signals or parallel data, the ST10F280 pro-
vides up to 143 parallel I/O lines, organized into
two 1 6-bit I /O port (Port 2, XPort9), eight 8-bit I /O
ports (PORT0 made of P0H and P0L, PORT1
made of P1H and P1L, Port 4, Port 6, Port 7,
Port 8) , one 15-bit I /O port (P ort 3) and two 16-bit
input port (Port 5, XPort10).
These port lines may be used for general purpose
Input/Output, controlled via software, or may be
used implicitly by ST10F280’s integrated periph-
erals or the Exter nal Bus Controller.
All port lines are bi t addressable, and all input /out-
put lines are individually (bit-wise) programmable
as i nputs or outputs via direct ion registers ( except
Port 5, XPort10). The I/O ports are true bidirec-
tional port s which are s witched to hi gh i mpedance
stat e when configured as inputs. T he out put dr iv-
ers of seven I/O ports (2, 3, 4, 6, 7, 8, 9) can be
configured (pin by pin) for push/pull operation or
open-drain operation via ODPx control regist ers.
The output driver of the pads are programmable to
adapt the edge characteristics to the application
requirem ent and to improve the EMI behaviour.
This is possible using the POCONx registers for
Ports P0L, P0H, P1L, P1H, P2, P3, P4, P6, P7,
P8. The output dr iver ca pabilities of ALE, RD and
WR control lines a re programmable with the dedi-
cated bits of POCON20 control register.
The input threshold levels are programmable
(TTL/CMOS) for five ports (2, 3, 4, 7, 8) with the
PICON register control bits . The logic lev el of a pin
is c locked into the inpu t latch once per state t ime,
regardless whether the por t is configured for input
or output.
A write operation to a port pin configured as an
input causes the value to be written into the port
output latch, while a read operation returns the
latched state of the pin itself. A read-modify-write
operation reads the value of the pin, modifies it,
and w rites it back to the output latch.
Writing to a pin configured as an output
(DPx. y=‘1’) causes t he output latch and the pin to
have the written value, since the output buffer is
enabled. Read ing th is pin returns th e value of the
output latch. A read-modify-write operation reads
the value of the output latch, modifies it, and
wri tes it back to the output latch, thus also modify-
ing the level at t he pin.
Note: The new I/O ports (XPort9, XPort10) are
not mappe d on the SFR space but on the
internal XBUS interface . The XPort9 and
XPort10 are ena bled by setting XPEN bi t 2
of the SYSCON register and bit 3 of the
new XPERCON register. On the XBUS
interface, t he registers are not bit-address-
able.
ST10F280
71/186
Fi gure 2 5 : S FRs Associated wit h the P arallel Ports
Data Inpu t / Output Register
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YP0L
----- - - -YYYYYYYYP0H
----- - - -YYYYYYYYP1L
----- - - -YYYYYYYYP1H
YYYYY YYYYYYYYYYYP2
Y-YYY YYYYYYYYYYYP3
----- - - -YYYYYYYYP4
YYYYY YYYYYYYYYYYP5
----- - - -YYYYYYYYP6
----- - - -YYYYYYYYP7
----- - - -YYYYYYYYP8
Dire c tion Contro l Registers
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YDP0L
----- - - - YYYYYYYYDP0H
----- - - -YYYYYYYYDP1L
----- - - -YYYYYYYYDP1H
YYYYY YYYYYYYYYYYDP2
Y-YYY YYYYYYYYYYYDP3
----- - - -YYYYYYYYDP4
----- - - -YYYYYYYYDP6
----- - - -YYYYYYYYDP7
----- - - -YYYYYYYYDP8
Thres hold / Open Drain Control
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
-
4
Y
3
Y
2
Y
1
Y
0
YPICON E
YYYYY YYYYYYYYYYYODP2 E
--Y-Y YYYYYYYYYYYODP3 E
----- ---YY------ODP4 E
----- - - -YYYYYYYYODP6 E
----- - - -YYYYYYYYODP7 E
----- - - -YYYYYYYYODP8 E
Output Driver Control Register
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YPOCON0L E
----- - - -YYYYYYYYPOCON0H E
----- - - -YYYYYYYYPOCON1L E
----- - - -YYYYYYYYPOCON1H E
YYYYY YYYYYYYYYYYPOCON2 E
Y-YYY YYYYYYYYYYYPOCON3 E
----- - - -YYYYYYYYPOCON4 E
----- - - -YYYYYYYYPOCON6 E
----- - - -YYYYYYYYPOCON7 E
----- - - -YYYYYYYYPOCON8 E
----- - - -YYYYYYYYPOCO N 20 E *
* RD, W R , ALE lines only
Y : Bit has an I/O function
- : Bit has no I/O dedicated function or is not implemented
Register belongs to ESFR areaE:
YYYYY YYYYYYYYYYYP5DIDIS
PICON: P2LIN P2HIN
P3LIN P3HIN
P4LIN
P7LIN
P8LIN
E
E
E
E
ST10F280
72/186
Fi gure 2 6 : XB US Registers Associated with the Parallel Ports
12.1 - Introduction
12.1 . 1 - Open Drain Mo de
In the ST10F280 som e por ts provide Open Drain
Control. This make is possibl e to switch the output
driver of a por t pin from a push/pull configuration
to an open drain configuration. I n push/p ull mode
a port out put driv er has an upper and a low er t ran-
sistor, thus it can actively drive the line either to a
high or a low level. In open drain mode the up per
transistor is always switched off, and the output
driver can onl y acti vely drive the line to a low le v el.
W hen writing a ‘1’ t o the port latch, the lower tran-
sistor is switched off and the output enters a
high-impedance state. The high level must then
be provided by an external pull-up device. With
this feature, it is possible to connect several port
pins together to a Wired-AND configuration, sav-
ing external glue logic and/or additional software
overhead for enabling/disabling output signals.
This feature is implemented for ports P2, P3, P4,
P6, P7 and P8 (see respective sections), and is
controlled through the respective Open Drain
Control Registers ODPx. These registers allow
the individual bit-wise selection of the open drain
mode for each port line. If the respective control
bit ODPx.y is ‘0’ (default after reset), the output
dri ver is in the push/pull mode. If ODPx. y is ‘1’, the
open drain configuration is selected. Note that all
ODP x registers are located in the ESFR space.
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXP9
YYYYY YYYYYYYYYYYXP9SET
YYYYY YYYYYYYYYYYXP9CLR
YYYYY YYYYYYYYYYYXP10
YYYYY YYYYYYYYYYYXP10DIDIS
----- ----------YXADCMUX
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXDP9
YYYYY YYYYYYYYYYYXP9SET
YYYYY YYYYYYYYYYYXP9CLR
15
Y
14
Y
13
Y
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXOP9
YYYYY YYYYYYYYYYYXOP9SET
YYYYY YYYYYYYYYYYXOP9CLR
Fi gure 2 7 : Output Drivers in Push/Pull Mode and in Open Drain Mode
Pin
Q
Push-Pull Outpu t Driver
Q
Open Drain Output Driver
External
Pullup
Pin
ST10F280
73/186
12.1.2 - Input Threshold Control
The standard inputs of the ST10F280 determine the status of input signals according to TTL levels. In
ord er to ac cept and recognize noisy sig nals, CMOS -like input thresholds can be s elected ins tead of the
standard T TL thresholds for all pins of Por t 2, Port 3, Por t4, Port 7 and Po rt 8. The se speci al thresho lds
are def ined above the TTL thresholds and feature a defined hyst eresis to pre vent the input s f rom toggling
while the respective input signal level is near the thresholds.
The Port Inpu t Control register PICON is used to select these thresholds for each byte of the indicated
ports, i.e. t he 8-bit port s P7 and P8 are controlled b y one bit each while ports P2 and P3 are c ontrolled b y
two bits each.
PICON (F1C4h / E2h) ESFR Reset Value:-00h
All opt ions for individual di rection and output m ode control are available for each pin, i ndependent of the
selec ted input threshold. The input hysteresis provides stable inputs from noisy or slowly chang ing exter-
nal signals.
12.1.3 - Output Driver Control
The port output c ontrol regist ers P OC ONx a llow to s elect the port output driver characteristics of a port.
The aim of these selections is to adapt the output drivers to the application’s requirements, and to
improve t he E MI behaviour of the device. Two characteristics may be selected:
Ed ge characteristic defines the rise/fall time for the res pect ive output, ie. the transition time. Slow edge
reduc e the peak curren ts that are sinked/sourced when c hangi ng th e voltage level of an external ca paci-
tive load. For a bus interface or pins that are changing at frequency higher than 1MHz, however, fast
edges may still be requir ed.
Drive r chara cteristic defines either t he g eneral driving capabil ity of the res pe ctive driver, or if t he dr iver
strength is reduced after the target output level has been reached or not. Reducing the driver strength
incre ases the output’s inter nal resistance, which attenuates noise that is imported via the output line. For
driving LEDs or power tr ansistors , howe ver, a stable high output current ma y still be r equired.
1514131211109876543210
--------P8LIN P7LIN - P4LIN P3HIN P3LIN P2HIN P2LIN
RW RW RW RW RW RW RW RW
Bit Function
PxLIN 0
1
Port x Low Byte Input Level Selection
Pins Px.7...Px.0 switch on standard TTL input levels
Pins Px.7...Px.0 switch on special threshold input levels
PxHIN 0
1
Port x High Byte Input Level Selection
Pins Px.15...Px.8 switch on standard TTL input levels
Pins Px.15...Px.8 switch on special threshold input levels
Fi gure 2 8 : Hys teres is for Special Input Thresholds
Inpu t level
Bit state
Hysteresis
ST10F280
74/186
For each f eature, a 2-bit control field (ie. 4 bits) is prov ided for each group of 4 port pads (i e. a port nibb le),
in port output control registers POCONx.
POCO Nx (F0yyh / zzh) for 8-bit Ports E SFR Reset Val ue: - - 00h
PO CONx (F0yy h / zzh) for 16-bit Ports ES F R Reset Value: 000 0h
Note: In case of reading an 8 bit P0CONX register, high Byte ( bit 15..8) i s read as 00h.
Port Con t r ol Register Allo c a t io n
The table below lists th e defined POCON regist ers and the allocation of control bitfields and port pins:
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
1514131211109876543210
PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PN0DC PN0EC
RW RW RW RW RW RW RW RW
Bit Function
PNxEC 00
01
10
11
Port Nibble x Edge Characteristic (rise/fall time)
Fast edge mode, rise/fall times depend on the driver’s dimensioning.
Slow edge mode, rise/fall times ~60 ns
Reserved
Reserved
PNxDC 00
01
10
11
Port Nibble x Driver Characteristic (output current)
High Current mode: Driver always operates with maximum strength.
Dynamic Current mode: Driver strength is reduced after the target level has been reached.
Low Current mode: Driver always operates with reduced strength.
Reserved
Control
Register Physical
Address 8-Bit
Address Controlled Port
POCON0L F080h 40h P0L.7...4 P0L.3...0
POCON0H F082h 41h P0H.7...4 P0H.3...0
POCON1L F084h 42h P1L.7...4 P1L.3...0
POCON1H F086h 43h P1H.7...4 P1H.3...0
POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0
POCON3 F08Ah 45h P3.15, P3.13...12 P3.11...8 P3.7...4 P3.3...0
POCON4 F08Ch 46h P4.7...4 P4.3...0
POCON6 F08Eh 47h P6.7...4 P6.3...0
POCON7 F090h 48h P7.7...4 P7.3...0
POCON8 F092h 49h P8.7...4 P8.3...0
ST10F280
75/186
Dedicated P ins Output Con trol
Programmable pad drivers also are supported for the dedicated pins ALE, RD and WR. For these pads, a
spe cial POCON20 register is provided.
PO CON20 (F0A Ah / 5h) ESFR Reset Value: 0000h
12.1.4 - Alternate Port Functions
Each por t line h as one associated programmable
alternate input or output function. PORT0 and
PORT1 may be used as the address and data
lines when acc essing external memory.
P ort 4 outputs the additional segment address bits
A23/A19/A18/A16 in systems where more than
64 KBytes of memory are to be accessed directly.
Port 6 provides the optional chip select outputs
and the bus arbitration lines.
Port 2, Port 7 and Port 8 are associated with the
capt ure in puts or com par e outpu ts of t he CA PCOM
units and/or with the o ut puts of the PWM module.
Port 2 is al so used for fast external interrupt inputs
and for timer 7 input.
Port 3 includes alternate input/output functions of
timers, serial interfaces, the optional bus control
signal BHE/WRH and the system clock output
(CLKOUT).
Port 5 is us ed for the analog input channels to the
A/D conve rter or timer control si gnals.
If an alternate output function of a pin is to be
used, the direction of this pin must be pro-
grammed for output (DPx.y=‘1’), except for some
signals that are used directly after reset and are
configured automatically. Otherwise the pin
remains in the high-impedance state and is not
effected by the alternate output function. The
respec tive port latc h should hol d a ‘1’, because its
output is ANDed with the alternate output data
(except for PWM out put signals).
If an alternate inp ut fun ction of a p in is used, the
directio n o f the pin must be programmed for input
(DPx.y= ‘0’) if an extern al device is dr iving the pin.
The input direction is the default after reset. If no
external device is connected to the pin, however,
one can also set the di rection for this pi n t o out put.
In this case, the pin reflects the state of the port
output latch. Thus, the alternate input function
reads the value stored in the port output latch.
This can be used for testing purposes to allow a
software trigger of an alternate input function by
wr iting to the port output latch.
1514131211109876543210
--------PN1DC PN1EC PN0DC PN0EC
RW RW RW RW
Bit Function
PN0EC 00
01
10
11
RD, WR Edge Characteristic (rise/fall time)
Fast edge mode, rise/fall times depend on the driver’s dimensioning.
Slow edge mode, rise/fall times ~60 ns
Reserved
Reserved
PN0DC 00
01
10
11
RD, WR Driver Characteristic (output current)
High Current mode:Driver always operates with maximum strength.
Dynamic Current mode:Driver strength is reduced after the target level has been reached.
Low Current mode:Driver always operates with reduced strength.
Reserved
PN1EC 00
01
10
11
ALE Edge Characteristic (rise/fall time)
Fast edge mode, rise/fall times depend on the driver’s dimensioning.
Slow edge mode, rise/fall times ~60 ns
Reserved
Reserved
PN1DC 00
01
10
11
ALE Driver Characteristic (output current)
High Current mode:Driver always operates with maximum strength.
Dynamic Current mode:Driver strength is reduced after the target level has been reached.
Low Current mode:Driver always operates with reduced strength.
Reserved
ST10F280
76/186
On m ost of the port lin es, the user sof tware is responsible for setting the pro per direction when using an
alternate input or output function of a pi n. This i s done by setting or clearing the di rection control bi t DPx.y
of the pin before e nabling the alternate function. There are por t lines, however, where the direction of the
port line is switched automatically. For instance, in the multiplexed external bus modes of PORT0, the
direction mu st be switche d several times for an instruction fetc h in order to output the address es and t o
input the data. Obviously, this cannot be done through instructions. In these cases, the direction of the
port line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate l evel of the port output latches check how t he alternate data output is com-
bined with the respect ive port latch output.
There is one ba sic str ucture for all port lines wit h only a n al ter nate input function. Port lines with only an
alternate output function, however, have different structures due to the way the direction of the pin is
switched and depending on whether the pin is acc essible by the user software or not in the alternate func-
tion mode.
All por t lines that are not used for these al ter nate functions may be used as general purpose I/O lines.
When using port pins for general purpose out put, the i nitial output v alue should be written to the port latch
pri or to enab ling t he output dri v ers, in order to a void undesired transitions on the output pins. This applies
to single pins as well as to pin groups (see ex am ple s below).
SINGLE_BIT: BSET P4.7 ; Initial output level is "high"
BSET DP4.7 ; Switch on the output driver
BIT_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high"
BFLDH DP4, #24H, #24H ; Switch on the output drivers
Note: When using se veral BSET pairs to control more pins of one port , these pairs must be separat ed by
instruct ions, which do not reference the respecti v e port (see “Particular Pi peline Eff ects” in Chap-
ter 6 - Central Proces sing Unit (CPU)).
12.2 - P ORT0
The two 8-bit ports P 0H and P0L represent the higher and lower part of POR T0, respect ively. Both halves
of P ORT 0 can be written (e.g. via a PEC transfer) without effect ing the other half.
If this port is used for general purpose I/O , the direction of each line can be configured via the cor respond-
ing direction registers DP0H and DP0L.
P0L (FF00h / 80h) SF R Reset Value: - - 0 0h
P0H (FF02h / 81h) SF R R eset Value: - - 00h
DP0L (F100h / 80h) ESFR Reset Value: - - 00h
1514131211109876543210
--------P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0
RW RW RW RW RW RW RW RW
Bit Function
P0X.y Port data register P0H or P0L bit y
1514131211109876543210
- - - - - - - - DP0L.7 DP0L.6 DP0L.5 DP0L.4 DP0L.3 DP0L.2 DP0L.1 DP0L.0
RW RW RW RW RW RW RW RW
ST10F280
77/186
DP0H (F102h / 81h) ESFR Res e t Valu e : - - 0 0 h
12.2.1 - Alternate Functions of PORT 0
W hen an external bus is enabled, P ORT0 is us ed
as data bus or address/data bus.
Note that an external 8-bit de-multiplexed bus only
uses P0L, wh ile P0H is free for I/O (provided that
no other bus mode is enabled).
PORT0 is also used to select the system start-up
configuration. During reset, PORT0 is configured
to input, and each line is held high through an
inter nal pull-up device. Each line can now be indi-
vidu ally pulled to a low leve l ( see DC-level s peci fi-
cations) through an external pull-down device. A
default configuration is selected when the respec-
tive PORT0 l ines are at a high level. Through pull-
ing individual lines to a low level, this default can
be changed acc ording to the needs of the applica-
tions.
The internal pull-up devices are designed such
that an external pul l-down resistors can be used to
apply a correct l ow level. Thes e external pull-down
resistor s c an remain connected to the PORT0 pins
also during norma l operat ion, however, care has to
be taken such that they do not disturb the normal
function of PORT0 (this might be the case, for
exam ple , if the ext ern al resist or is too strong). With
the end of reset, the selected bus co nfigur ation will
be wr itten to the BUSCON0 regist er. The configu-
ration of the high byte of PORT0, will be copied
into the special register RP0H. This read-only reg-
ister holds the selection for the number of chip
selects and segment addresses. Software can
read this register in order to react according to the
selected configurat ion, if required. When the reset
is terminated, the internal pull-up devices are
switched off, and PORT0 will be switched to the
appropriate operating m ode.
During external accesses in multiplexed bus
modes PORT0 first outputs the 16-bit intra-seg-
ment address as an alternate output function.
PORT0 is then switched to high-impedance input
mode to read the incoming instruction or da ta. In
8-bit data bus mode, two memory cycles are
required for word accesses, the first for the low
byte and the seco nd for the high byte of the word.
Durin g write cycles PORT0 outputs the data byte
or word after outputting the address. During ex ter-
nal accesses in de-multiplexed bus modes
PORT0 reads the incoming instruction or data
word or outputs the data byte or wor d.
1514131211109876543210
- - - - - - - - DP0H.7 DP0H.6 DP0H.5 DP0H.4 DP0H.3 DP0H.2 DP0H.1 DP0H.0
RW RW RW RW RW RW RW RW
Bit Function
DP0X.y Port direction register DP0H or DP0L bit y
DP0X.y = 0: Port line P0X.y is an input (high-impedance)
DP0X.y = 1: Port line P0X.y is an output
Fi gure 2 9 : PORT0 I/O and Alternate Funct ions
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
PORT0
P0H
P0L
Alternate Function a) b) c) d)
General Purpose
Input/Output 8-bit
Demultiplexed Bus 16-bit
Demultipl exed Bu s 8-bit
Multiplexed Bus 16-bit
Multiplexed Bus
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ST10F280
78/186
When an external b us mode i s enabled, the di rec-
tion of t he port pin and the l oading of data int o the
port out put latch are controlled by the bus control-
ler hardw are.
The input o f the por t output l atch is d isconnected
from the internal bus and is switched to the line
labeled “Alternate Data Output” via a multiplexer.
The alt ernate data can be t he 16-bit intr a-segment
address or the 8/16-bit data information. The
incoming data on PORT0 is read on the line
“Alternate Data Input”. While an external bus
mode is enabled, the user software should not
wr ite to the port output latch, otherwise unpredict-
able results may occur. When the external bus
mode s are disabled, the contents of the direction
register last written by the user becomes active.
The Figure 30 shows the structure of a PORT0
pi n.
Fi gure 3 0 : Block Diagram of a PORT0 Pin
Direction
Latch
Write DP0H.y / DP0L.y
Read DP0H.y / DP0L.y
Port Output
Latch
Write P0H.y / P0L.y
Read P0H.y / P0L.y
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
Alternate
Direction
Input
Latch
P0H.y
P0L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
CPU Clock
ST10F280
79/186
12.3 - P ORT1
The two 8-bit ports P 1H and P1L represent the higher and lower part of POR T1, respect ively. Both halves
of P ORT 1 can be written (e.g. via a PEC transfer) without effect ing the other half.
If this port is used for general purpose I/O , the direction of each line can be configured via the cor respond-
ing direction registers DP1H and DP1L.
P1L (FF04h / 82h) SF R Reset Value: - - 0 0h
P1H (FF06h / 83h) S F R R eset Value: - - 00h
DP1L (F104h / 82h) ESFR Reset Value: - - 00h
DP1H (F106h / 83h) ESFR Reset Value: - - 00h
12.3.1 - Alternate Functions of PORT 1
When a de-multiplexed external bus is enabled,
PORT1 is used as address bus.
Note that de-multiplexed bus modes use PORT1
as a 16-bi t port. Otherwise all 16 port li nes can be
used f or general purpose I /O.
The upper four pins of PORT1 (P1H.7...P1H.4)
also serve as capture input lines for the
CAPCOM 2 unit (CC27I O. ..CC24IO).
As all other capture inputs , the capture i nput func-
tion of pins P1H.7...P1H.4 can also be used as
external interrupt inputs (200 ns sample rate at
40MHz CPU clo ck).
During external accesses in de-multiplexed bus
modes PORT1 outputs the 16-bit intra-segment
addres s as an alter nat e output function.
During external accesses in multiplexed bus
modes, when no BUSCON register selects a
de-multiple xed bus mode, POR T1 is not used and is
available for general purpose I/O (see Figure 31).
When an external b us mode i s enabled, the di rec-
tion of t he port pin and the l oading of data int o the
port out put latch are controlled by the bus control-
ler hardware. The input of the port output latch is
disconnected from the internal bus and is
switched to the line labeled “Alternate Data Out-
put” via a multiplexer. The alternate data is the
16-bit int ra-s egment address.
1514131211109876543210
--------P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------P1H.7 P1H.6 P1H.5 P1H.4 P1L.3 P1H.2 P1H.1 P1H.0
RW RW RW RW RW RW RW RW
Bit Function
P1X.y Port data register P1H or P1L bit y
1514131211109876543210
--------DP1L.7 DP1L.6 DP1L.5 DP1L.4 DP1L.3 DP1L.2 DP1L.1 DP1L.0
RW RW RW RW RW RW RW RW
1514131211109876543210
--------DP1H.7DP1H.6DP1H.5DP1H.4DP1H.3DP1H.2DP1H.1DP1H.0
RW RW RW RW RW RW RW RW
Bit Function
DP1X.y Port direction register DP1H or DP1L bit y
DP1X.y = 0: Port line P1X.y is an input (high-impedance)
DP1X.y = 1: Port line P1X.y is an output
ST10F280
80/186
Whi le an external bus mode is enabled, the user software should not write to the port output l atch, other-
wise unpredictable results may occur. When the external bus modes are disabled, the contents of the
direction register last written by the user becomes active.
The figure below shows the structure of a POR T 1 pin.
12.4 - Port 2
If this 16-bit port is used for general purpos e I/O, the direction of each line can be configu red via the cor-
respo nding direction register DP2. Each port line can be switched into push/pul l or o pen drain mode via
the open drain control register ODP2.
Fi gure 3 1 : PORT1 I/O and Alternate Funct ions
Fi gure 3 2 : Block Diagram of a PORT1 Pin
PORT1
P1H
P1L
Alternate Function a)
Genera l Purpos e Input/Outpu t 8/16-bit Demul tipl exed Bus
b)
CAPCOM2 Capture Inputs
P1H.7
P1H.6
P1H.5
P1H.4
P1H.3
P1H.2
P1H.1
P1H.0
P1L.7
P1L.6
P1L.5
P1L.4
P1L.3
P1L.2
P1L.1
P1L.0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CC27I
CC26I
CC25I
CC24I
Direction
Latch
Write DP1H.y / DP1L.y
Read DP1 H.y / DP1L.y
Port Output
Latch
Write P1H.y / P1L.y
Read P1H.y / P1L.y
Internal Bus
MUX
0
1
MUX
0
1
MUX
0
1
“1”
Input
Latch
P1H.y
P1L.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
Port Data
Output
Alternate
Data
Output
CPU Cloc k
ST10F280
81/186
P2 (FF C0h / E0h) SFR Reset Value: 0000h
DP2 (FFC2h / E1h) SFR Reset Value: 0000h
ODP2 (F1C2h / E1h) ESFR Reset Value: 0000h
12.4.1 - Alternate F unctions of Port 2
All Port 2 lines (P2.15...P2.0) serve as capture
inputs or compare outputs (CC15IO...CC0IO) for
the CAPC OM 1 unit.
W hen a Port 2 line is us ed as a capture inpu t, the
state of the input latch, which represents the s tate
of the port pin, is directed to the CAPCOM unit via
the line “Alternate Pin Data Input”. If an external
capture trigger signal is used, the direction of the
respective pin must be set to input. If the directi on
is set to output, the state of the port output latch
will be read since the pin represents the state of
the output latch. This can be used to trigger a cap-
ture event through software by settin g or clearing
the port latch. Note that in the output configura-
tion, no external device may drive the pin, other-
wise confl icts would occur .
When a Port 2 line is used as a compare output
(compare m odes 1 and 3), the compa re event (or
the timer overflow in compare mode 3) directly
effects the port output latch. In compare mode 1,
when a valid compare match occurs, th e state of
the por t output latch is read by the CAPCOM con-
trol hardware via the line “Alternate Latch Data
Input”, inverted, and written back to the latch via
the li ne “Alternate Data Output”.
The port output latch is clocked by the signal
“Compare Trigger” which is generated by the
CAPCOM unit. In compare mode 3, when a match
occurs, the value '1' is written to the port output
latch via the line “Alternate Data Output”. When
an overflow of the corresponding timer occurs, a
'0' is written to the port output latch. In both cases,
the out put latch is clock ed by t he signal “Compare
Trigger”.
1514131211109876543210
P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
P2.y Port data register P2 bit y
1514131211109876543210
DP2.
15 DP2.
14 DP2.
13 DP2.
12 DP2.
11 DP2.
10 DP2.9 DP2.8 DP2.7 DP2.6 DP2.5 DP2.4 DP2.3 DP2.2 DP2.1 DP2.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
DP2.y Port direction register DP2 bit y
DP2.y = 0: Port line P2.y is an input (high-impedance)
DP2.y = 1: Port line P2.y is an output
1514131211109876543210
ODP2
.15 ODP2
.14 ODP2
.13 ODP2
.12 ODP2
.11 ODP2
.10 ODP2
.9 ODP2
.8 ODP2
.7 ODP2
.6 ODP2
.5 ODP2
.4 ODP2
.3 ODP2
.2 ODP2
.1 ODP2
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
ODP2.y Port 2 Open Drain control register bit y
ODP2.y = 0: Port line P2.y output driver in push/pull mode
ODP2.y = 1: Port line P2.y output driver in open drain mode
ST10F280
82/186
The di rection of the pi n should be se t to output by
the user, otherwise the pin will be in the
high-im pedance state and will not refl ect the state
of the output latch.
As can be seen f rom the port structure below, the
user software always has free access to the port
pin even when it is used as a compare output.
This is useful for setting up the initial level of the
pin when using compare mode 1 or the dou-
ble-register mode. In t hese modes, unlike in com-
pare mod e 3, the pin is not set to a specific value
when a compare match occurs, but is toggled
instead.
When the user wants to wri te to the port pi n at the
same time a compare tri gger t ries to clock the out-
put latch, the wr ite operation of the user software
has priority. Each time a CPU wr ite access to the
port output latch occurs, the input multiplexer of
the port output latch is switched to the line con-
nected to the internal bus. The port output latch
will receive the value from the internal bus and the
h ardware tr igg e red cha nge will be los t .
As all other capture inputs , the capture i nput func-
tion of pins P2.15...P2.0 can also be used as
external interrupt inputs (200 ns sample rate at
40MHz CPU clo ck).
The upper eight Port 2 lines (P2.15...P2.8) also
can serve as Fast External Interrupt inputs from
EX0IN to EX7IN. (Fast external interrupt sampling
rate is 25ns at 40MHz CPU clock).
P2.15 in addition serves as input for CAPCOM2
timer T7 (T7IN).
The table below summarizes the alternate func-
tion s of Port 2.
Fi gure 3 3 : Port 2 I/O and Alternate Functions
Port 2 Pin Alternate Function a) Alternate Function b) Alternate Function c)
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
CC0IO
CC1IO
CC2IO
CC3IO
CC4IO
CC5IO
CC6IO
CC7IO
CC8IO
CC9IO
CC10IO
CC11IO
CC12IO
CC13IO
CC14IO
CC15IO
-
-
-
-
-
-
-
-
EX0IN Fast External Interrupt 0 Input
EX1IN Fast External Interrupt 1 Input
EX2IN Fast External Interrupt 2 Input
EX3IN Fast External Interrupt 3 Input
EX4IN Fast External Interrupt 4 Input
EX5IN Fast External Interrupt 5 Input
EX6IN Fast External Interrupt 6 Input
EX7IN Fast External Interrupt 7 Input
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
T7IN Timer T7 Ext. Count Input
Port 2
Alternate Function a)
General Purpose
Input / Output CAPCOM1
Capture Input / Compare Output
b)
Fast External
Interrupt Input
c)
CAPCOM2
Timer T7 Input
P2.15
P2.14
P2.13
P2.12
P2.11
P2.10
P2.9
P2.8
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
CC15IO
CC14IO
CC13IO
CC12IO
CC11IO
CC10IO
CC9IO
CC8IO
CC7IO
CC6IO
CC5IO
CC4IO
CC3IO
CC2IO
CC1IO
CC0IO
EX7IN
EX6IN
EX5IN
EX4IN
EX3IN
EX2IN
EX1IN
EX0IN
T7IN
ST10F280
83/186
The pins of Port 2 combin e internal bus data with alternate data output before the por t latch input.
Fi gure 3 4 : Block Diagram of a Port 2 Pin
Open Drain
Latch
Write ODP2.y
Read O DP2.y
Direction
Latch
Write DP2.y
Read D P2.y
Internal Bus
MUX
0
1
Alternate Data In p u t
Input
Latch
P2.y
CCyIO
Output
Buffer
x = 7...0
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P2 .y
Compare Trigger
Read P 2.y
Fast External Interrupt Input
CPU Clo ck
EXxIN
y = 15...0
ST10F280
84/186
12.5 - Port 3
If th is 15-bit port is used for general purpos e I/O, the direction o f e ach lin e can be configured by the cor-
respo nding direction re gister DP3. Most por t lines can be sw itched into push/pull or open drai n mode by
the open drain control register ODP3 (pins P3.15, P3 .14 and P3.12 do not support open drain mode).
Due to pin limitations register bit P3.14 is not connected to an output pin.
P3 (FF C4h / E2h) SFR Reset Value: 0000h
DP3 (FFC6h / E3h) SFR Reset Value: 0000h
ODP3 (F1C6h / E3h) SFR Reset Value: 0000h
1514131211109876543210
P3.15 - P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
P3.y Port data register P3 bit y
1514131211109876543210
DP3
.15 - DP3
.13 DP3
.12 DP3
.11 DP3
.10 DP3.9 DP3.8 DP3.7 DP3.6 DP3.5 DP3.4 DP3.3 DP3.2 DP3.1 DP3.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
DP3.y Port direction register DP3 bit y
DP3.y = 0: Port line P3.y is an input (high-impedance)
DP3.y = 1: Port line P3.y is an output
1514131211109876543210
- - ODP3
.13 - ODP3
.11 ODP3
.10 ODP3
.9 ODP3
.8 ODP3
.7 ODP3
.6 ODP3
.5 ODP3
.4 ODP3
.3 ODP3
.2 ODP3
.1 ODP3
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
ODP3.y Port 3 Open Drain control register bit y
ODP3.y = 0: Port line P3.y output driver in push-pull mode
ODP3.y = 1: Port line P3.y output driver in open drain mode
ST10F280
85/186
12.5.1 - Alternate Functions of Port 3
The pins of Port 3 serve for various functions which include external timer control lines, the two serial
interfaces and the cont rol lines BHE/WRH and CLKOUT.
The por t structure of the Port 3 pins depends on
thei r alternat e fun ction (see Figure 36).
When the on-chip peripheral associated with a
Por t 3 pin is configured to use the alternate input
funct ion, it reads the input latch, which represents
the st ate of the pin, via the line labeled “A lternat e
Data Inpu t”. Port 3 pins with alternate input func-
tions are:
T0IN, T2IN, T3IN, T4IN, T3 EUD and CAPIN.
When the on-chip peripheral associated with a
Port 3 pin is conf i gured to use the alternate output
functi on, its “Alternate Data Out put” line is A NDed
with the port output latch line. When using these
alternate functions, t he user must s et the direction
of the port line to output (DP3.y=1) and must set
the port output latch (P3.y=1). Ot herwise the pin is
in its high-impedance state (when configured as
input ) or the pin i s stuck at '0' (when the port out-
put latch is cleared).
W hen the alternate output functions are not used,
the “Alternate Data Output” line is in its inactive
state, which is a high level ('1'). Port 3 pins with
alternate output functions are: T6OUT, T3OUT,
TxD0 and CLKOUT.
Table 16 : Port 3 Alternative Functions
Port 3 Pin Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
T0IN CAPCOM1 Timer 0 Count Input
T6OUT Timer 6 Toggle Output
CAPIN GPT2 Capture Input
T3OUT Timer 3 Toggle Output
T3EUD Timer 3 External Up/Down Input
T4IN Timer 4 Count Input
T3IN Timer 3 Count Input
T2IN Timer 2 Count Input
MRST SSC Master Receive / Slave Transmit
MTSR SSC Master Transmit / Slave Receive
TxD0 ASC0 Transmit Data Output
RxD0 ASC0 Receive Data Input / (Output in synchronous mode)
BHE/WRH Byte High Enable / Write High Output
SCLK SSC Shift Clock Input/Output
--- No pin assigned!
CLKOUT System Clock Output
Fi gure 3 5 : Port 3 I/O and Alternate Functions
Port 3
No Pin
Alternate Function a) b)
Genera l Purpos e Input/Outp ut
P3.15
P3.13
P3.12
P3.11
P3.10
P3.9
P3.8
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
CLKOUT
SCLK
BHE
RxD0
TxD0
MTSR
MRST
T2IN
T3IN
T4IN
T3EUD
T3OUT
CAPIN
T6OUT
T0IN
WRH
ST10F280
86/186
When the on-c hi p peripheral assoc iated with a P ort 3 pin is configured to use bot h the alternate input and
output function, the descriptions above apply to the respective current operating mode. The direction
must be set accordingly. Port 3 pins with alternate input/output functions are: M TSR, MRST, RxD0 and
SCLK.
Note: Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit
DP3.15=’ 1’ is not required.
Fi gure 3 6 : B lock Diagram of Port 3 Pin with Al ternate Input or Alternate Output Function
Open Drain
Latch
Write ODP3.y
Read ODP3.y
Direction
Latch
Write DP3.y
Read DP3.y
Internal Bus
MUX
0
1
Alternate
Data
Input
Input
Latch
P3.y
Output
Buffer
y = 13, 11...0
Port Output
Latch
Read P3.y
Write P3.y
&
Alternate
Data Output
Port Data
Output
CPU Clock
ST10F280
87/186
Pin P3.12 (BHE/WRH) is another pin wi th an alternate output f unction, howe ver , its structure is slightly dif-
ferent (see f igure F igure 37). A fter reset the B HE or WRH function must be used de pending on the sys-
tem start-up configuration. In either of these cases, there is no possibility to program any port latches
before. Thus, the appropr iat e a lternate func tion is s electe d au tomat ically. If BHE/WRH is not used in the
system, this pin can b e used fo r gene ral purp ose I/O by disabling t he altern ate f unction (B YTDIS = ‘1’ /
WRCFG=’0’).
Note: Enabling the BHE or WRH function automatically enables the P3.12 output driver. Setting bit
DP3.12=’ 1’ is not required.
During bus hold, pin P3.12 is switched back to its standard function and is then controlled by
DP3.12 and P 3.12. Keep DP 3.12 = ’0’ in t his case to ensure floating in hold mode.
12.6 - Port 4
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
spo nding direction register DP4.
P4 (FF C8h / E4h) SF R Reset Value: - - 0 0h
Fi gure 3 7 : B lock Diagram of Pins P3.15 (CLKOUT) and P3.12 (BHE/WRH)
1514131211109876543210
--------P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
RW RW RW RW RW RW RW RW
Bit Function
P4.y Port data register P4 bit y
Direction
Latch
Write DP3.x
Read DP3.x
Port Output
Latch
Write P3.x
Read P3.x
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
P3.12/BHE
P3.15/CLKOUT
Output
Buffer
x = 15, 12
Alternate
Function
Enable
CPU Clock
ST10F280
88/186
DP4 (FFCAh / E5h) SF R Reset Value: - - 0 0h
For CAN configuration suppo r t (see Chapter 1 5 - CA N Modul es), Por t 4 has a n ew open drain function,
con trolled with the new ODP 4 register:
ODP4 (F1CAh / E5h) SFR R eset Value: - - 00h
Note: Only bits 6 and 7 are im plemented, al l other
bits will be read as “0”.
12.6.1 - Alternate Functions of Port 4
Durin g external bus cycles that use segm entation
(i.e. an address space above 64K Bytes) a num-
ber of Port 4 pins may output the segment
address lines. The number of pins used for seg-
ment address output determines the directly
access ible external address spac e.
The other pins of Port 4 may be used for general
purpose I/O. If segment address lines are
selected, the alternate function of Port 4 may be
necessa ry to access e .g. e xternal memory directly
after reset. For this reason Port 4 will b e switched
to t his alternate func tion automatically.
The num ber of segment address l ines is selected
via PORT0 during reset. The selected value can
be read from bitfield SALSEL in register RP0H
(read only) to check the configuration during run
time.
Devices with CAN inte rfaces use 2 pins of Por t 4
to interface each CAN Module to an external CAN
transceiver. In this case the number of possible
seg men t address lines is reduced.
The table below summarizes the alternate func-
tions of Port 4 depending on the number of
select ed segment address lines (coded via bitfi eld
SALSEL)..
1514131211109876543210
--------DP4.7 DP4.6 DP4.5 DP4.4 DP4.3 DP4.2 DP4.1 DP4.0
RW RW RW RW RW RW RW RW
Bit Function
DP4.y Port direction register DP4 bit y
DP4.y = 0: Port line P4.y is an input (high-impedance)
DP4.y = 1: Port line P4.y is an output
1514131211109876543210
--------ODP4.
7
ODP4.
6------
RW RW
Bit Function
ODP4.y Port 4 Open drain control register bit y
ODP4.y = 0: Port line P4.y output driver in push/pull mode
ODP4.y = 1: Port line P4.y output driver in open drain mode if P4.y is not a segment address line output
Port 4 Pin Std. Function
SALSEL=01 64 KB Altern. Function
SALSEL =11 2 56KB Altern. Function
SALSEL=00 1MB Altern. Function
SALSEL =10 16MB
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
GPIO
GPIO
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Seg. Address A16
Seg. Address A17
GPIO
GPIO
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
GPIO/CAN2_RxD
GPIO/CAN1_RxD
GPIO/CAN1_TxD
GPIO/CAN2_TxD
Seg. Address A16
Seg. Address A17
Seg. Address A18
Seg. Address A19
Seg. Address A20
Seg. Address A21
Seg. Address A22
Seg. Address A23
ST10F280
89/186
Fi gure 3 9 : Block Diagram of a Port 4 Pin
Fi gure 3 8 : Port 4 I/O and Alternate Functions
Port 4
Alternate Function a)
General Purpose
Input / Output
b)
Seg ment Address
Lines Cans I/O and General Purpose
Input / Output
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
A23
A22
A21
A20
A19
A18
A17
A16
CAN2_TxD
CAN1_TxD
CAN1_RxD
CAN2_RxD
p4.3
P4.2
P4.1
P4.0
Direction
Latch
Write DP4.y
Read DP4.y
Port Output
Latch
Write P4.y
Read P4.y
Internal Bus
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
P4.y
Output
Buffer
y = 7...0
Alternate
Function
Enable
CPU Clock
ST10F280
90/186
Fi gure 4 0 : Block Diagram of P4.4 and P4.5 Pins
Direction
Latch
Writ e DP4.x
Read DP4.x
Port Output
Latch
Writ e P4.x
Read P4.x
Internal Bu s
MUX
0
1
MUX
0
1
Alternate
Data
Output
MUX
0
1
“1”
Input
Latch
Clock
P4.x
x = 5, 4
Alternate
Function
Enable 0
1
“0”
MUX
MUX
0
1
“0”
Output
Buffer
&
≤
1y = 1, 2 (CAN Channel)
z = 2, 1
a = 0, 1
b = 1, 0
CANy.RxD
XPERCON.a
XPERCON.b
(CANyEN)
(CANzEN)
ST10F280
91/186
Fi gure 4 1 : Block Diagram of P4.6 and P4.7 Pins
MUX
0
1
"0"
Open Drain
Latch
Write ODP4.x
Read ODP4.x
Direction
Latch
Write DP4.x
Read DP4.x
Internal Bus
MUX0
1
Input
Latch
Clock
P4.xOutput
Buffer
Port Output
Latch
Read P4.x
Write P4.x Alternate
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
MUX
0
1
"1" MUX
MUX
0
1
"0"
MUX
0
1
MUX
≤
1
CANy.TxD
XPERCON.a
(CANyEN)
XPERCON.b
(CANzEN)
Data ou tput
x = 6, 7
y = 1, 2 (CAN Channel)
z = 2, 1
a = 0, 1
b = 1, 0
ST10F280
92/186
12.7 - Port 5
This 16-bit input port can only read data. There is no output l atch and no direction register. Data written to
P5 will be lost.
P5 (FFA2h / D1h) SFR Reset Value: XXXXh
Alternate Functions of Por t 5
Each line of Port 5 is also connected to one of t he m ultiplexer of t he A nal og/ Di gi tal C onverter . All port lines
(P5.15... P 5.0) can acc ept analog s i gnals (A N15... AN 0) that can be converted b y the ADC. No special pro-
gram ming is requi red for pi ns that shall be used as analog in puts. Some pins of Port 5 also serve as exter-
nal timer control lines f or GPT1 and GPT2. The table below summarize s the alternate functions of P ort 5.
1514131211109876543210
P5.15 P5.14 P5.13 P5.12 P5.11 P5.10 P5.9 P5.8 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0
RRRRRRRRRRRRRRRR
Bit Function
P5.y Port data register P5 bit y (Read only)
Table 17 : Port 5 Alternate Functions
Port 5 Pin Alternate Function a) Alternate Function b)
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
Analog Input AN0
Analog Input AN1
Analog Input AN2
Analog Input AN3
Analog Input AN4
Analog Input AN5
Analog Input AN6
Analog Input AN7
Analog Input AN8
Analog Input AN9
Analog Input AN10
Analog Input AN11
Analog Input AN12
Analog Input AN13
Analog Input AN14
Analog Input AN15
-
-
-
-
-
-
-
-
-
-
T6EUD Timer 6 ext. Up/Down Input
T5EUD Timer 5 ext. Up/Down Input
T6IN Timer 6 Count Input
T5IN Timer 5 Count Input
T4EUD Timer 4 ext. Up/Down Input
T2EUD Timer 2 ext. Up/Down Input
Fi gure 4 2 : Port 5 I/O and Alternate Functions
Port 5
Alternate Function a)
General Purpose Inputs
b)
A/D Converter Inputs Timer Inputs
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P5.15
P5.14
P5.13
P5.12
P5.11
P5.10
P5.9
P5.8 AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
T2EUD
T4EUD
T5IN
T6IN
T5EUD
T6EUD
ST10F280
93/186
Port 5 pins have a special port st ructure (see F igure 43), first because it is an input onl y port, and second
because the analog input channels are directly connected to the pins rather than to the input l at ches.
12.7.1 - Port 5 Schmitt Trigger Analog Inputs
A Sc hmitt tr igger protecti on can be ac tivated on each pin of Port 5 by setting the dedicat ed bit of register
P5DIDIS.
P5DIDIS (FFA4h / D2h ) SFR Reset Value: 0000h
12.8 - Port 6
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
sponding dir ection register DP6. Each port line can be switched into push/pull or open drain mode via the
open drain control register ODP 6.
P6 (FF CCh / E6h) SF R Reset Value: - - 00h
DP6 (FFCEh / E 7h) SFR R eset Value: - - 00h
Fi gure 4 3 : Block Diagram of a Port 5 Pin
1514131211109876543210
P5DI
DIS.15 P5DI
DIS.14 P5DI
DIS.13 P5DI
DIS.12 P5DI
DIS.11 P5DI
DIS.10 P5DI
DIS.9 P5DI
DIS.8 P5DI
DIS.7 P5DI
DIS.6 P5DI
DIS.5 P5DI
DIS.4 P5DI
DIS.3 P5DI
DIS.2 P5DI
DIS.1 P5DI
DIS.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
P5DIDIS.y Port 5 Digital Disablel register bit y
P5DIDIS.y = 0: Port line P5.y digital input is enabled (Schmitt trigger enabled)
P5DIDIS.y = 1: Port line P5.y digital input is disabled (Schmitt trigger disabled, necessary for input
leakage current reduction)
1514131211109876543210
--------P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0
RW RW RW RW RW RW RW RW
Bit Function
P6.y Port data register P6 bit y
1514131211109876543210
--------DP6.7 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0
RW RW RW RW RW RW RW RW
Read Port P5.y
Intern al Bus
Input
Latch
CP U Clock
P5.y/ANy
Read
Buffer
to Sample + Hold
Circuit
Channel
Select
Analog
Switch
y = 15...0
ST10F280
94/186
ODP6 (F1CEh / E7h) ESFR Reset Value: - - 00h
12.8.1 - Alternate Functions of Port 6
A programmable number of chip select signals (CS4...CS0) derived from the bus control registers
(BUSCON4...BUSCON0) can be output on the 5 pins of Port 6. The number of chip select signals is
selec ted via P ORT0 d uring reset. Th e selected value can b e read from bitfield CSSEL i n register RP0H
(read only) e.g. in order to check the confi guration during run t i me. T he table below summarizes the alter-
nate functions of P ort 6 depending on the number of selected chip select lines (coded via bitfield CSSEL).
Fi gure 4 4 : Port 6 I/O and Alternate Functions
Bit Function
DP6.y Port direction register DP6 bit y
DP6.y = 0: Port line P6.y is an input (high-impedance)
DP6.y = 1: Port line P6.y is an output
1514131211109876543210
--------ODP6.7ODP6.6ODP6.5ODP6.4ODP6.3ODP6.2ODP6.1ODP6.0
RW RW RW RW RW RW RW RW
Bit Function
ODP6.y Port 6 Open Drain control register bit y
ODP6.y = 0: Port line P6.y output driver in push/pull mode
ODP6.y = 1: Port line P6.y output driver in open drain mode
Table 18 : Port 6 Alternate Functions
Port 6 Pin Al tern. Funct ion
CSSEL = 10 Altern. Function
CSSEL = 01 Altern. Function
CSSEL = 00 Altern. Function
CSSEL = 11
P6.0
P6.1
P6.2
P6.3
P6.4
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
General purpose I/O
Chip select CS0
Chip select CS1
Gen. purpose I/O
Gen. purpose I/O
Gen. purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
Gen. purpose I/O
Gen. purpose I/O
Chip select CS0
Chip select CS1
Chip select CS2
Chip select CS3
Chip select CS4
P6.5
P6.6
P6.7
HOLD External hold request input
HLDA Hold acknowledge output
BREQ Bus request output
Port 6
Alternate Function a)
General Purpose Input/Output
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
BREQ
HLDA
HOLD
CS4
CS3
CS2
CS1
CS0
ST10F280
95/186
The chip select lines of Port 6 have an internal weak pull-up device. This device is switched on d uring
reset. This feature is implemented to drive the c hip select lines high during reset in order to avoid multiple
chip select i on.
After reset the CS f unction must be used, if selected so . In t his case there is no possibility to program any
port lat ches before. Thus the alternate function ( CS) is selec t e d a utomatic ally in this cas e.
Note: The open drain output option can only be selected via software earliest during the initialization
routine; at least signal CS0 will be in pus h / pu ll ou t pu t dr iver mode dire c tly a f ter r e s et.
Fi gure 4 5 : B lock Diagram of Port 6 Pins wi t h an Alternate Output Function
* P6.5 has only alternate input function.
12.9 - Port 7
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
sponding dir ection register DP7. Each port line can be switched into push/pull or open drain mode via the
open drain control register ODP 7.
MUX
0
1
"0"
Open Drain
Latch
Write ODP6.y
Read ODP6.y
Direction
Latch
Write DP6.y
Read DP6.y
Inte rnal Bus
MUX
0
1
Input
Latch
CPU Cl o c k
P6.y
Output
Buffer
Port Output
Latch
Read P6.y
Write P6.y Alternate *
Data
Output MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable
y = (0...4, 6, 7)
ST10F280
96/186
P7 (FF D0h / E8h) SF R Reset Value: - - 0 0h
DP7 (FFD2h / E9h) SF R Reset Value: - - 0 0h
ODP7 (F1D2h / E9h) ESFR Reset Value: - - 00h
12.9.1 - Alternate Functions of Port 7
The uppe r 4 lines of Por t 7 (P7.7...P7.4) ser ve as
capture inputs or compare outputs
(CC31IO...CC28IO) for the CA PC OM 2 unit.
The usage o f the por t lines by the CAPCO M unit,
its accessibility via software and the precautions
are the same as describe d for the Port 2 lines.
As all other capture inputs , the capture i nput func-
tion of pins P7.7...P7.4 can also be used as exter-
nal interru pt input s (200 ns sa mp le rate at 40MHz
CPU clock).
The lower 4 lines of Por t 7 (P7 .3...P7.0) serve as
outputs from the PWM module
(POU T3...POUT0). At these pins the value of the
respective port output latch is XORed with the
value of the PWM output rather than ANDed, as
the ot her p ins do. T his a llows to use the alternat e
output value either as it is ( port latch holds a ‘0’) or
invert its level at the pin (port latch holds a ‘1’).
Note that the PWM outputs must be enabled via
the respective PENx bits in P WMCON1.
The table below summarizes the alternate func-
tion s of Port 7.
1514131211109876543210
- - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0
RW RW RW RW RW RW RW RW
P7.y Port dat a reg i ster P7 bit y
1514131211109876543210
- - - - - - - - DP7.7 DP7.6 DP7.5 DP7.4 DP7.3 DP7.2 DP7.1 DP7.0
RW RW RW RW RW RW RW RW
DP7.y Po rt direction register DP 7 bit y
DP7.y = 0: Port line P 7. y is an input (high impedance)
DP7.y = 1: Port line P 7. y is an output
1514131211109876543210
--------ODP7.7 ODP7.6 ODP7.5 ODP7.4 ODP7.3 ODP7.2 ODP7.1 ODP7.0
RW RW RW RW RW RW RW RW
ODP7.y Port 7 Open Drain co ntro l reg ister bit y
ODP7.y = 0: P ort line P7.y output dri v er in push-pul l mode
OD P7.y = 1: Port line P7.y output driver in open drain mode
Table 19 : Port 7 Alternate Functions
Port 7 Pin Alternate Function
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
POUT0 PWM mode channel 0 output
POUT1 PWM mode channel 1 output
POUT2 PWM mode channel 2 output
POUT3 PWM mode channel 3 output
CC28IO Capture input / compare output channel 28
CC29IO Capture input / compare output channel 29
CC30IO Capture input / compare output channel 30
CC31IO Capture input / compare output channel 31
ST10F280
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The port str uc tur es of Po rt 7 differ in the way the output latc hes are connected t o t he internal bus and t o
the pin dr iver (s ee the two Figure 47). Pins P7.3...P7.0 (POUT3...POUT0) XO R the alternat e data output
with the port latch output, which al lo ws to use the alternate data directly or invert ed at the pin driv er.
Fi gure 4 6 : Port 7 I/O and Alternate Functions
Fi gure 4 7 : Block Diagram of Port 7 Pins P7.3...P7.0
Port 7
Alternate Function
General Purpose Input/ Output
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
CC31IO
CC30IO
CC29IO
CC28IO
POUT3
POUT2
POUT1
POUT0
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
In ternal Bus
MUX
0
1
Input
Latch
CPU Clock
P7.y/POUTy
Output
Buffer
P ort Ou tput
Latch
Read P7.y
=1
Port Data
Output EXOR
Alternate
Data
Output
Write P7.y
y = 0...3
ST10F280
98/186
Fi gure 4 8 : Block Diagram of Port 7 Pins P7.7...P7.4
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
Internal Bus
MUX
0
1
Alte rnat e La t ch
Data Input
Input
Latch
Clock
P7.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P7.y
Compare Trigger
Read P7.y
y = (4...7)
z = (28...31)
Alte rnat e P in
Data Input
ST10F280
99/186
12.1 0 - Po rt 8
If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corre-
sponding dir ection register DP8. Each port line can be switched into push/pull or open drain mode via the
open drain control register ODP 8.
P8 (FF D4h / EAh) SF R Reset Value: - - 0 0h
DP8 (FFD6h / EBh) SFR R es et Value: - - 00h
ODP8 (F1D6h / EBh) ESFR Reset Value: - - 00h
12.10 .1 - Altern ate Functions of Por t 8
The 8 lines of Port 8 (P8.7...P8. 0) serve as capture inputs or compare outputs (CC23IO...CC16IO) for the
CAPC OM 2 unit.
The usage of the port lines by the CAP COM unit, its accessibility via software and the precautions are the
same as descr ibed fo r the Port 2 lines.
As all other capture inputs, the capture input function of pins P8.7...P8.0 can also be used as external
interr upt inputs (200 ns sample rate at 40MHz CPU clock).
The Table 20 summarizes the alter nate fun ction s of Port 8.
1514131211109876543210
- - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0
RW RW RW RW RW RW RW RW
P8.y Port data register P8 bit y
1514131211109876543210
- - - - - - - - DP8.7 DP8.6 DP8.5 DP8.4 DP8.3 DP8.2 DP8.1 DP8.0
RW RW RW RW RW RW RW RW
DP8.y Port direction register DP8 bit y
DP8.y = 0: Port line P8.y is an input (high impedance)
DP8.y = 1: Port line P8.y is an output
1514131211109876543210
--------ODP8.7ODP8.6 ODP8.5 ODP8.4 ODP8.3 ODP8.2 ODP8.1 ODP8.0
RW RW RW RW RW RW RW RW
ODP8.y Port 8 Open Drain control register bit y
ODP8.y = 0: Port line P8.y output driver in push-pull mode
ODP8.y = 1: Port line P8.y output driver in open drain mode
Table 20 : Port 8 Alternate Functions
Port 7 Alternate Function
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
CC16IO Capture input / compare output channel 16
CC17IO Capture input / compare output channel 17
CC18IO Capture input / compare output channel 18
CC19IO Capture input / compare output channel 19
CC20IO Capture input / compare output channel 20
CC21IO Capture input / compare output channel 21
CC22IO Capture input / compare output channel 22
CC23IO Capture input / compare output channel 23
ST10F280
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The port str uc tur es of Po rt 8 differ in the way the output latc hes are connected t o t he internal bus and t o
the pin driver (see the Figure 50). Pins P8.7...P8.0 (CC23IO...CC16IO) combine internal bus data and
alte rn ate data output before the port latch input, as do the Po rt 2 pins.
Fi gure 4 9 : Port 8 I/O and Alternate Functions
Fi gure 5 0 : Block Diagram of Port 8 Pins P8.7...P8.0
Port 8
Alternate FunctionGeneral Purpose Input / Output
P8.7
P8.6
P8.5
P8.4
P8.3
P8.2
P8.1
P8.0
CC23IO
CC22IO
CC21IO
CC20IO
CC19IO
CC18IO
CC17IO
CC16IO
Open Drai n
Latch
Write 0DP8.y
Read 0DP8.y
Direction
Latch
W rite D P8.y
Read DP8.y
Internal Bus
MUX
0
1
Alte rn ate L at ch
Data Inp ut
Input
Latch
CPU Clock
P8.y
CCzIO
Output
Buffer
Alternate
Data
Output
MUX
0
1Output
Latch
≥
1
Write Port P8.y
Co m p are T rigger
Read P8.y
y = (7...0)
z = (16...23)
Alternate Pin D at a Inpu t
ST10F280
101/186
12.1 1 - XPort 9
The XPort9 is enabled by setting XPEN bit 2 of the SYSCON register an d XPORT 9EN b it 3 of the new
XPE RCON register. On t he XBUS interface, the register are not bit-addressable
This 16-bit port is used f or general purpose I /O, the directi on of each line can be configured via the corre-
sponding direction register XDP9. Each port l ine can be switched into push/pull or open drain mode via
the open drain control register XODP9.
All port l ines can be individually (bit-wise) programmed. The “ bit-address able” f eature is availabl e via spe-
cific “Set” and “Clear” regist ers: XP9SET, XP9CLR, XDP9SET, XDP9CLR, XODP9SET, XODP9CLR.
XP9 (C100h) Reset Value: 0000h
XP9SET (C102h) Reset Value: 0000h
XP9CLR (C104 h ) Reset Value: 0000h
XDP9 (C200h) Reset Value: 0000h
1514131211109876543210
XP9.15 XP9.14 XP9.13 XP9.12 XP9.11 XP9.10 XP9.9 XP9.8 XP9.7 XP9.6 XP9.5 XP9.4 XP9.3 XP9.2 XP9.1 XP9.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
XP9.y Port data register XP9 bit y
1514131211109876543210
XP9SET
.15 XP9SET
.14 XP9SET
.13 XP9SET
.12 XP9SET
.11 XP9SET
.10 XP9SET
.9 XP9SET
.8 XP9SET
.7 XP9SET
.6 XP9SET
.5 XP9SET
.4 XP9SET
.3 XP9SET
.2 XP9SET
.1 XP9SET
.0
WWWWWWWWWWWWWWWW
Bit Function
XP9SET.y Writing a ‘1’ will set the corresponding bit in XP9 register, Writing a ‘0’ has no effect.
1514131211109876543210
XP9CLR
.15 XP9CLR
.14 XP9CLR
.13 XP9CLR
.12 XP9CLR
.11 XP9CLR
.10 XP9CLR
.9 XP9CLR
.8 XP9CLR
.7 XP9CLR
.6 XP9CLR
.5 XP9CLR
.4 XP9CLR
.3 XP9CLR
.2 XP9CLR
.1 XP9CLR
.0
WWWWWWWWWWWWWWWW
Bit Function
XP9CLR.y Writing a ‘1’ will clear the corresponding bit in XP9 register, Writing a ‘0’ has no effect.
1514131211109876543210
XDP9
.15 XDP9
.14 XDP9
.13 XDP9
.12 XDP9
.11 XDP9
.10 XDP9
.9 XDP9
.8 XDP9
.7 XDP9
.6 XDP9
.5 XDP9
.4 XDP9
.3 XDP9
.2 XDP9
.1 XDP9
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
XDP9.y Port direction register XDP9 bit y
XDP9.y = 0: Port line XP9.y is an input (high-impedance)
XDP9.y = 1: Port lineX P9.y is an output
ST10F280
102/186
XDP9 SE T (C2 0 2h) Reset Value: 0000h
XDP9CLR (C204h) Reset Value: 0000h
XODP 9 (C300h) Reset Value: 0000h
XODP 9SET (C302h) Reset Value: 0000h
XODP9CLR (C304h) Reset Value: 0000h
1514131211109876543210
XDP9
SET.15 XDP9
SET.14 XDP9
SET.13 XDP9
SET.12 XDP9
SET.11 XDP9
SET.10 XDP9
SET.9 XDP9
SET.8 XDP9
SET.7 XD P9
SET.6 XD P9
SET.5 XDP9
SET.4 XDP9
SET.3 XDP9
SET.2 XDP9
SET.1 XDP9
SET.0
WWWWWWWWWWWWWWWW
Bit Function
XDP9SET.y Writing a ‘1’ will set the corresponding bit in XDP9 register, Writing a ‘0’ has no effect.
1514131211109876543210
XDP9
CLR.15 XDP9
CLR.14 XDP9
CLR.13 XDP9
CLR.12 XDP9
CLR.11 XDP9
CLR.10 XDP9
CLR.9 XDP9
CLR.8 XDP9
CLR.7 XDP9
CLR.6 XDP9
CLR.5 XDP9
CLR.4 XDP9
CLR.3 XDP9
CLR.2 XDP9
CLR.1 XDP9
CLR.0
WWWWWWWWWWWWWWWW
Bit Function
XDP9CLR.y Writing a ‘1’ will clear the corresponding bit in XDP9 register, Writing a ‘0’ has no effect.
1514131211109876543210
XODP9
.15 XODP9
.14 XODP9
.13 XODP9
.12 XODP9
.11 XODP9
.10 XODP9
.9 XODP9
.8 XODP9
.7 XODP9
.6 XODP9
.5 XODP9
.4 XODP9
.3 XODP
9.2 XODP9
.1 XODP9
.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
XODP9.y Port 9 Open Drain control register bit y
XODP9.y = 0: Port line XP9.y output driver in push/pull mode
XODP9.y = 1: Port line XP9.y output driver in open drain mode
1514131211109876543210
XODP9
SET.15 XODP9
SET.14 XODP9
SET.13 XODP9
SET.12 XODP9
SET.11 XODP9
SET.10 XODP9
SET.9 XODP9
SET.8 XODP9
SET.7 XODP9
SET.6 XODP9
SET.5 XODP9
SET.4 XODP9
SET.3 XODP9
SET.2 XODP9
SET.1 XODP9
SET.0
WWWWWWWWWWWWWWWW
Bit Function
XODP9SET.y Writing a ‘1’ will set the corresponding bit in XODP9 register, Writing a ‘0’ has no effect.
1514131211109876543210
XODP9
CLR.15 XODP9
CLR.14 XODP9
CLR.13 XODP9
CLR.12 XODP9
CLR.11 XODP9
CLR.10 XODP9
CLR.9 XODP9
CLR.8 XODP9
CLR.7 XODP9
CLR.6 XODP9
CLR.5 XODP9
CLR.4 XODP9
CLR.3 XODP9
CLR.2 XODP9
CLR.1 XODP9
CLR.0
WWWWWWWWWWWWWWWW
Bit Function
XODP9CLR.y Writing a ‘1’ will clear the corresponding bit in XODP9 register, Writing a ‘0’ has no effect.
ST10F280
103/186
12.1 2 - XPort 10
The XPor t1 0 is enabled by set ting XPEN bit 2 of the SYSCON register and bit 3 of the new XPERCON
register. On the X BUS in terface, the register are not bit-addres sable. This 16-bit input por t can only read
data. There is no output latch and no direction register. Data written to XP10 will be lost.
XP10 (C380h) Reset Value: XXXXh
12.12 .1 - Altern ate Functions of XPort 10
Each line of XPort 10 is also connect ed t o one of the multiplexer o f the Ana log/Digital Converter. All port
lines (XP10. 15. ..XP10.0) can accept analog signals (AN31...AN16) that can be con verted b y the ADC. No
speci al programming is required for pins that shall be used as analog inputs. The Table 21 summarizes
the alternate functions of XPort 10.
Fi gure 5 1 : PORT10 I/O and Alternate Functions
1514131211109876543210
XP10
.15 XP10
.14 XP10
.13 XP10
.12 XP10
.11 XP10
.10 XP10
.9 XP10
.8 XP10
.7 XP10
.6 XP10
.5 XP10
.4 XP10
.3 XP10
.2 XP10
.1 XP10
.0
RRRRRRRRRRRRRRRR
Bit Function
XP10.y Port data register XP10 bit y (Read only)
Table 21 : X Port 10 Alter nat e Funct ions
XPort 10 Pin Alternate Function
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P10.8
P10.9
P10.10
P10.11
P10.12
P10.13
P10.14
P10.15
Analog Input AN16
Analog Input AN17
Analog Input AN18
Analog Input AN19
Analog Input AN20
Analog Input AN21
Analog Input AN22
Analog Input AN23
Analog Input AN24
Analog Input AN25
Analog Input AN26
Analog Input AN27
Analog Input AN28
Analog Input AN29
Analog Input AN30
Analog Input AN31
A/D Conver ter Input
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
XPort 10
Alternate Function
General Purpose Input
XP10.15
XP10.14
XP10.13
XP10.12
XP10.11
XP10.10
XP10.9
XP10.8
XP10.7
XP10.6
XP10.5
XP10.4
XP10.3
XP10.2
XP10.1
XP10.0
ST10F280
104/186
12.12.2 - Ne w Disturb Protectio n on Analog Inputs
A new regist er is provi ded f or additional disturb protection support on analog inputs for Port X P10:
XP10DIDIS (C382h) Reset Value: 0000h
1514131211109876543210
XP10
DIDIS
.15
XP10
DIDIS
.14
XP10
DIDIS
.13
XP10
DIDIS
.12
XP10
DIDIS
.11
XP10
DIDIS
.10
XP10
DIDIS.9 XP10
DIDIS.8 XP10
DIDIS.7 XP10
DIDIS.6 XP10
DIDIS.5 XP10
DIDIS.4 XP10
DIDIS.3 XP10
DIDIS.2 XP10
DIDIS.1 XP10
DIDIS.0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
XP10DIDIS.y 0
1
XPort 10 Digital Disable register bit y
Port line XP10.y digital input is enabled (Schmitt trigger enabled)
Port line XP10.y digital input is disabled (Schmitt trigger disabled, necessary for input leakage
current reduction)
ST10F280
105/186
13 - A/ D CON VE RTER
13.1 - A/D Conver ter Module
A 10-bit A/D converter with 2 x 16 multiplexed
input channels and a sample and hold circuit is
integrated on-chip. This A/D Converter does not
have the self-calibration feature. Thus, guaran-
teed Total Unadjusted Error is + 2 LSB. Refer to
Section 20 .3.1 - A/D Converter Characteristics for
detailled characteristics. The sample time (for
loadin g the capac itors) an d the co nversion time is
programmable and can be adjusted to the exter-
nal circuitr y. Converti on time is fully equivalent to
the o ne of previous generation A/D self-calibrated
Converter.
To remove high frequency components from the
analog input signal, a low-pass fi lter m ust be con-
nec ted at the ADC input.
Overrun e rror detection/protec tion is controlled by
the ADDAT register. Either an interrupt request is
generated when the result of a previous conver-
sion ha s not been rea d from t he result register at
the time the next conversion is complete, or the
next conversion is suspended until the previous
result has been read. For applications which
require less than 16 analog input channels, the
remaining channel inputs can be used as digital
input port pins.
The A/D converter of the ST10F280 supports four
different conversi on modes:
Single channel conversion mode the analog
level on a specified c hannel is sam pled once a nd
conver ted to a digital result.
Single channel continuous mode the analog
lev el on a spec ified channel is repeatedly sampled
and converted without software intervention.
Auto scan mode the analog lev els on a pre-spec-
ified number of channels are s equentially sampled
and conv erted.
Auto scan continuous mode the number of
pre -specified ch annels is repeat edl y sampled and
conver ted.
Channel Injection Mode injects a channel into a
running sequence without disturbing this
sequence. The peripheral event controller stores
the conversion results in memor y without entering
and exit i ng i nterrup t r out i nes for eac h data transfer.
ST10F280
106/186
13.2 - Multiplexage of two blocks of 16 Analog Inputs
The A DC can manag e 16 analog inputs, so t o inc reas e its capabilit y, a new XADC MUX r egist er is added
to control the multiplexage between the first block of 16 channels on Por t5 and the second block of 16
channels on X Port10. The conversion result r egister stays i dentical and only a softw are management can
deter m ine the block in use.
The XADCMUX register is enabled by setting XPEN bit 2 of the SYSCON register and bit 3 of the new
XPERCON register
XADCMUX (C384h) Reset Value: 0000h
Fi gure 5 2 : Bl oc k Diagram
151413121110987654321 0
---------------XADCMUX
RW
Bit Function
XADCMUX.0 0
1Default configuration,analog inputs on port P5.y can be converted
Analog inputs on port XP10.y can be converted
y = 15...0
Input
latch
Input
latch
ADC
Read P ort P5.y
Read Port XP10.y
Channel Select
XADCMUX
0
1
CPU clock
CPU clock
P5.y
XP10.y
16
16
XBUS
Interna l Bus
ST10F280
107/186
13.3 - XTI MER P er ip heral (trig ger fo r ADC
chann el injection)
This new peripheral is dedicated for the Channel
Injection Mode of the A/D converter. This mode
inject s a c hann el i nto a running s equen ce without
disturbing this sequence. The peripheral event
controller st ores the conver sion results in memory
without entering and exiting interrupt routines for
each data transfer.
A channel injection can be triggered by an event
on Capture/Compare CC31 (Port P7.7) of the
CAPC OM 2 unit.
The dedicated output XADCINJ of the XTIMER
must be connected externally on the input P7.7/
CC31.
Due to the multiplexed inputs, at a time, the ADC
exclusively converts the Port5 inputs or the
XPor t10 input s. If one "y" channe l has to be used
continuously in injection mode, it must be exter-
nally hardware connected to the Port5.y and
XP ort 10.y inputs.
The XTIMER peripheral is enabled by setting
XPEN bit 2 of the SYSCON register and bit 3 of
the new XPERCON register.
13.3.1 - Main Features
The X TIMER features are :
– 16 bits l in ear timer / 4 bi t s exponential presc aler
– Counting between 16 bits “start value” and 16
bits “end value”
– Counting peri od bet ween 4 cycles and 2**33 cy-
cles (100 ns and 214s using 40MHz CPU clock)
– 1 t rigger ouput (XADCINJ)
– P rogram m able f unctions :
•Internal clock XCLK is derivated from the CPU
clock and has the same period
•Up count i ng / down counting
•Reload enable
•Continue / stop modes
– 4 m em ory mapped registers :
•Control / pres caler
•Sta rt valu e
•End value
•Current value
Table 22 : The Different Counting Modes
TLE TCS TCVR(n) = TEVR TUD TEN TCVR(n+1) comments
x x x x 0 TCVR(n) Timer disable
x 0 1 x 1 Stop
x x 0 0 TCVR(n)-1 Decrement
0 1 1 Decrement (Continue)
x x 0 1 TCVR(n)+1 Increment
0 1 1 Increment (Cont inue)
1 1 1 x TSVR Load
ST10F280
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13.3.2 - Register Description
1 3.3. 2.1 - TCR : Time r Cont rol Re gi s te r
XTCR (C000 h ) Reset Value: 000 0h
1514131211109876543210
000000 TFP[3:0] TCM TIE TCS TLE TUD TEN
RRRRRR RW RWRWRWRWRWRW
Bit Function
TEN Timer Enable
When TEN = ’0’, the Timer is disabled (reset value). To avoid glitches, it is recommended to modify TCR in
2 steps, first with new values and and second by setting TEN.
TUD Timer Up / Down Counting
When TUD = ’0’, the Timer is counting "down" (reset value), ie the TCVR (’current value’) register content
is decrement ed.
When TUD = ’1’, the Timer is counting "up", ie the TCVR (’current value’) register content is incremented.
TLE Timer Load Enable
When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded with TSVR (’ start value’)
register content when TLE = ’1’. When TLE = ’0’ (reset va lue), the next state of TCVR depe nds on TCS
bit.
TCS Timer Continue / Stop
When TLE = ’0’ (no l oad) an d when the counter has reached its end value (TCVR = TEVR), the T CVR
content continues to increment / decrement according to TUD bit when TCS = ’1’ (continue mode).
When TCS = ’0’ (stop mode reset value), TCVR is stopped and its content is frozen.
TIE Timer Output Enable
When the counter has reached its end value (TCVR = TEVR), the XADCINJ output is set when TIE = ’1’.
When TIE = ’0’ (reset value), XADCINJ output is disabled (= ’0’).
TCM Timer Clock Mode Must be Cleared
TCM = ’0’ (reset value), the TCVR clock is derived from internal XCLK clock according to TFP bits.
TFP[3:0] Timer Frequency Prescaler
When TC M = ’0’ (in ter na l clock), the T CVR re giste r clock is der ived from th e XCLK clock input by dividing
XCLK by 2**(2+ TFP). The coding is as follows :
- 0000 : prescaler by 2 (reset value), XCLK divided by 4
- 0001 : prescaler by 4, XCLK divided by 8
- 0010 : prescaler by 8, XCLK divided by 16
- ...
- 1111 : prescaler by 2**16, XCLK divided by 2**17
ST10F280
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13.3.2.2 - XTSVR :Timer Start Value Register
XTSVR (C002h) Reset Value: 0000h
13.3.2.3 - XTEVR : Timer End Value Register
XTEVR (C004h) Reset Value: 0000h
13.3.2.4 - XTCVR : Timer Current Value Register
XTCVR (C006h) Reset Value: 0000h
13.3.2.5 - Registers Mapping
1514131211109876543210
TSVR
RW
Bit Function
TSVR[15:0] Timer Start Value
TSVR contains the data to be transferred to the TCVR ’Current Value’ register when :
1) - TEN = ’1’ (TIM enable),
- TLE = ’1’ (TIM Load enable),
- TCVR = TEVR (count period finished),
- TCS = ’1’ (stop mode disabled).
2) - first counting clock rising edge after the timer start (the timer starts on TEN rising edge).
1514131211109876543210
TEVR
RW
Bit Function
TEVR[15:0] Timer End Value
TEVR contains the data to be compared to the TCVR ’Current Value’ register.
1514131211109876543210
TCVR
R
Bit Function
TCVR[15:0] Timer Current Value
TCVR contains the current counting value. When TCVR = TEVR, TCVR content is changed
according to Table 22. The TCVR clock is derived from internal XCLK clock according to TFP bits
when TCM = ’0’.
Table 23 : Tim er Registers Mapping
Address (Hexa) Register Name Reset Value (Hexa) Access
C000h XTCR : Control 0000h RW
C002h XTSVR : Start Value 0000h RW
C004h XTEVR : End Value 0000h RW
C006h XTCVR : Current Value 0000h R
ST10F280
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13.3.3 - Block Diagram
13.3.3.1 - Clock s
The X TCVR register c lock is the prescaler output.
The prescaler allows to divide the basic register
frequen cy in order t o offe r a wide range of count -
ing period, from 2**2 to 2**33 cycles (note that 1
cycle = 1 XCLK per iods).
13.3.3.2 - Registers
The XTCVR register input is linked to several
sources:
– XTS VR register (start value) for reload when the
period is finish ed, or for load when the timer is
starting.
– Incr ementer output when the ’up’ mode is selected,
– Decrementer output when the ’down’ mode is
selected.
– The selection between the sources is made
through the XTCR control register.
When st arting t he tim er, by sett ing TEN bit of TCR
to ’1’, XTCVR will be loaded with XTSVR value on
the first rising edge of the counting cloc k. That’s to
say that for counting from 0000h to 0009h for
example, 10 counting clock rising edges are
required.
The XTCVR register output is continuously com-
pared to the XTEVR register to dete ct the end of
the c ounting period. When the registers are equal,
sev eral actions are made depending on t he XTCR
con trol register con tent :
– The output X ADCINJ is conditional l y generated,
– XTCV R is loaded with XTSVR or s tops or contin-
ues to count (see Table 22 ).
XTEVR, XTSVR and all TCR bits except TEN
must not be modified while the timer is counting,
ie while TEN bit of TCR = ’1’. The timer behaviour
is not guaranteed if this rule is not respected. It
impl ies that the timer can be configured only when
stopped (TEN = ’0’). When programming the
timer , XTEVR, XTSVR and XTCR bits except TEN
can be m odified, with T EN = ’ 0’; then the timer is
started by modifying only TEN bit of TCR. To stop
the timer, only TEN bit shoul d be modified, from ’1’
to ’0 ’.
Fi gure 5 3 : XTIMER Bl o c k D i a gram
XTCR
XTSVR
XTCVR
Prescaling
XTEVR
ctl
ctl =
ctl
ctl
diff
XCLK
- 1
+ 1
Timer output
DATA
(XADCINJ)
ST10F280
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13.3.3.3 - Timer output (XADCINJ)
The X ADCINJ output is the result of the (XTCVR = XTEV R) flag after differentiation. The durati on of the
outpu t lasts two cycles (50ns at 40 MHz).
Fi gure 54 : XADCINJ Timer Output
Figu re 55 : External Connection for ADC Channel Injection
XADCINJ
4 TC L =50ns
XCLK
Input
Latch
XTIMER
Clock
P7.7/CC31
XADCINJ
CAPCOM2 Output
trigger
for ADC
UNIT
channel
injection
ST10F280
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14 - SERIAL CHANNE L S
Serial communication with other microcontrollers,
microprocessors, terminals or external peripheral
com ponents is provided by two serial interfaces: the
asynchronous / synchronous serial channel (ASC O)
and the high-speed synchronous serial channel
(SSC). Two dedicated Baud rate generators set up
all standard Baud rates without the requirement of
oscillator tuning. For transmission, reception and
erroneous reception, 3 separate interrupt vectors
are provided f or each serial channel.
14.1 - Asynchronous / Synchronous Serial
Interface (ASCO)
The asynchronous / synchronous serial interface
(ASCO) provides serial communication between
the ST10F280 and other microcontrollers,
microproces sors or external peripherals.
A set of registers is used to configure and to
con trol the ASCO serial interface:
– P 3, DP3, ODP3 for pin configuration
– SOBG for Baud rate generator
– SOTBUF for transmit buffer
– S OT IC for transmit interrupt control
– S OT B IC for transmit buffer interrupt control
– S OC ON for control
– SORBUF for rec eive buf fer (re ad only)
– S ORIC for receive interrupt control
– SOEIC for error interrupt cont rol
14.1.1 - ASCO in Asynchronous Mode
In asynchronous mode, 8 or 9-bit data transfer,
parity generation and the number of stop bit can
be selected. Parity framing and overrun error
detection is provided to increase the reliability of
data transfers . Transmission and reception of data
is double-buffered. Full-duplex communication up
to 1.25M Bauds (at 40MHz of fCPU) is supported
in this mode.
Figure 56 : Asynchron ous Mode of Serial Chann el ASC0
Pin
2
CPU
Clock
S0R
Baud Rate Tim er
Reload Register
16
Clock
Serial Port Co ntrol
Sh ift C lo ck
S0M S0STP S0FE S0OE
S0PE
S0REN
S0FEN
S0PEN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
Receive Interrupt
Request
Transmit Interrupt
Request
E rror Interrupt
Request
Transm it Shift
Register
Re c eiv e Sh ift
Register
Transmit Buffer
Register S0TBUF
Receive Buffer
Register S0RBUF
SamplingMUX
0
1
Pin
Input
Intern al Bus
RxD0/P3.11
Output
T x D0 / P 3 .10
ST10F280
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Asynch ronous Mode Baud rat es
For asynchronous operation, the Baud rate
generator provides a clock with 16 times the rate
of the establishe d Baud rate. Every received Bit is
sampled at the 7th, 8th and 9th cycle of this clock.
The Baud rate for asynchronous operation of
serial channel ASC0 and the required reload
value for a gi ven B aud rate can be deter mined by
the following formul as:
(S0BRL) represents the content of the reload
register, taken as unsigned 13 Bit integer,
(S0BRS) repr esents the value of Bit S0BRS (‘0’ or
‘1’), tak en as integer.
Using the above equation, the maximum Baud
rate can be calcul ated for any given clock speed.
Baud rate versus reload register value (SOBRS=0
and SO BRS=1) is des cr i bed in Table 24.
Note: The deviation errors given in the Table 24 are rounded. To avoid dev ia tion errors use a Baud rate
crystal (providing a multiple of the ASC0/ SSC sampling frequency).
BAsync = fCPU
16 x [2 + (S 0B RS )] x [(S0BRL) + 1]
S0BRL = ( fCPU
16 x [2 + (S0BRS)] x B Async ) 1
Table 24 : Com m only Us ed Baud Rates by Reload Value and Deviation Errors
S0BRS = ‘0’, fCPU = 40M Hz S0BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Reload Value
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
1 250 000 0.0% / 0.0% 0000 / 0000 833 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% /7.0% 000A / 000B 112 000 +6.3% /7.0% 0006 / 0007
56 000 +1.5% /3.0% 0015 / 0016 56 000 +6.3% /0.8% 000D / 000E
38 400 +1.7% /1.4% 001F / 0020 38 400 +3.3% /1.4% 0014 / 0015
19 200 +0.2% /1.4% 0040 / 0041 19 200 +0.9% /1.4% 002A / 002B
9 600 +0.2% /0.6% 0081 / 0082 9 600 +0.9% /0.2% 0055 / 0056
4 800 +0.2% /0.2% 0103 / 0104 4 800 +0.4% /0.2% 00AC / 00AD
2 400 +0.2% /0.0% 0207 / 0208 2 400 +0.1% /0.2% 015A / 015B
1 200 0.1% / 0.0% 0410 / 0411 1 200 +0.1% /0.1% 02B5 / 02B6
600 0.0% / 0.0% 0822 / 0823 600 +0.1% /0.0% 056B / 056C
300 0.0% / 0.0% 1045 / 1046 300 0.0% / 0.0% 0AD8 / 0AD9
153 0.0% / 0.0% 1FE8 / 1FE9 102 0.0% / 0.0% 1FE8 / 1FE9
ST10F280
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1 4.1. 2 - ASC O in Sy nc hron ous Mod e
In synch ronous mod e, data are transmitted or received synchronously to a shift clock which is generat ed
by the ST10F280. Hal f- duple x c ommunication up to 5M Baud (at 40MHz of fCPU) is possible in this mode.
Figure 57 : Synchr onous Mode of Serial Channel ASC0
2
CPU
Clock
S0R
Baud Rate Timer
Reload Register
4
Clock
Serial Port Con trol
Shift Clock
S0 M = 000 B S0OE
S0REN
S0OEN
S0LB
S0RIR
S0TIR
S0EIR
R eceive Interrupt
Request
Transmit Interrupt
Request
Error Inte rrupt
Request
Tran sm i t Shift
Register
Receiv e Shift
Register
Transmi t Buffer
Register S0T BU F
Receive Buffer
Registe r S0RBUF
MUX
0
1
Pin
In te r na l B u s
Receive
Output
Transmit
Pin
Input/Output
TDx0/P3.10
RxD0/P3.11
ST10F280
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Synchronous Mode Baud Rates
For synchronous operation, the Baud rate
generator provides a clock with 4 times the rat e of
the established Baud rate. The Baud rate for
synchronous operation of serial channel ASC0
can be deter m ined by the following formula:
(S0BRL) represents the content of the reload
register, taken as unsigned 13 Bit integers,
(S0BRS) repr esents the value of Bit S0BRS (‘0’ or
‘1’), tak en as integer.
Using the above equation, the maximum Baud
rate can be calculated for any clock speed as
given in Table 25.
Note: The deviation errors given in the Table 25 are rounded. To avoid dev ia tion errors use a Baud rate
crystal (providing a multiple of the ASC0/ SSC sampling frequency)
BSync =
S0BRL = ( fCPU
4 x [2 + (S0BRS )] x BSync ) 1
fCPU
4 x [2 + (S 0B RS)] x [(S0BRL) + 1]
Table 25 : Com m only Us ed Baud Rates by Reload Value and Deviation Errors
S0BRS = ‘0’, fCPU = 40M Hz S0BRS = ‘1’, fCPU = 40MHz
Baud Rate (Baud) Deviation Error Reload Value
(hexa) Baud Rate (Baud) Deviation Error Reload Value
(hexa)
5 000 000 0.0% / 0.0% 0000 / 0000 3 333 333 0.0% / 0.0% 0000 / 0000
112 000 +1.5% /0.8% 002B / 002C 112 000 +2.6% /0.8% 001C / 001D
56 000 +0.3% /0.8% 0058 / 0059 56 000 +0.9% /0.8% 003A / 003B
38 400 +0.2% /0.6% 0081 / 0082 38 400 +0.9% /0.2% 0055 / 0056
19 200 +0.2% /0.2% 0103 / 0104 19 200 +0.4% /0.2% 00AC / 00AD
9 600 +0.2% /0.0% 0207 / 0208 9 600 +0.1% /0.2% 015A / 015B
4 800 +0.1% /0.0% 0410 / 0411 4 800 +0.1% /0.1% 02B5 / 02B6
2 400 0.0% / 0.0% 0822 / 0823 2 400 +0.1% /0.0% 056B / 056C
1 200 0.0% / 0.0% 1045 / 1046 1 200 0.0% / 0.0% 0AD8 / 0AD9
900 0.0% / 0.0% 15B2 / 15B3 600 0.0% / 0.0% 15B2 / 15B3
612 0.0% / 0.0% 1FE8 / 1FE9 407 0.0% / 0.0% 1FFD / 1FFE
ST10F280
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14. 2 - H igh Sp eed Sync hr onous Serial Channel
(SSC)
The High-Speed Synchronous Serial Interface
SSC provides flexible high-speed serial
commu nication between the S T1 0F280 and ot her
microcontrollers, microprocessors or external
peripherals.
The SSC supports full-duplex and half-duplex
synchronous communication. The serial clock
signal can be generated by the SSC itself (master
mode) or be received from an external master
(slave mode). Data width, shift direction, clock
polarity and phase are programmable.
This allows communication with SPI-compatible
devices. Transmission and reception of data is
double-buffered. A 16-bit Baud rate generator
provides the SSC with a separate serial clock
signal. The serial channel SSC has its own
dedicated 16-bit Baud rate generator with 16-bit
reload capability, allowing Baud rate generation
independent from the timers.
Fi gure 5 8 : S ynchronous Seri al Channel SSC Block Diagram
Baud Rat e Gene r ato r
SSC Control
Block
Pin
Internal Bus
Clock Control
CPU
Clock
Slave Clock
Master Clock SCLK
Shift
Clock
Status Control
Recei ve I nter rupt Reque st
Transmit Interrupt Request
Error Interrupt Request
16-Bit Shift Register
Pin
Control
Pin
Pin
MTSR
MRST
Transm it Buffer
Reg is t er SSCTB Receiv e Buffe r
Register SSCRB
ST10F280
117/186
Baud Rate Generatio n
The Baud rate generat or is clocked by fCPU/2 . The
timer is counting downwards and can be started
or stopped through the global enable Bit SSCEN
in register SSCCON. Register SSCBR is the
dual-function Baud Rate Generator/Reload
register. Reading SSCBR, while the SSC is
enabled, retur ns the content of the timer. Readi ng
SSCBR, while the SSC is disabled, returns the
programmed reload value. In this mode the
des ired reload value can be written to SSCBR.
Note Never write to SSCBR, while the SSC is
enabled.
The formulas below calculate the resulting Baud
rate for a given reload value and the required
reload value for a g iven Baud rate:
(SSCBR) represents the content of the reload
register, taken as unsigned 16 Bit intege r.
Table 26 lists some possible Baud rates against
the required reload values and the resulting bit
times f o r a 40MHz CPU cloc k.
Baud rateSSC = fCPU
2 x [(SSCBR ) + 1]
SSCBR = ( fCPU
2 x B aud rateSSC ) 1
Table 26 : S y nchronous B aud Rate and Reload
Values
Baud Rate Bit Time Reload Value
Reserved use a
reload value > 0. --- ---
10M Baud 100ns 0001h
5M Baud 200ns 0003h
2.5M Baud 400ns 0007h
1M Baud 1µs 0013h
100K Baud 10µs 00C7h
10K Baud 100µs 07CFh
1K Baud 1ms 4E1Fh
306 Baud 3.26ms FF4Eh
ST10F280
118/186
15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames in accordance with the CAN specification
V2.0 par t B (active) i.e. the on-chip CAN module
can receive and transmit standard frames with
11-bit identifiers as well as extended frames with
29-bit identifiers.
Because of duplication of CAN controllers, the fol-
lowing adjustements are to be cons idered:
– T he same internal register addresses both CAN
controllers, but with the base addresses diff ering
in address bit A8 and separate chip select for
each CAN module. For address mapping, see
Chapter 4.
– The CAN1 t ransmit line (CAN1_TxD) is the alter-
nate function of the port P4.6 and the receive
line (CAN1_RxD) is P4.5.
– The CAN2 t ransmit line (CAN2_TxD) is the alter-
nate function of the port P4.7 and the receive
line (CAN 2_RxD) is the alt ernat e function of the
po r t P4.4.
– Interrupt of CAN2 is connec ted to the XBUS in-
terrupt line XP 1 (CAN1 is on XP0).
– Because of the new XPERCON register, both
CAN modules have to be selected, before the bit
XPEN is set in SYSCO N register.
– After reset, t he CAN1 is sel ected with the related
control bit in the XPERCON register. The CAN2
is not selected.
15.1 - Memory Mapping
15.1.1 - CAN1
Address range 00’EF00h 00’EFFFh is reserved
for the CAN1 Module access. The CAN1 is
enabled by setting bit 0 of the new XPERCON
register before setting XPEN bit 2 of the SYSCON
register. Ac cesses to the CAN Module use demul -
tiplexed addresses and a 16-bit data bus (byte
accesses are possible). Two waitstates give an
access time of 100 ns at 40MHz CPU clock. No
tri state waitstate is used.
15.1.2 - CAN2
Address range 00’EE00h 00’EEFFh is reserved
for the CAN2 Module access. The CAN2 is
enabled by setting XPEN bit 2 of the SYSCON
register and bit 1 of the new XPERCON register.
Accesses to the CAN Module use demultiplexed
addresses and a 16-bit data bus (byte accesses
are possible). Two waitstates give an access time
of 100 ns at 40MHz CPU clock. No tristate wait-
stat e is used.
Note: If one or the two CAN modules are used,
P ort 4 can not be prog rammed to output all
8 segment address lines. Thus, only 4
segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte per CS line).
15.2 - CAN Bus Configurations
Dependi ng on application, CA N bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F280 is able to
sup port these 2 cases.
Single CAN Bus
The single CAN Bus multiple interfaces
configuration may be implemented using 2 CAN
transce ives as shown in Figure 59.
The ST10F280 also supports single CAN Bus
multiple (dual) interfaces using the open drain
option of the CANx_TxD output as shown in Fig-
ure 60. Than ks to the OR-Wired Connection, o nly
one tr ansceiver is required. In this case the design
of the application must take in account the wire
lengt h and the noise environment.
Fi gure 5 9 : Singl e CAN Bus Multiple Interfaces -
Multip le Tran s c eive r s
Fi gure 6 0 : Si ngle CAN Bus Dual Interfaces -
Single Tra ns c e iv er
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN bus
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver
CAN_H
CAN_H CAN bu s
* O pen drain ou t put
+5V
2.7k
Ω
**
ST10F280
119/186
Multiple CAN Bus
The ST10F280 provides 2 CAN interfaces to
support the kind of bus configuration shown in
Figure 61.
15.3 - Register and Message Object
Organization
All registers and message objects of the CAN
con troller are located in the s pecial CAN address
are a of 256 bytes, which i s mapp ed into segm ent
0 and uses addresses 00’EE00h through
00’EFFFh. All registers are organized as 16 bit
registers, located on word addresses. Howe v er , all
registers may be accessed byte wise in order to
select special actions without effecting other
mechanisms.
Note The address map shown in Figure 62 lists
the registers which are part of the CAN
controller. There are also ST10F280
specific registers that are associated with
the CA N Module. These registers, however,
control the access to the CAN Module
rat her than its func tion.
Fi gure 6 2 : CA N Module Address Map
Fi gure 6 1 : Connection to Two Different CAN
Buses (e.g. for gateway application)
CAN1
RxD TxD CAN2
RxD TxD
CAN
Transceiver CAN
Transceiver
CAN_H
CAN_H CAN
CAN bus 2
bus 1
EF00h/EE00h
EF02h/EE02h
EF04h/EE04h
EF06h/EE06h
EF08h/EE08h
EF0Ch/EE0Ch
Message Object 15
Message Object 14
Message Object 13
Message Object 12
Mess age Obj ect 11
Message Object 10
Mess age Obj ect 9
Mess age Obj ect 8
Mess age Obj ect 7
Mess age Obj ect 6
Mess age Obj ect 5
Mess age Obj ect 4
Mess age Obj ect 3
Mess age Obj ect 2
Mess age Obj ect 1
General Registers
CAN Ad dress Area General Register s
EF00h
EF10h
EF20h
EF30h
EF40h
EF50h
EF60h
EF70h
EF80h
EF90h
EFA0h
EFB0h
EFC0h
EFD0h
EFE0h
EFF0h
Control / Status
Register
Interrupt
Register
Bi t Ti ming
Register
Global Mask
Short
Global Mask
Long
Mask of
Last Message
EE00h
EE10h
EE20h
EE30h
EE40h
EE50h
EE60h
EE70h
EE80h
EE90h
EEA0h
EEB0h
EEC0h
EED0h
EEE0h
EEF0h
CAN1CAN2
ST10F280
120/186
Control / Status Register (EF00h/EE00h) XReg Reset Value: XX0 1h
Table 27 : CA N Cont rol/Status Register
1514131211109876543210
BOFF EWRN -RXOK TXOK LEC TST CCE 0 0 EIE SIE IE INIT
R R RW RW RW RW RW R R RW RW RW RW
Bit Function (Control Bit)
INIT Initialization
1: Software initialization of the CAN controller. While init is set, all message transfers are stopped.
Setting init does not change the configuration registers and does not stop transmission or
reception of a message in progress. The INIT bit is also set by hardware, following a busoff
condition; the CPU then needs to reset INIT to start the bus recovery sequence.
0: Disable software initialization of the CAN controller; on INI completion, the CAN waits for 11
consecutive recessive bit before taking part in bus activities.
IE Interrupt Enable Does not affect status updates.
1: Global interrupt enable from CAN module.
0: Global interrupt disable from CAN module.
SIE Status Chan ge Interr upt Enable
1: Enables interrupt generation when a message transfer (reception or transmision is successfully
completed) or CAN bus error is detected and registered in LEC is the status partition.
0: Disable status change interrupt.
EIE Error Interrupt Enable
1: Enables interrupt generation on a change of bit BOFF or EWARN in the status partition.
0: Disable error interrupt.
CCE Configuration Change Enable
1: Allows CPU access to the bit timing register
0: Disables CPU access to the bit timing register
TST Test Mode (Bit 7)
Make sure tha t bit 7 is cleared when writing to the Control Register. Writing a 1 during normal operation
may lead erroneous device behaviour.
LEC Last Error Code
This field holds a code which indicates the type of the last error occurred on the CAN bus. If a message has
been transferred (reception or transmission) without error, this field will be cleared. Code “7” is unused and
may be written by the CPU to check for updates.
0: No Error
1: Stuff Er ror: Mor e than 5 equal bit in a sequ ence have occurre d in a pa rt of a recei ved message
where this is not allowed.
2: Form Error: A fixed format part of a received frame has the wrong format.
3: AckError: The message this CAN controller transmitted was not acknowledged by another node
4: Bit1Error: D uring the trans mission of a me ssage (with the exception of the arbitration field), the
device wanted to send a
recessive
level (“1”), but the monitored bus value was
dominant
5: Bit0Error: During the transmission of a message (or ac knowledge bit, activ e error flag, or overload
flag), the device wanted to send a
dominant
level (“0”), but the monitored bus value was
recessive
.
During
busoff
recovery this status is set each time a sequence of 11
recessive
bit has been
monitored. This enables the CPU to monitor the proceeding of the busoff recovery sequence
(indicating the bus is not stuck at
dominant
or continuously disturbed).
6: CRCError: The CRC check sum was incorrect in the message received.
ST10F280
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Note Reading the upper half of the Control
Register (status partition) will clear the
Status Change Interrupt value in the
Interrupt Register, if it is p ending. Use byt e
accesse s to the lower half to avoid this.
15.4 - CAN Interrupt Handlin g
The on-chip CAN Module has one interrupt
output, which is connected (through a
synchronization stage) to a standard interrupt
node i n the ST10 F280 in the s ame manner as al l
other interrupts of the standard on-chip
peripherals. The control register for this interrupt
is XP0IC (l ocated at address F186h/C3h for CAN1
and F18Eh/C7h for CAN2 in the ESFR range).
The associated interrupt vector is called XP0INT
at location 100h (trap number 40h) and XP1INT at
location 104h (trap number 41h). With this
configuration, the user has all control options
available for this interrupt, such as enabling/
disabling, level and group priority, and interrupt or
PEC se rvice (see note below).
As for all other interrupts , the interrupt request f lag
XP0IR/XP1IR in register XP0IC/XP1IC is cleared
automatically by hardware when this interrupt is
ser viced (either by standard interrupt or P EC ser-
vice).
Note As a rule, CAN interrupt requests can be
serviced by a PEC channel. However,
because PEC channels only can execute
single predefined data transfers (there are
no conditional PEC transfers), PEC service
can only be used, if the respective request
is known to be generated by one specific
source, and that no other interrupt request
will be generated in between. In practice
this seems to be a rare ca se.
Since an i nterrupt request of the CAN Module can
be generated due to different conditions, the
appropr iate CAN interrupt status register must be
read in the service routine to determine the cause
of the interrupt request. The Interrupt Identifier
INTID (a number) in the Interrupt Register
indicates the cause of an interrupt. When no
interrupt is pending, the identifier will have the
value 00h. If the value in INTID is not 00h, then
there is an i nterrupt pendi ng. If bit IE in the Contr ol
Register is set, also the interrupt line to the CPU i s
activated. The interrupt line remains active until
either INTI D gets 00h (after t he interrupt requester
has been serviced) or until IE i s reset (if interrupts
are dis abl ed).
The interrupt with the lowest number has the
highest prior ity. I f a higher pr ior ity interrup t (lower
number) occurs before the current interrupt is
processed, INTID is updated and the new
inte rr upt overrides the last one. The Table 28 li sts
the valid va lues for INTID and their corresponding
inter rupt sour ces.
TXOK Transmitted Message Successfully
Indicate s th at a me ssag e h as b een transm itted suc cessf ully (error free an d a cknowledge d by a t lea st o ne
other node), since this bit was last reset by the CPU (the CAN controller does not reset this bit!).
RXOK Received Message Successfully
Indicates that a message has been received successfully, since this bit was last reset by the CPU (the CAN
controller does not reset this bit!).
EWRN Er ror Warning Status
Indicates that at least one of the error counters in the EML has reached the error warning limit of 96.
BOFF Bu soff Statu s
Indicates when the CAN controller is in busoff state (see EML).
Bit Function (Control Bit)
ST10F280
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Interrupt Regi ster (EF02h/EE 02h) XReg Reset Value: - - XXh
Table 28 : INTID v alues and Corresponding Int errupt Sources
Notes 1) Bit INTPND of t he corres ponding me ssage object has to
be cleared to give messages with a lower priority the
possibility to update INTID or to reset INTID to 00h (idle
state).
2) A message interrupt code is only displayed, if there is no
other interrupt request wi th a higher prio rity.
Bit Timing Configuration
According to the CAN protocol specificat ion, a bit
time is subdivided into four segments:
Sync segment, propagation time segmen t, phase
buff er segment 1 and phase buffer segment 2.
Each segment is a m ul tiple of the tim e quantum tq
with tq = ( BRP + 1 ) x2 xt
XCLK
The Synchronization Segment (Sync seg) is
always 1 tq long. Th e Pr opaga tion Time Segm ent
and the Phase Buffer Segment1 (combined to
Tseg1) defines the time before the sample point,
while Phas e Buffer Segment2 (Tseg2) def ines the
time after the sample point. The length of these
segm ents is programmable ( except Sync-Seg).
Note For exact definition of these segments
please r efer to the C A N Specific ati on.
1514131211109876543210
RESERVED INTID
R
Bit Function
INTID Interrupt Identifier
This number indicates the cause of the interrupt. When no interrupt is pending, the value will be “00”.
INTID Cause of the Interrupt
00 Interrupt Idle: There is no interrupt request pending.
01 Status Change Interrupt: The CAN controller has updated (not necessarily changed) the status in the
Control Register. This can refer to a change of the error status of the CAN controller (EIE is set and BOFF
or EWRN change) or to a CAN transfer incident (SIE must be set), like reception or transmission of a
messag e (RXOK or TXO K is set) or the occu rrence of a CAN bus error (LEC is u pdated). Th e CPU may
clear RXOK, TXOK, and LEC, however, writing to the status partition of the Control Register can never
generate o r rese t an in terr upt. To upda te the INTID value the s tatus p artition o f the C ontro l Reg ister mu st
be read.
02 Message 15 Interrupt: Bit INTPND in the Message Control Register of message object 15 (last message)
has been set.
The last message object has the highest interrupt priority of all message objects. 1)
(2+N) Messag e N Inte rrupt: Bit INTPND in the M essage C ontrol Re gister of message object ‘N’ has bee n set
(N = 1...14). 1) 2)
Fi gure 6 3 : Bit Timing Definition
Seg TSeg1 TSeg2
1 bit time
1 time quantum sample poi nt transm it point
Sync Seg
Sync
ST10F280
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Bit Timing Register (EF04h /EE04h ) XReg Reset Value: UUUUh
Note This register can only be written, if the
configuration change enable bit (CCE) is
set.
Ma sk Re g isters
Messages can use standard or extended
identifi ers. Incoming frames are mask ed with t heir
appropriate global m asks. Bit ID E of the in co ming
mess age deter mines wh ether the s tandard 11 bit
mask in G lobal Mask S hor t or th e 29 bit extended
mask in Global Mask Long is to be used. Bit
holding a “0” mean “don’t care”, so do not
compare the message’s identifier in the respectiv e
bit position.
The last message object (15) has an additional
individually programmable acceptance mask
(Mask of Last Message) for the complete
arbitration field. This allows classes of messages
to be received in this object by masking some bits
of the iden tifier.
Note The Mask of Last Message is ANDed with
the Global Mask that corresponds to the
incoming mes sage.
Global Mas k Short (EF06h/EE 06h) XReg Reset Value: UFUUh
Upper Global Mask Lo ng (EF08h /EE08h) XReg Reset Value: UUUUh
1514131211109876543210
0TSEG2 TSEG1 SJW BRP
RRW RW RW RW
Bit Function
BRP Baud Rate Prescaler
For generating the bit time quanta the CPU frequency is divided by 2 x (BRP+1).
SJW (Re)Synchronization Jump Width
Adjust the bit time by maximum (SJW+1) time quanta for re-synchronization.
TSEG1 Time Segment before sample point
There are (TSEG1+1) time quanta before the sample point. Valid values for TSEG1 are “2...15”.
TSEG2 Time Segment after sample point
There are (TSEG2+1) time quanta after the sample point. Valid values for TSEG2 are “1...7”.
1514131211109876543210
ID20...18 11111 ID28...21
RW RRRRR RW
Bit Function
ID28...18 Identifier (11 Bit)
Mask to filter incoming messages with standard identifier.
1514131211109876543210
ID20...13 ID28...21
RW RW
ST10F280
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Low er Globa l Mask Long (EF0Ah /EE0Ah) XReg Reset Value: UUUUh
Uppe r Mask of Last Messag e (EF0Ch/E E0Ch) XReg Reset Value: UUUUh
Lower Mask of Last Message (EF0Eh/EE0Eh) XReg Reset Value: UUUUh
15.5 - The Message Object
The message object is the primary means of
communicat ion between CPU and CA N controller.
Each of the 15 message objects uses 15
cons ecutive bytes (see Figure 64) and starts at an
address that is a multiple of 16.
Note All message objects must be initialized by
the CPU , e ven those which are not going to
be used, before clearing the INIT bit.
Each e lement of the Mes sage Control Register is
made of two complemen tar y bits.
This special mechanism allows the selective
setting or resetting of specific elements (leaving
others unchanged) without requiring
read-mod ify-wr ite cy cles. None of these element s
will be aff ect ed by reset.
The Table 29 shows how to use and to interpret
these 2 bit-fields.
1514131211109876543210
ID4...0 0 0 0 ID12...5
RW R R R RW
Bit Function
ID28...0 Identifier (29 bit)
Mask to filter incoming messages with extended identifier.
1514131211109876543210
ID20...18 ID17...13 ID28...21
RW RW RW
1514131211109876543210
ID4...0 0 0 0 ID12...5
RW R R R RW
Bit Function
ID28...0 Identifier (29 bit)
Mask to filter the last incoming message (Nr. 15) with standard or extended identifier (as configured).
Fi gure 6 4 : M essage Object Address Map
Message Control
Arbitration
Message Config.
+0
+2
+4
+6
+8
+10
+12
+14
Object S tart Address
Data0
Reserved
Data1Data2
Data3Data4
Data5Data6
Data7
Table 29 : Functions of Complementary Bit of Message Control Register
Value Function on Write Meaning on Read
00 Reserved Reserved
01 Reset element Element is reset
10 Set element Element is set
11 Leave element unchanged Reserved
ST10F280
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Mess age Con trol Register (EFn0h /EEn0 h) XReg Reset Value: UUUUh
Notes 1. In message object 15 (la st m essage) these bi ts are har dwired to “0” (in active) in order to pr event transmis sion of m essage 15 .
2. When the CAN controller writes new data into the message object, unused message bytes will be overwritten by non specified
valu es. Usually t he CPU will cl ear this bit before working on the data, and ve rify that the bit i s still cl eared once it has finished workin g
to ensure th at it has worked on a consi stent set of data and not part of an old m essage and part of the new messag e.
For tran smit-objects the CPU will set this bit along with clearing bit CPUUPD. This will ensure that, if the message is actually being
transmitted during the time the message was being updated by the C PU, the C AN controller will n ot reset bit TXRQ. In this way bit
TXRQ is only reset onc e t he actual data has been trans ferred.
3. When the CPU requests the transmission of a receive -o bject, a remote frame will be sent instead of a data frame to request a
remote node to send the corresponding da ta f rame. This bit will be cleared by the CA N cont roller along w ith bit R MTP ND w he n the
message has been successfully transmitted, if bit NEWDAT has not been set. If there are se v eral valid message objects with pending
trans m i ssion request , t he m essage with the lowest me ssage number is transmitted first.
1514131211109876543210
RMTPND TXRQ MSGLST
CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND
RW RW RW RW RW RW RW RW
Bit Function
INTPND Interrupt Pending
Indicates, if this message object has generated an interr upt request (see TX IE and RXIE), since
this bit was last reset by the CPU, or not.
RXIE Receive Interrupt Enable
Defines, if bit INTPND is set after successful reception of a frame.
TXIE Transmit Interrupt Enable
Defines, if bit INTPND is set after successful transmission of a frame. 1
MSGVAL Message Valid
Indicates, if the corresponding message object is valid or not. The CAN controller only operates on
valid objects. Message objects can be tagged invalid, while they are changed, or if they are not
used at all.
NEWDAT New Data
Indicates, if new data has been written into the data portion of this message object by CPU
(transmit-objects) or CAN controller (receive-objects) since this bit was last reset, or not. 2
MSGLST
(Receive) Message Lost (This bit applies to
receive
-objects only)
Indicates tha t the CAN cont roller has stor ed a new message into this object , while N EWDAT was
still set, i.e. the previously stored message is lost.
CPUUPD
(Transmit) CPU Update (This bit applies to
transmit
-objects only)
Indicates th at the corre sponding m essage ob ject may not be tran smitted now. The CPU sets this
bit in order to inhibit the transmission of a message that is currently updated, or to control the
automatic response to remote requests.
TXRQ Transmit Request
Indicates that the transmission of this message object is requested by the CPU or via a remote
frame and is not yet done. TXRQ can be disabled by CPUUPD. 1 3
RMTPND Remote Pending (Used for transmit-objects)
Indicates that the transm ission of this message obje ct has been requested by a remo te n ode, but
the data has not yet been transm itted. Wh en RMT PND is set , the CAN con troller also sets TXR Q.
RMTPND and TXRQ are cleared, when the message object has been successfully transmitted.
ST10F280
126/186
15.6 - Arbitration Registers
The arbitration Registers are used for acceptance filtering of incoming messages and to define the
ident ifier of outgoing messages.
Up per Arbi tr at io n Re g (EFn2h/ EE n2h) XReg Reset Value: UUUUh
Lower Arbi t ra ti on R eg (E Fn 4 h/ E E n4h) XReg Reset Value: UUUUh
1514131211109876543210
ID20...18 ID17...13 ID28...21
RW RW RW
1514131211109876543210
ID4...0 0 0 0 ID12...5
RW R R R RW
Bit Function
ID28...0 Identifier (29 bit) Identifier of a standard message (ID28...18) or an extended message (ID28...0).
For standard identifiers bit ID17...0 are “don’t care”.
ST10F280
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16 - WATCHDOG TI MER
The Watchdog Timer is a fail-safe mechanism
which prevents the microcontroller from malfunc-
tion ing for long periods of time.
The Watchdog Timer is always enabled after a
reset of the chip and can only be disabled in the
time interval until the EINIT (end of initialization)
instructi on has been ex ecuted.
Therefore, the chip start-up procedure is always
monit ored. The software must be desi gned to ser-
vice the watchdog timer before it overflows. If, due
to hardware or software related failures, the soft-
ware fails to do so, the watchdog timer overflows
and gene rates an internal hardware reset. It pulls
the RSTOUT pin low in order to allow external
hardware com ponents to be reset.
Each of th e different reset sources is indicated in
the WDT CON register.
The indicated bit are cleared with the EINIT
instr uction. The or igine of the reset c an be identi-
fied during the initialization phase.
WDTCON (FFAEh / D7h) SFR Reset Value : 00xxh
Notes: 1. More tha n one reset i ndi cation flag may be set. After EINIT, al l flags are cleared.
2. Power-on is detected when a ri sing edge from Vcc = 0 V t o Vc c > 2.0 V is recogni zed.
1514131211109876543210
WDTREL - - PONR LHWR SHWR SWR WDTR WDTIN
RW RRRRRRW
WDTIN Watchdog Timer Inp ut Frequen cy Sel e ct i on
‘0’: Input Frequency is fCPU/2.
‘1’: Input Frequency is fCPU/128.
WDTR1W atchdog Timer R eset Indicati on Flag
Set by the watchdog time r on an overflow.
Cleared by a hardware reset or by the SRVW DT instruct ion.
SWR1Software Reset Indication Flag
Set by the SRS T e x ecution.
Cleared by the EINIT instruct ion.
SHWR1Short Har d ware Reset Indication F la g
Set by the input RSTIN.
Cleared by the EINIT instruct ion.
LHWR1Long Hardw are Reset Indi cation Flag
Set by the input RSTIN.
Cleared by the EINIT instruct ion.
PONR1- 2 Power-On (Asynchronous) Reset Indication Flag
Set by the input RSTIN if a power-on condition has been detected.
Cleared by the EINIT instruct ion.
ST10F280
128/186
The PONR flag of WDTCON register is set i f the output voltage of the internal 3.3V supply falls below the
threshol d (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of
the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not
set. This could be the case on fast switch-off / switch-on of the 5V supply. The time need ed for such a
seq uence to activate the PO NR flag depends on the value of the capac itors connect ed to the supply and
on the exact value of the internal thresho ld of the detection circuit.
Notes: 1. PONR bit may not be set f or short supply failure.
2. For power-on reset and re set after suppl y partial failu re, async hronous reset must be used.
In case of bi -directional rese t is enabled, and i f the RSTIN pin is latched low after the end of the inter nal
reset sequence, then a Short hardware reset, a software reset or a watchdog reset will trigger a Long
hardware reset. Thus, Reset Indications flags will be se t to indicate a Long Hardware Reset.
The Watchdog Timer is 16 -bit, clocked with the system clock divided by 2 or 1 28. The high Byte of the
watchdog timer register can be set to a pre-specified reload value (stored in W DTREL).
Each t ime it is ser viced by the application software, t he high byt e of the watchdog timer is reloaded. For
secur ity, rewrite WDTCON each time before t he watchdog timer is ser viced
The Table 31 shows the watchdog time range fo r 40MHz CPU clock.
The watchdog time r period is calculat ed with the fol lowing for mula:
Table 30 : WDTCON Bits Value on Differen t Resets
Reset Source PONR LHWR SHWR SWR WDTR
Power On Reset X X X X
Power on after partial supply failure 1 X X X
Long Hardware Reset X X X
Shor t Hardwar e Reset X X
Software Reset X
Watchdog Reset XX
Table 31 : WDT R EL Reload Value
Reload value in WDTREL Prescaler for fCPU = 40MHz
2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)
FFh 12.8µs 819.2ms
00h 3.276ms 209.7ms
PWDT 1
fCPU
--------------- 512×1WDTIN]63)256 WDTREL])[–(××[+(×=
ST10F280
129/186
UNDER UPDATING
17 - SYSTEM RESET
System reset initializes the MCU in a predefined
state. There are five wa ys to activate a res et s tate .
The system start-up configuration is different for
eac h case as shown in Table 32.
17.1 - A synchronous Reset (Long H ardware Reset)
An asynchronous reset is triggered when RSTIN pin
is pulled low while RPD pin is at low level. Then the
MCU is immediately forced in reset default state. It
pulls low RSTOUT pin, it cancels pending internal
hold states if any, it waits for any internal access
cycles to finish, it aborts external bus cycle, it
switches buses (data, address and control signals)
and I/O pin drivers to high-impedance, it pulls high
PORT0 pins and the reset sequence starts.
Pow er-on reset
The asynchronous reset must be used during the
power-on of the MCU. Depending on crystal fre-
quency, the on-chip oscillator needs about 10ms to
50ms to stabilize. The logic of the MCU does not
need a stabilized clock signal to detect an asyn-
c hro nous r eset, so it i s sui table for power-on c o ndi-
tions. To ensure a proper reset sequence, the
RSTIN
pin and the RPD pin must be held at low
level u ntil th e MCU clo c k s ignal is sta bilized and t he
sys t em configura tion v alue on PORT0 is sett led.
Hardware reset
The asynchronous reset must be used to recover
from catastrophic situations of the application. It
may be t ri ggerred by the hardware of the applica-
tion. Internal hardware logic and application cir-
cuitry are described in Reset ci rcuitry chapter and
Figures Figure 68 :, Figure 69 : and Figure 70 :.
Exit of asyn chro nous reset state
When the RSTIN pin is pulled high, the MCU
restarts. The system configuration is latched from
PORT0 and ALE, RD and R/W p ins are d riven to
their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
asynchron ous reset sequence are s ummarized in
Figure 65.
Note: 1. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL) .
Table 32 : Reset Event Definition
Reset Source Short-cut Conditions
Power-on reset PONR Power-on
Long Hardware reset (synchronous & asynchronous) LHWR t RSTIN > 1032 TCL
Short Hardware reset (synchronous reset) SHWR 4 TCL < t RSTIN < 1032 TCL
Watchdog Timer reset WDTR WDT overflow
Software reset SWR SRST execution
Fi gure 6 5 : As ync hronou s Reset Timing
6 TCL or 8 TCL1
CPU Clock
RSTIN
Asynchronous
Reset Condition
RPD
RSTOUT
ALE
PORT0 Reset Configuration INST #1
Internal
Reset
Signal
Latching point of PORT 0
for system st art -up
configuration
130/186
ST10F280
UNDER UPDATING
17.2 - Synchro no us Reset (Wa rm Reset)
A synchronous reset is triggered when
RSTIN
pin
is pulled low while RPD pin is at high level. In
order to properly activate the internal reset logic of
the MCU , the
RSTIN
pin must be held lo w , at least ,
during 4 TCL (2 periods of CPU clock). The I/O
pins are set to high impedance and
RSTOUT
pin is
driven low. After
RSTIN
level is detected, a short
duration of 12 TCL (approximately 6 periods of
CPU clock) elapes, during which pen ding interna l
hold states are cancelled and the current internal
access cycle if any is completed. External bus
cycle is ab orted. The inte r nal pull-down of
RSTIN
pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. This bit is
always cleared on power-on or after a reset
sequence.
Exit of synchronous reset state
The internal reset sequence starts for 1024 TCL
(512 peri ods of C PU clock) and
RSTIN
pin leve l is
sampled. The reset sequence is extended until
RSTIN
level becomes high. Then, the MCU
restarts. The system configuration is latched from
PORT0 and ALE, RD and
R/W
pins are driven to
their inactive level. The MCU starts program
execution from memory location 00'0000h in code
segment 0. This starting location will typically
point to the general initialization routine. Timing of
synchronous reset sequence are summarized in
Figure 66 and Figure 67.
Notes: 1. RSTIN assertion can be released there.
2. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the
asynchronous reset is then immediately entered.
3. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(fCPU =f
XTAL / 2) , e lse it is 4 CPU cl ock cy cles (8 T CL).
4) RSTIN pin is pulled low if bit BDRSTEN (b it 5 of SYSCON register) was previously set by software. Bit BDRSTEN is clear ed after
re set.
Fi gure 6 6 : Sy nchronous Warm Reset (Short low pulse on
RSTIN)
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0 INST #1
Internal
Reset
Signal
Lat ching point of POR T 0
for system start-up con figuration
6 or 8 TCL
3
4 TCL 12 TCL
min. max. 1024 TCL
1
Internally pu lled low
4
Reset Confi guration
V
RPD
> 2.5V Asynchronous Reset not entered.
200
µ
A Discharge
2
ST10F280
131/186
UNDER UPDATING
Fi gure 6 7 : Synchronous Warm Reset (Long low pulse on
RSTIN)
Notes: 1. RSTIN r ising edge to in ternal latch of PORT 0 is 3 CPU
(6 TCL) clock cycles if the PLL is bypassed and the
prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock
cycl e s (8 TCL) .
2. If during the res et cond ition (RSTIN low), VRPD voltage
drops below the threshold voltage (about 2.5V for 5V
operation), the asynchronous reset is then immediately
entered.
3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of
SYSCON register) was previously set by soft-ware. Bit
BDRSTEN is cleared after reset.
17.3 - Software Reset
The reset sequence can be trigg ered at any time
using the protected instruction SRST (software
reset). This instruction can be executed
deliber ately within a program, for e xample to lea ve
bootstrap loader mode, or upon a hardware trap
that reveals a sy stem f ailure.
Upon execution of the SRST instruction, the
internal reset sequence (1024 TCL) is started.
The microcont roller behavi our is the same as for a
Short Hardware reset, except that only
P0.12.. .P0.6 bit are latched at the end of the reset
seq uence, while P0.5...P0.2 bit are cleared.
17.4 - Watchdog Timer Reset
When the watchdog timer is not disabled during
the initialization or when it i s not regul arly s erviced
during progr am e xecuti on it will ov erflow and it will
trigger the reset sequence.
Unlike hardware and software resets, the
watchdog reset completes a ru nning ex ternal bus
cycle if this bu s cycle either does not use READY,
or if READY is sampled active (low) after the
programmed wait states. When READY is
sampled inactiv e (high) after t he programmed wai t
states the running external bus cycle is aborted.
Then the internal reset sequence is started. At the
end of the internal reset sequence (1024 TCL),
only P 0.12...P0.6 bi t are latched, while previously
latched v al ues of P0.5...P0.2 are cleared.
17 .5 - RSTOU T Pin and Bidirectional R eset
The RST OUT pin is driven activ e (low level) at the
beginning of any reset sequence (synchronous/
asynchronous hardware, software and watchdog
timer resets). RSTOUT pin stays active low
beyond the end of the initialization routine, until
the protected EINIT instruction (End of
Initializ a ti on ) is c omplet ed.
The Bidirectional Reset function is useful when
external d evi ces require a reset s ignal but cannot
be connec ted to RSTOUT pin, because RSTOUT
signal last s dur ing initialisation. It is, for instance,
the case of external memor y running initialization
routine before t he execution of EI NIT instruction.
Bidirectional reset function is enabled by setting
bit 3 (B DRSTEN) in S YSCO N register. It only can
be enabled dur ing the initialization rout ine, before
EINIT i nstruction i s completed.
CPU Clock
RSTIN
RPD
RSTOUT
ALE
PORT0
Internal
Reset
Signal
Latching point of PORT0
for syste m start-u p configuratio n
6 or 8 TCL
1
4 TCL 12 TCL 1024 TCL
In t e rn ally pull ed low
3
Reset Configu ration
2
V
RPD
> 2.5V Asyn chronous Res et not entered.
200
µ
A Discharge
132/186
ST10F280
UNDER UPDATING
When enabled, the open dr ain of the RSTIN pin is
activated, pulling down the reset signal, for the
duration of the internal reset sequence
(synchronous/asynchronous hardware, software
and watchdog timer resets). At the end of the
intern al reset sequ ence the p ull down is released
and the RSTIN pin is sampled 8 TCL periods later .
– If signal is sampled low, a hardware res et is tri g-
gered again.
– If it is sampled high, the chip exits reset state ac-
cording to the running reset way (synchronous/
asynchronous hardware, software and watch-
dog timer resets ).
Note: The bidirectional reset function is disabled
by any reset sequence (Bit BDRSTEN of
SYSCON i s cle ared). To be a ctivated again i t mu st
be enab l ed duri ng the ini tialization routine.
17.6 - Reset Ci rcuitry
The internal reset circuitry is described in Figure
68.
An internal pull-up resistor is implemented on
RSTIN pin. (50kΩ minimum , to 250kΩ ma x imum).
The minimum reset time must be calculat ed using
the lowest value. In addition, a programmable
pull-down (bit BDRSTEN of SYSCON register)
drives the RSTIN pin according to the internal
reset state as explained in Section 17.5 -
RSTO UT Pin and Bidirecti onal Reset.
The RSTOUT pin provides a signals to the
application as described in Section 17.5 -
RSTO UT Pin and Bidirecti onal Reset.
A weak internal pull-down is connected to the
RPD pin to discharge ext ernal capacitor to Vss at
a rate of 100µA to 200µA. This Pull-down is
tur ned on when RSTIN pin is low
If bit PWDCFG of SYSCON register is set, an
internal pull-up resistor is activated at the end of
the reset sequence. This pull-up charges the
capac itor connected to RPD pin.
If Bidirectional Reset function is not used, the
simplest way to reset ST10F280 is to connect
external components as shown in Figure 69. It
works with reset from application (hardware or
manual) and with power-on. The value of C1
capacitor, connected on RSTIN pin with internal
pull-up resistor (50kΩ to 250kΩ), must lead to a
charging time long enough to let the internal or
external oscillator and / or the on-chip PLL to
stabilize.
The R0-C0 components on RPD pin are mainly
imp lemente d to provide a time delay to exit Power
down mode (see Chapter 18 - Power Reduction
Modes). Nervertheless, they drive RPD pin level
during resets and they lead to different reset
mode s as explained hereafter. On powe r-o n, C0
is totaly discharged, a low l evel on RPD pin forces
an asynchronous hardware reset. C0 capacitor
starts to charge throught R0 and at the end of
reset sequence ST10F280 restarts. RPD pin
threshol d is typically 2.5V.
Dependi ng on the delay of the next applied reset,
the MCU can enter a synchronous reset or an
asynchron ous reset. If RPD pin is below 2 .5V an
asynchronous reset starts, if RPD pin is above
2.5V a synchronous reset starts. (see Section
17.1 - Asynchronous Reset (Long Hardware
Reset) and Section 17.2 - Synchronous Reset
(Warm Reset)).
Note that an internal pull-down is connected to
RPD pin and can drive a 100µA to 200µA current.
This Pull-down is turned on when RSTIN pin is
low.
In order to properly use the Bidirectional reset
features, the schematic (or equivalent) of Figure
70 must be implemented. R1-C1 only work for
power-on or manual reset in the same way as
explained previously. D1 diode brings a faster
discharge of C1 capacitor at power-off during
repetitive switch-on / switch-off sequences. D2
diode performs an OR-wired connect i on, it can be
replaced with an open drain buffer. R2 resistor
may be added to increase the pull-up current to
the op en drain in o rder to ge t a faster rise time on
RSTIN pi n when bi directional f unction is acti vated.
The start-up configurations and some system
features are selected on reset sequences as
desc ribed in Table 33 and Table 34.
Table 33 describes what is the system
configuration latched on PORT0 in the five
different reset ways. Table 34 summ arizes the bit
state of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers. RPOH register is described
in Section 19.2 - Sys tem Configuration Registers.
ST10F280
133/186
UNDER UPDATING
Fi gure 6 8 : Int ernal (simplified) Reset Circuitry.
RSTOUT
EINIT Instruction
Trigger
Clr
Clock
Reset State
Machine
Internal
Reset
Signal
Reset Sequence
(512 C PU C lock Cycles )
SRST instruction
watchdog overflow RSTIN
V
CC
BDRSTEN
V
CC
RPD
Weak pull-dow n
(~200
µ
A)
From /to E xit
Powerdown
Circuit
Asynchronous
Reset
Clr Q
Set
Fi gure 6 9 : Minimum External Reset Circuitry
ST10F280
External
Hardware
RSTOUT
+
RSTIN
a) Ma nu al Ha rdw a re R es et
C1
b) For A utomatic Pow er-u p R es et an d interrup tible po w er-do w n m o de
VDD
R0
RPD
+
C0
134/186
ST10F280
UNDER UPDATING
Table 33 : P ORT0 Latched Configuration for the Diffe r ent Resets
Notes: 1. N ot latch ed from PORT0.
2. Onl y RP0H low byte is used and t he bi t-fields are l at ched from PORT 0 h i gh byt e t o RP0H low byt e.
3. In di rectly depend on PORT0.
4. Bits set if EA pin is 1.
Fi gure 7 0 : Exter nal Reset Hardware Circuitry
X : Pin is sampled
- : Pin is not sampled
PORT0
Clock Options
Segm. Addr. Lines
Chip Sele cts
WR config.
Bus Type
Reserved
BSL
Reserved
Reserved
Adapt Mod e
Em u Mode
Sample event
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0H.0
P0L.7
P0L.6
P0L.5
P0L.4
P0L.3
P0L.2
P0L.1
P0L.0
Software Reset - - - XXXXXXX------
Watchdog Reset - - - XXXXXXX------
Shor t Hardwar e Reset - - - XXXXXXXXXXXXX
Long Hardware Reset XXXXXXXXXXXXXXXX
Power-On Reset XXXXXXXXXXXXXXXX
Table 34 : P ORT0 bit latched into t he different registers after reset
POR T0 b it
nber h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0
PORT0 bit
Name CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU
RP0H
2X
1X
1X
1X
1X
1X
1X
1X
1CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
SYSCON X
1X
1X
1X
1X
1X
1BYTDIS
3X
1WRCFG
3X
1X
1X
1X
1X
1X
1X
1
BUSCON0 X
1X
1X
1X
1-BUS
ACT0
4ALE
CTL0
4- BTYP BTYP X
1X
1X
1X
1X
1X
1
Internal Logic To Clock Gener ator To Por t 4 Logic To Por t 6 Logic X 1X 1X 1X 1Internal X 1X 1Internal Internal
ST10F280
External
Hardware
RSTOUT
+
RSTIN
V
DD
C1
D2 R1
D1
V
DD
R2
Open Drain Inverter
External
Reset Sou rce
V
DD
R0
RPD
+
C0
ST10F280
135/186
18 - POWER REDUCTION MODES
Two different power reduction modes with differ-
ent levels of power reduction have been imple-
mented in the ST10F280, which may be entered
under software control.
In Idle mode the CPU is stopped, while the
peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt
request.
In Power Down mode both the CPU and the
peripherals are stopped. Power Down mode can
now be configured by software in order to be ter-
minated only by a hardware reset or by a transi-
tion on enabled fast ex t er nal interrupt pins.
Note: All external bus actions are completed
before Idle or Power Down mode is
entered. However, Idle or Power Down
mode i s not entered if REA DY is enabled,
but has not been activated (driven low for
negative polarity, or driven high for positive
polarit y) during the last bus access .
18.1 - Idle Mode
Idle mode is entered by running IDLE protected
instruct ion. The CPU operation is st opped and the
peripherals still run.
Idle mode is terminate by any interrupt request.
Whatever the interrupt is serviced or not, the
instruction following the IDLE instruction will be
executed after return from interrupt (RETI)
instruction, then the CPU resumes the normal
program.
Note that a PEC transfer keep the CPU in Idle
mode. If the PEC transfer does not succeed, the
Idle m ode is ter minated. Watchdog tim er must be
properly programmed to avoid any disturbance
during Idle mode.
18.2 - Power Down Mode
Power Down mode starts by running PWRDN
pro tected i nstr uc tion. In ter nal clock is sto pped, al l
MCU parts are on hold including the watchdog
timer.
There are two different operating Power Down
modes : protected mode and interruptible mode.
The internal RAM contents can be preserved
through the voltage supplied via the VDD pins. To
verify RAM integrity, some dedicated patterns
may be written before entering the Power Down
mode and have to be checked after Power Down
is resumed.
It is mandatory t o keep VDD = +5 V ± 10 % du ri ng
power-down mode, because the on-chip
voltage regulator is turned in power saving
mod e and it delivers 2.5V to the core log ic, but
it must be supplied at nominal VDD = +5V.
SYSCON (FF12h / 89h) SF R Reset Value : 0xx0h
Note: Register SYSCO N cann ot be changed after execution of the EINIT instr uction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ ROM
S1 SGT
DIS ROM
EN BYT
DIS CLK
EN WR
CFG CS
CFG PWD-
CFG OWD-
DIS BDR
STEN XPEN VISI
BLE XPER-
SHARE
RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
PWDCFG 0
1
Power Down Mode Configuration Control
P ower Down Mode can only be entered during PWRDN instruction execution if NMI pin is low , oth-
erwise t he i nstr uctio n h as n o e ffect. To exit Powe r Down Mo de, an exter nal reset must occ urs by
asserting the RSTIN pin.
Power Down Mode can only be entered during PWRDN instruction execution if all ena bled Fas-
tExternal Interrupt (EXxIN) pins are in their inactive level. Exiting this mode can be done by
asserting one enabled EXxIN pin.
ST10F280
136/186
18.2.1 - Protected Powe r Down Mode
This mode is selected by clearing the bit PWD-
CFG in register SYSCON to ‘0’.
In this m ode, the Power Down m ode can only be
entered if the NMI (Non Maskable Interru pt) pin is
e xternally pulled low whil e the PWRDN instruction
is executed .
This feature can be used in conjunction with an
external power failure signal which pulls the NMI
pin low when a power failure is imminent. The
microcontroller will enter the NMI trap routine
which can save the internal state into RAM. After
the internal state has been saved, the trap routine
may set a flag or write a certain bit pattern into
specific RAM locations, and then execute the
PWRDN instruction. If the NMI pin is still low at
this time, Power Down mode will be entered, oth-
erwise program execution continues. During
power down the voltage delivered by the on-chip
voltage regulator autom atic ally lowers the inter nal
logic supply down to 2.5 V, sa ving the power while
the contents of the internal RAM and al l registers
wi ll s til l b e p re se rve d.
Exiting Power Down Mode
In this mode, the only way to exit Power Down
mode is with an external hardware reset .
The initialization routine (executed upon reset)
can check the identification flag or bit pattern
within RAM to determine whether the controller
was initially switched on, or whether it was prop-
erly res tarted from Power Down mode.
18.2.2 - Interruptable Power Down Mode
This mode is selected by setting the bit bit PWD-
CFG in register SYSCON to ‘1’.
In this mode, the Power Down mode can be
entered if enabled Fast External Interrupt pins
(EXxIN pins, alternate functions of Port 2 pins,
with x = 7...0) are in their inactive level. This inac-
tive level is configured with the EX IxES b it field in
the EXICON register, as follow:
EXICON (F1C0h / E0h) ESFR Reset Value: 0000h
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
Bit Function
EXIxES
(x=7...0) 00
01
10
11
External Interrupt x Edge Selection Field (x=7...0)
Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
ST10F280
137/186
Exiting Power Down Mode
When Power Down mode i s ent ered, t he CPU and
peripheral clocks are frozen, and the oscillator
and PLL are stopped. Power Down mode can be
exited by either asserting RSTIN or one of the
enabled EXxIN pin (Fast Exter nal Interr upt).
RSTIN must be held low until the oscillator and
PLL have stabilized.
EXxIN inputs are normally sampled interrupt
inputs. However, the Power Down mode circuitry
uses them as lev el-sensitive inputs. An EXx IN (x =
7...0) Interru pt Ena ble bit (bit CCxIE in respective
CCxIC register) need not to be set to bring the
device out of Power Down mode. An exte rnal RC
circuit must be connect ed, as shown in the follow-
i n g figu r e :
To exit Power Down mode with exter nal interrupt,
an EXx IN pin has to be asserted for at least 40 ns
(x = 7...0). This signal enables the inter nal oscilla-
tor and PLL circuitry, and also turns on the weak
pull-down (see following figure). The discharging
of the external capacitor provides a delay that
allows the oscillator and PLL circuits to stabilize
before the internal CPU and Peripheral clocks are
enabled. When the Vpp voltage drops below the
threshold voltage (about 2.5 V), the Schmitt trig-
ger clears Q2 flip-flop, thus enabling the CPU and
Peripheral clocks, and the device resumes code
execution.
If the Interrupt was enabled (bit CCxIE=’1’ in the
respective CCxIC register) before entering Power
Down mode, the device e x ecutes the in terrupt ser-
vice routine, and then resumes ex ecut ion after the
PWRDN intruction (see note below). If the inter-
rupt was disabled, the device executes the
instruction following PWRDN instruction, and the
Interrupt Request Flag (bit CCxIR in the respec-
tive CCxIC register) remains set until it is cleared
by software .
Note: Due to i nt ernal pipeline, the instruction that
follows the PWRDN intruction is executed
before the CPU performs a call of the
interrupt service routine when exiting
power-down mode.
Fi gure 7 1 : External RC Circuit on RPD Pin for Exiting
Powerdown Mode with External Interrupt
RPD
VDD
C0
R0
220kΩ 1MΩ Typical
1µF Typical
ST10F280
+
Fi gure 7 2 : Si mpl ified Powerdow n Ex it Circuitr y
DQ
Q
V
DD
Enter cd
External
interrupt
reset
St op pl l
stop oscillator
VDD
DQ
Q
cd Syste m clock
CP U an d Periph erals clocks
RPD
VDD Pull-u p
Weak Pu ll-down
(~ 200µA)
PowerDown
Q1
Q2
ST10F280
138/186
Fi gure 7 3 : Powerdown Exit Sequence when Using an External Interrupt (PLL x 2)
CPU clk
internal
External
RPD
ExitPwrd
XTAL1
Interrupt
(internal)
~ 2.5 V
delay for oscillato r/pll
stabilization
signal
Powerdown
ST10F280
139/186
19 - SPECIAL FUNCTION REGISTER OVERVIEW
The following table lists all SFRs which are
implemented in the ST10F280 in alphabetical
order. Bit-addressable SFRs are marked with the
letter “b” in column “Name”. SFRs within the
Extended SFR-Space (ESFRs) are marked with
the letter “E” in column “Physical Address”.
An SFR can be specified by its individual
mnemonic name. Depending on the selected
addressing mode, an S FR can be accessed via its
physical address (using the Data Page Pointers),
or via its short 8-bit address (without using the
Data Page Pointers).
The reset value is defined as following:
X : Means the full nibb le is not defined at reset.
x : Means some bit of the nibb le are not def ined
at reset.
Table 35 : Special Function Registers Listed b y Name
Name Physical
address 8-bit
address Description Reset
value
ADCIC b FF98h CCh A/D Converter end of Conversion Interrupt Control Register - - 00h
ADCON b FFA0h D0h A/D Converter Control Register 0000h
ADDAT FEA0h 50h A/D Converter Result Register 0000h
ADDAT2 F0A0h E 50h A/D Converter 2 Result Register 0000h
ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h
ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h
ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h
ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h
ADEIC b FF9Ah CDh A/D Converter Overrun Error Interrupt Control Register - - 00h
BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0xx0h
BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h
BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h
BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h
BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h
CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h
CC0 FE80h 40h CAPCOM Register 0 0000h
CC0IC b FF78h BCh CAPCOM Register 0 Interrupt Control Register - - 00h
CC1 FE82h 41h CAPCOM Register 1 0000h
CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register - - 00h
CC2 FE84h 42h CAPCOM Register 2 0000h
CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register - - 00h
CC3 FE86h 43h CAPCOM Register 3 0000h
CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register - - 00h
CC4 FE88h 44h CAPCOM Register 4 0000h
CC4IC b FF80h C0h CAPCOM Register 4 Interrupt Control Register - - 00h
CC5 FE8Ah 45h CAPCOM Register 5 0000h
CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register - - 00h
CC6 FE8Ch 46h CAPCOM Register 6 0000h
ST10F280
140/186
CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control Register - - 00h
CC7 FE8Eh 47h CAPCOM Register 7 0000h
CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control Register - - 00h
CC8 FE90h 48h CAPCOM Register 8 0000h
CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register - - 00h
CC9 FE92h 49h CAPCOM Register 9 0000h
CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register - - 00h
CC10 FE94h 4Ah CAPCOM Register 10 0000h
CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register - - 00h
CC11 FE96h 4Bh CAPCOM Register 11 0000h
CC11IC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h
CC12 FE98h 4Ch CAPCOM Register 12 0000h
CC12IC b FF90h C8h CAPCOM Register 12 Interrupt Control Register - - 00h
CC13 FE9Ah 4Dh CAPCOM Register 13 0000h
CC13IC b FF92h C9h CAPCOM Register 13 Interrupt Control Register - - 00h
CC14 FE9Ch 4Eh CAPCOM Register 14 0000h
CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control Register - - 00h
CC15 FE9Eh 4Fh CAPCOM Register 15 0000h
CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control Register - - 00h
CC16 FE60h 30h CAPCOM Register 16 0000h
CC16IC b F160h E B0h CAPCOM Register 16 Interrupt Control Register - - 00h
CC17 FE62h 31h CAPCOM Register 17 0000h
CC17IC b F162h E B1h CAPCOM Register 17 Interrupt Control Register - - 00h
CC18 FE64h 32h CAPCOM Register 18 0000h
CC18IC b F164h E B2h CAPCOM Register 18 Interrupt Control Register - - 00h
CC19 FE66h 33h CAPCOM Register 19 0000h
CC19IC b F166h E B3h CAPCOM Register 19 Interrupt Control Register - - 00h
CC20 FE68h 34h CAPCOM Register 20 0000h
CC20IC b F168h E B4h CAPCOM Register 20 Interrupt Control Register - - 00h
CC21 FE6Ah 35h CAPCOM Register 21 0000h
CC21IC b F16Ah E B5h CAPCOM Register 21 Interrupt Control Register - - 00h
CC22 FE6Ch 36h CAPCOM Register 22 0000h
CC22IC b F16Ch E B6h CAPCOM Register 22 Interrupt Control Register - - 00h
CC23 FE6Eh 37h CAPCOM Register 23 0000h
CC23IC b F16Eh E B7h CAPCOM Register 23 Interrupt Control Register - - 00h
CC24 FE70h 38h CAPCOM Register 24 0000h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F280
141/186
CC24IC b F170h E B8h CAPCOM Register 24 Interrupt Control Register - - 00h
CC25 FE72h 39h CAPCOM Register 25 0000h
CC25IC b F172h E B9h CAPCOM Register 25 Interrupt Control Register - - 00h
CC26 FE74h 3Ah CAPCOM Register 26 0000h
CC26IC b F174h E BAh CAPCOM Register 26 Interrupt Control Register - - 00h
CC27 FE76h 3Bh CAPCOM Register 27 0000h
CC27IC b F176h E BBh CAPCOM Register 27 Interrupt Control Register - - 00h
CC28 FE78h 3Ch CAPCOM Register 28 0000h
CC28IC b F178h E BCh CAPCOM Register 28 Interrupt Control Register - - 00h
CC29 FE7Ah 3Dh CAPCOM Register 29 0000h
CC29IC b F184h E C2h CAPCOM Register 29 Interrupt Control Register - - 00h
CC30 FE7Ch 3Eh CAPCOM Register 30 0000h
CC30IC b F18Ch E C6h CAPCOM Register 30 Interrupt Control Register - - 00h
CC31 FE7Eh 3Fh CAPCOM Register 31 0000h
CC31IC b F194h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h
CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h
CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h
CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h
CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h
CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h
CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h
CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h
CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h
CP FE10h 08h CPU Context Pointer Register FC00h
CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register - - 00h
CSP FE08h 04h CPU Code Segment Pointer Register (read only) 0000h
DP0L b F100h E 80h P0L Direction Control Register - - 00h
DP0H b F102h E 81h P0h Direction Control Register - - 00h
DP1L b F104h E 82h P1L Direction Control Register - - 00h
DP1H b F106h E 83h P1h Direction Control Register - - 00h
DP2 b FFC2h E1h Port 2 Direction Control Register 0000h
DP3 b FFC6h E3h Port 3 Direction Control Register 0000h
DP4 b FFCAh E5h Port 4 Direction Control Register - - 00h
DP6 b FFCEh E7h Port 6 Direction Control Register - - 00h
DP7 b FFD2h E9h Port 7 Direction Control Register - - 00h
DP8 b FFD6h EBh Port 8 Direction Control Register - - 00h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F280
142/186
DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10-bit) 0000h
DPP1 FE02h 01h CPU Data Page Pointer 1 Register (10-bit) 0001h
DPP2 FE04h 02h CPU Data Page Pointer 2 Register (10-bit) 0002h
DPP3 FE06h 03h CPU Data Page Pointer 3 Register (10-bit) 0003h
EXICON b F1C0h E E0h External Interrupt Control Register 0000h
EXISEL b F1DAh E EDh External Interrupt Source Selection Register 0000h
IDCHIP F07Ch E 3Eh Device Identifier Register (n is the device revision) 118nh
IDMANUF F07Eh E 3Fh Manufacturer Identifier Register 0401h
IDMEM F07Ah E 3Dh On-chip Memory Identifier Register 3080h
IDPROG F078h E 3Ch Programming Voltage Identifier Register 0040h
IDX0 b FF08h 84h MAC Unit Address Pointer 0 0000h
IDX1 b FF0Ah 85h MAC Unit Address Pointer 1 0000h
MAH FE5Eh 2Fh MAC Unit Accumulator - High Word 0000h
MAL FE5Ch 2Eh MAC Unit Accumulator - Low Word 0000h
MCW b FFDCh EEh MAC Unit Control Word 0000h
MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h
MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h
MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h
MRW b FFDAh EDh MAC Unit Repeat Word 0000h
MSW b FFDEh EFh MAC Unit Status Word 0200h
ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h
ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h
ODP4 b F1CAh E E5h Port 4 Open Drain Control Register - - 00h
ODP6 b F1CEh E E7h Port 6 Open Drain Control Register - - 00h
ODP7 b F1D2h E E9h Port 7 Open Drain Control Register - - 00h
ODP8 b F1D6h E EBh Port 8 Open Drain Control Register - - 00h
ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh
P0L b FF00h 80h PORT0 Low Register (Lower half of PORT0) - - 00h
P0H b FF02h 81h PORT0 High Register (Upper half of PORT0) - - 00h
P1L b FF04h 82h PORT1 Low Register (Lower half of PORT1) - - 00h
P1H b FF06h 83h PORT1 High Register (Upper half of PORT1) - - 00h
P2 b FFC0h E0h Port 2 Register 0000h
P3 b FFC4h E2h Port 3 Register 0000h
P4 b FFC8h E4h Port 4 Register (8-bit) - - 00h
P5 b FFA2h D1h Port 5 Register (read only) XXXXh
P6 b FFCCh E6h Port 6 Register (8-bit) - - 00h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
ST10F280
143/186
P7 b FFD0h E8h Port 7 Register (8-bit) - - 00h
P8 b FFD4h EAh Port 8 Register (8-bit) - - 00h
P5DIDIS b FFA4h D2h Port 5 Digital Disable Register 0000h
POCON0L F080h E 40h PORT0 Low Outpout Control Register (8-bit) - - 00h
POCON0H F082h E 41h PORT0 High Output Control Register (8-bit) - - 00h
POCON1L F084h E 42h PORT1 Low Output Control Register (8-bit) - - 00h
POCON1H F086h E 43h PORT1 High Output Control Register (8-bit) - - 00h
POCON2 F088h E 44h Port2 Output Control Register 0000h
POCON3 F08Ah E 45h Port3 Output Control Register 0000h
POCON4 F08Ch E 46h Port4 Output Control Register (8-bit) - - 00h
POCON6 F08Eh E 47h Port6 Output Control Register (8-bit) - - 00h
POCON7 F090h E 48h Port7 Output Control Register (8-bit) - - 00h
POCON8 F092h E 49h Port8 Output Control Register (8-bit) - - 00h
POCON20 F0AAh E 55h ALE, RD, WR Output Control Register (8-bit) - - 00h
PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h
PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h
PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h
PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h
PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h
PECC5 FECAh 65h PEC Channel 5 Control Register 0000h
PECC6 FECCh 66h PEC Channel 6 Control Register 0000h
PECC7 FECEh 67h PEC Channel 7 Control Register 0000h
PICON b F1C4h E E2h Port Input Threshold Control Register - - 00h
PP0 F038h E 1Ch PWM Module Period Register 0 0000h
PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h
PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h
PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h
PSW b FF10h 88h CPU Program Status Word 0000h
PT0 F030h E 18h PWM Module Up/Down Counter 0 0000h
PT1 F032h E 19h PWM Module Up/Down Counter 1 0000h
PT2 F034h E 1Ah PWM Module Up/Down Counter 2 0000h
PT3 F036h E 1Bh PWM Module Up/Down Counter 3 0000h
PW0 FE30h 18h PWM Module Pulse Width Register 0 0000h
PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h
PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h
PW3 FE36h 1Bh PWM Module Pulse Width Register 3 0000h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
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PWMCON0 b FF30h 98h PWM Module Control Register 0 0000h
PWMCON1 b FF32h 99h PWM Module Control Register 1 0000h
PWMIC b F17Eh E BFh PWM Module Interrupt Control Register - - 00h
QR0 F004h E 02h MAC Unit Offset Register QR0 0000h
QR1 F006h E 03h MAC Unit Offset Register QR1 0000h
QX0 F000h E 00h MAC Unit Offset Register QX0 0000h
QX1 F002h E 01h MAC Unit Offset Register QX1 0000h
RP0H b F108h E 84h System Start-up Configuration Register (read only) - - XXh
S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h
S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h
S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register - - 00h
S0RBUF FEB2h 59h Serial Channel 0 Receive Buffer Register (read only) - - XXh
S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register - - 00h
S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register - - 00h
S0TBUF FEB0h 58h Serial Channel 0 Transmit Buffer Register (write only) 0000h
S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register - - 00h
SP FE12h 09h CPU System Stack Pointer Register FC00h
SSCBR F0B4h E 5Ah SSC Baud Rate Register 0000h
SSCCON b FFB2h D9h SSC Control Register 0000h
SSCEIC b FF76h BBh SSC Error Interrupt Control Register - - 00h
SSCRB F0B2h E 59h SSC Receive Buffer (read only) XXXXh
SSCRIC b FF74h BAh SSC Receive Interrupt Control Register - - 00h
SSCTB F0B0h E 58h SSC Transmit Buffer (write only) 0000h
SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register - - 00h
STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h
STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h
SYSCON b FF12h 89h CPU System Configuration Register 0xx0h 1)
T0 FE50h 28h CAPCOM Timer 0 Register 0000h
T01CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h
T0IC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h
T0REL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h
T1 FE52h 29h CAPCOM Timer 1 Register 0000h
T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h
T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h
T2 FE40h 20h GPT1 Timer 2 Register 0000h
T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
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Notes: 1. T he system configuration i s s el ected during reset.
2. Bit WDTR indicates a watchdog timer tr ig gered reset.
3. The XPnIC Interrupt Control Registers control interrupt requests from integrated X-Bus peripherals. Some software controlled
interrupt requests may be ge nerated by s etting t he X PnIR bit s (of XPnI C regi ster) of the unus ed X-peripheral node s.
T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register - - 00h
T3 FE42h 21h GPT1 Timer 3 Register 0000h
T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h
T3IC b FF62h B1h GPT1 Timer 3 Interrupt Control Register - - 00h
T4 FE44h 22h GPT1 Timer 4 Register 0000h
T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h
T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register - - 00h
T5 FE46h 23h GPT2 Timer 5 Register 0000h
T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h
T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register - - 00h
T6 FE48h 24h GPT2 Timer 6 Register 0000h
T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h
T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register - - 00h
T7 F050h E 28h CAPCOM Timer 7 Register 0000h
T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h
T7IC b F17Ah E BEh CAPCOM Timer 7 Interrupt Control Register - - 00h
T7REL F054h E 2Ah CAPCOM Timer 7 Reload Register 0000h
T8 F052h E 29h CAPCOM Timer 8 Register 0000h
T8IC b F17Ch E BFh CAPCOM Timer 8 Interrupt Control Register - - 00h
T8REL F056h E 2Bh CAPCOM Timer 8 Reload Register 0000h
TFR b FFACh D6h Trap Flag Register 0000h
WDT FEAEh 57h Watchdog Timer Register (read only) 0000h
WDTCON b FFAEh D7h Watchdog Timer Control Register 00xxh 2)
XP0IC b F186h E C3h CAN1 Module Interrupt Control Register - - 00h 3)
XP1IC b F18Eh E C7h CAN2 Module Interrupt Control Register - - 00h 3)
XP2IC b F196h E CBh XPWM Interrupt Control Register - - 00h 3)
XP3IC b F19Eh E CFh PLL unlock Interrupt Control Register - - 00h 3)
XPERCON F024h E 12h XPER Configuration Register - - 05h
ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h
Table 35 : S pec ial Function Registers Listed by Name (continued)
Name Physical
address 8-bit
address Description Reset
value
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Table 36 : X Registers Li sted by Nam e
Name Physical
address Description Reset value
CAN1BTR EF04h CAN1 Bit Timing Register XXXXh
CAN1CSR EF00h CAN1 Control/Status Register XX01h
CAN1GMS EF06h CAN1 Global Mask Short XFXXh
CAN1IR EF02h CAN1 Interrupt Register - - XXh
CAN1LAR1--15 EF14--EFF4h CAN1 Lower Arbitration register 1 to 15 XXXXh
CAN1LGML EF0Ah CAN1 Lower Global Mask Long XXXXh
CAN1LMLM EF0Eh CAN1 Lower Mask Last Message XXXXh
CAN1MCR1--15 EF10--EFF0h CAN1 Message Control Register 1 to 15 XXXXh
CAN1MO1--15 EF1x--EFFxh CAN1 Message Object 1 to 15 XXXXh
CAN1UAR1--15 EF12--EFF2h CAN1 Upper Arbitration Register 1 to 15 XXXXh
CAN1UGML EF08h CAN1 Upper Global Mask Long XXXXh
CAN1UMLM EF0Ch CAN1 Upper Mask Last Message XXXXh
CAN2BTR EE04h CAN2 Bit Timing Register XXXXh
CAN2CSR EE00h CAN2 Control/Status Register XX01h
CAN2GMS EE06h CAN2 Global Mask Short XFXXh
CAN2IR EE02h CAN2 Interrupt Register - - XXh
CAN2LAR1--15 EE14--EEF4h CAN2 Lower Arbitration register 1 to 15 XXXXh
CAN2LGML EE0Ah CAN2 Lower Global Mask Long XXXXh
CAN2LMLM EE0Eh CAN2 Lower Mask Last Message XXXXh
CAN2MCR1--15 EE10--EEF0h CAN2 Message Control Register 1 to 15 XXXXh
CAN2MO1--15 EE1x--EEFxh CAN2 Message Object 1 to 15 XXXXh
CAN2UAR1--15 EE12--EEF2h CAN2 Upper Arbitration Register 1 to 15 XXXXh
CAN2UGML EE08h CAN2 Upper Global Mask Long XXXXh
CAN2UMLM EE0Ch CAN2 Upper Mask Last Message XXXXh
XADCMUX C384h Port5 or PortX10 ADC Input Selection (Read / Write) 0000h
XDP9 C200h Direction Register Xport9 (Read / Write) 0000h
XDP9CLR C204h Bit Clear Direction Register Xport9 (Write only) 0000h
XDP9SET C202h Bit Set Direction Register Xport9 (Write only) 0000h
XODP9 C300H Open Drain Control Register Xport9 (Read / Write) 0000h
XODP9CLR C304H Bit clear Open drain Control register Xport9 (Write only) 0000h
XODP9SET C302H Bit Set Open Drain Control Register Xport9 (Write only) 0000h
XP10 C380h Read only Data register Xport10 (Read only) 0000h
XP10DIDIS C382h Xport10 Schmitt Trigger Input Selection (Read / Write) 0000h
XP9 C100h Data Register Xport9 (Read / Write) 0000h
XP9CLR C104h Bit Clear Data Register Xport9 (Write only) 0000h
XP9SET C102h Bit Set Data Register Xport9 (Write only) 0000h
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XPOLAR EC04h XPWM Channel Polarity Control Register 0000h
XPP0 EC20h XPWM Period Register 0 0000h
XPP1 EC22h XPWM Period Register 1 0000h
XPP2 EC24H XPWM Period Register 2 0000h
XPP3 EC26h XPWM Period Register 3 0000h
XPT0 EC10h XPWM Timer Counter Register 0 0000h
XPT1 EC12h XPWM Timer Counter Register 1 0000h
XPT2 EC14h XPWM Timer Counter Register 2 0000h
XPT3 EC16h XPWM Timer Counter Register 3 0000h
XPW0 EC30h XPWM Pulse Width Register 0 0000h
XPW1 EC32h XPWM Pulse Width Register 1 0000h
XPW2 EC34h XPWM Pulse Width Register 2 0000h
XPW3 EC36h XPWM Pulse Width Register 3 0000h
XPWMCON0 EC00h XPWM Control Register 0 0000h
XPWMCON1 EC02h XPWM Control Register 1 0000h
XTCR C000h Xtimer Control Register (Read / Write) 0000h
XTCVR C006h Xtimer Current Value Register (Read / Write) 0000h
XTEVR C004h Xtimer End Value Register (Read / Write) 0000h
XTSVR C002h Xtimer Start Value Register (Read / Write) 0000h
Name Physical
address Description Reset value
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19.1 - Identification Registers
The S T10F 280 has four Identification regist ers, mapped in ESFR space. These register contain:
– A ma nufacturer identifier,
– A chip identifier, with its revision,
– A internal memory and size identifier and programmin g voltage description.
IDMANUF (F07Eh / 3Fh ) 1ESFR Reset Value: 040 1h
IDCHIP (F07Ch / 3Eh) 1ESFR Reset Value: 118Xh
IDME M (F07Ah / 3Dh) 1ESF R Reset Value: 308 0h
IDPROG (F078h / 3Ch) 1ESF R Res et Value: 004 0h
Note : 1. All i dentifi cation words are read only registers.
1514131211109876543210
MANUF 00001
R
MANUF Manufacturer Identifier 020h: STMicroelectronics Manufacturer (JTAG worldwide normalisation).
1514131211109876543210
CHIPID REVID
RR
REVID Device Revision I dentifier
CHIPID Devi ce Identifier 118h: ST10F280 identifier.
15 14131211109876543210
MEMTYP MEMSIZE
RR
MEMSIZE Internal M emory Size is calculated using t he foll owing formula:
Size = 4 x [MEM SIZE] (in K Byte) 080h for ST10F280 (512K Byte)
MEMTYP Internal Memory Type 3h for ST10F280 (Fla sh memory).
1514131211109876543210
PROGVPP PROGVDD
RR
PROGVDD Programming VDD Voltage
VDD vol tage when programming EPROM or FLASH dev ices is calculated using the
followi ng formula: VDD = 20 x [PROGVDD] / 256 (volts) 40h for ST10F280 (5V).
PROGVPP Program ming VPP Voltage (n o need of external V PP) 00h
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19.2 - System Configuration Registers
The ST10F280 has registers used for different configuration of the overall system. These registers are
desc ribed belo w.
SYSCON (FF12h / 89h) SF R Reset Value: 0xx0h
Notes: 1. Thes e bi t are set di rectly or in di rectly according to P O RT 0 and EA pin co nfiguration duri ng re set sequence.
2. R egister SYSCON cannot b e changed a fter execution of the EINIT instruction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG PWD
CFG OWD
DIS BDR
STEN XPEN VISIBLE XPER-
SHARE
RW RW RW RW1RW1RW RW1RW RW RW RW RW RW RW
XPER-SHARE XBUS Peripheral Share Mode Control
‘0’: External accesses to XBUS peripherals are disabled
‘1’: XBUS peripherals are accessible via the external bus during hold mode
VISIBLE Vis ible Mode Control
‘0’: Accesses to XBUS peripherals are done internally
‘1’: XBUS peripheral accesses are made visible on the external pins
XPEN XBUS Peripheral Enable bit
‘0’: Accesses to the on-chip X-Peripherals and XRAM are disabled
‘1’: The on-chip X-Peripherals are enabled.
BDRSTEN Bidirectional Reset Enable
‘0’: RSTIN pin is an input pin only. (SW Reset or WDT Reset have no effect on this pin)
‘1’: RSTIN pin is a bidirectional pin. This pin is pulled low during 1024 TCL during reset sequence.
OWDDIS Oscillator Watchdog Disable Control
‘0’: Oscillator Watchdog (OWD) is enabled. If PLL is bypassed, the OWD monitors XTAL1 activity. If
there is no activity on XTAL1 for at least 1 µs, the CPU clock is switched automatically to PLL’s
base frequency (2 to 10MHz).
‘1’: OWD is disabled. If the PLL is bypassed, the CPU clock is always driven by XTAL1 signal. The
PLL is turned off to reduce power supply current.
PWDCFG Power Down Mode Configuration Control
‘0’: Power Down Mode can only be entered during PWRDN instruction execution if NMI pin is low,
otherwise the instruction has no effect. Exit power down only with reset.
‘1’: Power Down Mode can only be entered during PWRDN instruction execution if all enabled fast
external interrupt EXxIN pins are in their inactive level. Exiting this mode can be done by asserting
one enabled EXxIN pin or with external reset.
CSCFG Chip Select Configuration Control
‘0’: Latched Chip Select lines: CSx change 1 TCL after rising edge of ALE
‘1’: Unlatched Chip Select lines: CSx change with rising edge of ALE.
WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H)
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR acts as WRL, pin BHE acts as WRH.
CLKEN System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
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Table 37 : Stack Size Selection
BU SCON 0 (FF0Ch / 86h) SF R Reset Value: 0xx0h
BU SCON1 (FF14h / 8Ah ) SFR Reset Value: 0000h
BU SCON2 (FF16h / 8Bh ) SFR Reset Value: 0000h
BU SCON3 (FF18h / 8Ch ) SFR Reset Value: 0000h
BYTDIS Disable/Enable Control for Pin BHE (Set according to data bus width)
‘0’: Pin BHE enabled
‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
ROMEN Internal Memory Enable (Set according to pin EA during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1 Internal Flash Memory Mapping
‘0’: Internal Flash Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Flash Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
<STKSZ> Stack Size
(Words) Internal RAM Addresses (Words) of Physical Stack Significant Bits of
Stack Pointer SP
0 0 0 b 256 00’FBFEh...00’FA00h (Default after Reset) SP.8...SP.0
0 0 1 b 128 00’FBFEh...00’FB00h SP.7...SP.0
0 1 0 b 64 00’FBFEh...00’FB80h SP.6...SP.0
0 1 1 b 32 00’FBFEh...00’FBC0h SP.5...SP.0
1 0 0 b 512 00’FBFEh...00’F800h (not for 1K Byte IRAM) SP.9...SP.0
1 0 1 b - Reserved. Do not use this combination -
1 1 0 b - Reserved. Do not use this combination -
1 1 1 b 1024 00’FDFEh...00’FX00h (Note: No circular stack)
00’FX00h represents the lower IRAM limit, i.e.
1K Byte: 00’FA00h, 2K Byte: 00’F600h, 3K Byte: 00’F200h
SP.11...SP.0
15 14 13 12 11 10 9 876 5 4 3210
CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BU S ACT0 ALE CT L 0 -BTYP MTTC0 RWDC0 MCTC
RW RW RW RW RW2RW2RW1RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC
RW RW RW RW RW RW RW RW RW RW
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BU SCON4 (FF1Ah / 8Dh) SFR Reset Value: 0000h
Notes: 1. BTYP (b it 6 and 7) are set according to the configuration of the bi t l1 and l2 of PORT 0 latched at the end of t he reset sequence.
2. BUSC ON0 is i niti alize d with 000 0h, if EA pi n is hi gh du ring reset. If EA pin is low duri ng reset , bit BUSACT0 and ALECTR L0 are
set ( ’1 ’ ) and bit fiel d BTY P is load ed wi th the bus c onf i guration selected via P O RT0.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 - BTYP MTTC4 RWDC4 MCTC
RW RW RW RW RW RW RW RW RW RW
MCTC Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 [MCTC])
. . .
1 1 1 1: No wait states
RWDCx Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
MTTCx Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
BTYP External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALECTLx ALE Lengthenin g Control
‘0’: Normal ALE signa l
‘1’: Lengthened ALE signal
BUSACTx Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see ADDRSEL)
RDYENx READY Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY input signal
RDYPOLx Ready Active Level Control
‘0’: Active level on the READY pin is low, bus cycle terminates with a ‘0’ on READY pin,
‘1’: Active level on the READY pin is high, bus cycle terminates with a ‘1’ on READY pin.
CSRENx Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD)
‘1’: The CS signal is generated for the duration of the read command
CSWENx Write Chip Select Enable
‘0’: The CS signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS signal is generated for the duration of the write command
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RP0H (F108h / 84h) ESFR Reset Value: - - XXH
Notes: 1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pin s during
re set, RP0H default valu e i s "F F h".
2. These bits are set according to Por t 0 c onf iguration during any res et sequence.
EXICON (F1C0h / E0h ) ESFR Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- CLKSEL SALSEL CSSEL WRC
R 1 - 2 R 2R 2R2
WRC 2Write Configuration Control
‘0’: Pin WR acts as WRL, pin B HE acts as WRH
‘1’: Pins WR and BHE retain their normal function
CSSEL 2Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS lines at all
1 1: 5 CS lines: CS4...CS0 (Default without pull-downs)
SALSEL 2Segment Address Line Selection (Number of active segment address outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 8-bit segment address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
CLKSEL 1 - 2 Sys tem Clock Selection
000: fCPU = 2.5 x fOSC
001: fCPU = 0.5 x fOSC
010: fCPU = 10 x fOSC
011: fCPU = fOSC
100: fCPU = 5 x fOSC
101: fCPU = 2 x fOSC
110: fCPU = 3 x fOSC
111: fCPU = 4 x fOSC
1514131211109876543210
EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES
RW RW RW RW RW RW RW RW
EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0)
0 0: Fast external interrupts disabled: standard mode
EXxIN pin not taken in account for entering/exiting Power Down mode.
0 1: Interrupt on positive edge (rising)
Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level)
1 0: Interrupt on negative edge (falling)
Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level)
1 1: Interrupt on any edge (rising or falling)
Always enter Power Down mode, exit if EXxIN level changed.
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EXISEL (F1D Ah / EDh) ESFR Reset Value: 0000h
XP3IC (F19Eh / CFh) 1ESFR Reset Value: - - 00h
Note: 1. XP3 IC register has the same bit field as xxIC interrupt registers
xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h
1514131211109876543210
EXI7SS EXI6SS EXI5SS EXI4SS EXI3SS EXI2SS EXI1SS EXI0SS
RW RW RW RW RW RW RW RW
EXIxSS External Interrupt x Source Selection (x=7...0)
‘00’: Input from associated Port 2 pin.
‘01’: Input from “alternate source”.
‘10’: Input from Port 2 pin ORed with “alternate source”.
‘11’: Input from Port 2 pin ANDed with “alternate source”.
EXIxSS Port 2 pin Alternate Source
0 P2.8 CAN1_RxD
1 P2.9 CAN2_RxD
2...7 P2.10...15 Not used (zero)
1514131211109876543210
--------
XP3IR XP3IE XP3ILVL GLVL
RW RW RW RW
1514131211109876543210
--------xxIR xxIE ILVL GLVL
RW RW RW RW
Bit Function
GLVL Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
ILVL Interrupt Priority Level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
xxIE Interrupt Enable Control Bit (individually enables/disables a specific source)
‘0’: Interrupt Request is disabled
‘1’: Interrupt Request is enabled
xxIR Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
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XPERCON (F02 4h / 12h ) ESFR Reset Value: - - 05h
Note: - When both CAN and XPWM are disab l ed via XPERCON setting, then any access in the address
range 00’EC00h 00’EFFFh will be directed to external memory interface, using the BUSCONx
register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as
General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General
Pur pos e I/O when CAN1 is not enabled.
- The default XPER selection after Reset is : XCAN1 is enabled, XCAN2 is disabled, XRAM is
enabled, XPORT9, XTIMER, XPO RT10, XPWM are disabled.
- Regi st er XPE RCON cannot be changed af ter the global enabling of XPeripherals, i.e. after
setting of bit X PEN in SYSCON register.
15141312111098765 4 3 2 1 0
-----------XPWMENXPERCONEN3XRAMENCAN2ENCAN1EN
RW RW RW RW RW
Bit Function
CAN1EN 0
1
CAN1 Enable Bit
Accesses to the on -chip CAN 1 X Periph eral a nd its f unctio ns are disabled . P4 .5 a nd P4.6 pin s
can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed t o
external memory if CAN2EN and XPWM bits are cleared also.
The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN 0
1
CAN2 Enable Bit
Accesses to the on -chip CAN 2 X Periph eral a nd its f unctio ns are disabled . P4 .4 a nd P4.7 pin s
can be used a s general pur pose I/O s. Address range 00 ’EE00h-00 ’EEFFh is only d irected t o
external memory if CAN1EN and XPWM bits are cleared also.
The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAMEN 0
1
XRAM Enable Bit
Accesses to the on-chip 16K Byte XRAM are disabled, external access performed.
The on-chip 16K Byte XRAM is enabled and can be accessed.
XPERCONEN3 0
1
XPORT9,XTIMER, XPORT10, XADCMUX Enable Bit
Accesses to the XPO RT9, XT IMER, XPORT10, XA DCMUX per ipherals are disa bled , externa l
access performed.
The on-chip XPORT9, XTIMER, XPORT10, XADCMUX peripherals are enabled and can be
accessed.
XPWMEN 0
1
XPWM Enable Bit
Accesses to the on-chip XPWM are disabled, external access performed. Address range
00’EC00h-00’ECFFh is only directed to external memory if CAN1EN and CAN2EN are ‘0’ also
The on-chip XPWM is enabled and can be accessed.
ST10F280
155/186
20 - ELECTRICAL CHARACTERISTICS
20.1 - Absolute Maximu m Ratings
Not e: 1. Stre sses above th ose listed under “Absolut e Max imum Ratings” may cause per mane nt damage to the devic e. This is a stre ss
rating o nl y and func t i onal operation of the device at t hese or any oth er conditio ns above those indicated i n the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods ma y af fect devi ce reliability.
During overload co ndition s (V
IN
> V
DD
or V
IN
< V
SS
) t he voltag e on p ins w ith r espe ct to grou nd (V
SS
) must not exceed t he valu es
defined by the Absolu te M aximum Ratings.
2 0.2 - Param e ter In te rpretation
The parameters listed in the following tables represent the characteristics of the ST10F280 and its
demands on the system. Where the ST10F280 logic provides signals with their respective timing
cha racteristics, the symbol “CC” for Controller Characteristics, is i nc luded in the “S ym bol” colum n.
Where the external system must provide signals with their respective timing characteristics to the
ST 10F2 80, the symbol “SR” fo r System Requirement , is included in the “Symbol” column.
20.3 - DC Characteristics
VDD = 5V ± 10%, VSS = 0V, f CPU = 40MHz, Reset active, TA = -40 to +125°C
Symbol Parameter Value Unit
VDD Voltage on VDD pins with respect to ground1-0.5, +6.5 V
VIO Voltage on any pin with respect to ground1-0.5, (VDD +0.5) V
VAREF Voltage on VAREF pin with respect to ground1-0.3, (VDD +0.3) V
IOV Input Current on any pin during overload condition1-10, +10 mA
ITOV Absolute Sum of all input currents during overload condition1|100 mA| mA
Ptot Power Dissipation11.5 W
TAAmbient Temperature under bias -40, +125 °C
Tstg Storage Temperature1-65, +150 °C
Symbol Parameter Test
Conditions Min. Max. Unit
VIL SR Input low voltage – -0.5 0.2 VDD - 0.1 V
VILS SR Input low voltage (special threshold) – -0.5 2.0 V
VIH SR Input high voltage
(all except RSTIN and XTAL1) –0.2 VDD +
0.9 VDD + 0.5 V
VIH1 SR Input high voltage RSTIN – 0.6 VDD VDD + 0.5 V
VIH2 SR Input high voltage XTAL1 – 0.7 VDD VDD + 0.5 V
VIHS SR Input high voltage (special threshold) – 0.8 VDD - 0.2 VDD + 0.5 V
HYS Input Hysteresis (special threshold) 3– 400 – mV
VOL CC Output low voltage (PORT0, PORT1, Port 4,
ALE, RD, WR , BHE, CLKOUT, RSTOUT) 1IOL = 2.4mA – 0.45 V
VOL1 CC Output low voltage (all other outputs) 1IOL1 = 1.6mA – 0.45 V
ST10F280
156/186
Notes: 1. ST10F280 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These
low -noise drivers deli ver their m aximum current only until the res pective tar get output level is reached. Af ter th i s, the outpu t cu rrent
is r educed. T hi s results in in crease d i mpedance of the driver, which attenuates el ectric al noise from the c onnected PCB t racks. The
current sp ecifie d i n colu m n “T est Conditions” is del i vered in any cases.
2. This specification is not valid for o utputs whic h are switched to op en dr ain mod e. In t his c ase the r espective o utput will float and the
vol tage res ul ts from the ext ernal cir cuitry.
3. Par t i al l y tes ted, gua ranteed by design characte ri zation.
4. Overload conditions o ccur if the s tanda rd ope rating conditions are exceeded, i.e. the v oltage on any pin ex ceeds the sp ecified
range (i.e. VOV > VDD+0.5V or VOV <0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The
supply voltage must remain within the specified limits.
VOH CC Output high voltage (PORT0, PORT1, Port4,
ALE, RD, WR , BHE, CLKOUT, RSTOUT) 1IOH = -500µA
IOH = -2.4mA 0.9 VDD
2.4 –
–V
VOH1 CC Output high voltage (all other outputs) 1/2 IOH = – 250µA
IOH = – 1.6mA 0.9 VDD
2.4 –
–V
V
IOZ1
CC Input leakage current (Port 5, XPort 10) 0V < VIN < VDD – 0.2 µA
IOZ2
CC Input leakage current (all other) 0V < VIN < VDD –1µA
I
OV
SR Overload current 3/4 –5mA
R
RST CC RSTIN pull-up resistor 3–50 250 kΩ
IRWH Read / Write inactive current 5/6 VOUT = 2.4V – -40 µA
IRWL Read / Write active current 5/7 VOUT = VOLmax -500 – µA
IALEL ALE inactive current 5/6 VOUT = VOLmax 40 – µA
IALEH ALE active current 5/7 VOUT = 2.4V – 500 µA
IP6H Port 6 inactive current 5/6 VOUT = 2.4V – -40 µA
IP6L Port 6 active current 5/7 VOUT = VOL1max -500 – µA
IP0H PORT0 configuration current
5/6 VIN = VIHmin – -10 µA
IP0L 5/7 VIN = VILmax -100 – µA
IIL
CC XTAL1 input current 0V < VIN < VDD –20µA
C
IO CC Pin capacitance (digital inputs / outputs) 3/5 f = 1MHz, TA
= 25°C –10pF
I
CC Power supply current 8RSTIN = VIH1
fCPU in [MHz] –
30 + 3.3 x f
CPU
mA
IID Idle mode supply current 9RSTIN = VIH1
fCPU in [MHz] –20 + fCPU mA
IPD Power-down mode supply current 10 VDD = 5.5V
TA = 55°C – 200 µA
Symbol Parameter Test
Conditions Min. Max. Unit
ST10F280
157/186
5. This s pecification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are us ed f or
CS output and i f their op en drain function i s not enabled.
6. The max i m um curr ent may be drawn while the respectiv e signal li ne remains ina ct i ve.
7. The mini m um cur rent must be drawn i n order to dr i ve the respecti ve signal l i ne active.
8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These
parameters are tested at VDDmax and 40MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is
configured wi th a d em ul tiple xed 16-bit bus, di rect cl ock d ri ve, 5 chip select l i nes and 2 segm ent address lines, EA pin is low du ri ng
re set. Af te r reset, PORT 0 i s driven with the value ‘ 00CCh’ t hat produces i nfin ite execution of NOP ins truction with 15 wait-state , R/
W de lay, memory tristate wait state, n ormal ALE. Peripherals are not activa ted.
9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 74. These
param eters are tes ted at VDDmax and 40MHz CPU cloc k with al l out puts disc onnect ed and all i nputs at VIL or VIH.
10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at
VDD – 0.1V to VDD, VREF = 0V, all outputs (i ncluding pins configured as outputs) di sconnec ted.
Fi gure 7 4 : S upply / I dle Current as a Function of Operating Frequency
0
0
00
0
0
000
0
0
0000
00
0
000
0
0
000
0
00
000
0
0
0000
0
0
000
0
0
000
0
0
0000
00
0
000
0
0
000
0
00
000
0
0
0000
0
0
000
0
0
000
0
0
0000
00
0
000
0
0
000
0
00
000
0
0
0000
0
0
000
0
0
000
0
0
0000
0
0
0000
0
0
000
0
0
000
0
0
0000
00
0
000
0
0
00
0
0
00
0
0
000
0
00
000
0
0
0000
0
0
0000
00
0
000
0
0
000
0
0
000
0
0
000
0
00
000
0
0
0000
0
0
0000
00
0
000
0
0
000
0
0
000
0
0
000
0
0
000
0
00
000
0
0
0000
0
0
0000
00
0
000
0
0
000
0
0
000
0
0
000
0
0
000
0
00
000
0
0
0000
0
0
0000
00
0
000
0
0
000
0
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I [m A]
fCPU [MH z ]
10
20
300
10
ICCtyp
IIDmax
ICCmax
IIDtyp
40
30
70mA
162mA
ST10F280
158/186
20.3.1 - A/D Conver ter Cha racteristi cs
V
DD
= 5V ± 10%, V
SS
= 0V
,
T
A
= -40 t o +125°C , 4 .0V
≤
V
AREF
≤
V
DD
+ 0.1V ; V
SS
0.1V
≤
V
AGND
≤
V
SS
+ 0.2V
Notes: 1. V
AIN
may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectiv ely.
2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of
the analog source mu st al l ow t h e capacitance to reach its f i nal voltage l evel wit hi n the tS sample time. After the end of the tS sample
time, changes of the a nalog inp ut voltage have no effect on the c onversio n resu lt. Value s for th e t SC samp le clock dep end on the
program ming. Referring to t he tC conversion t ime formula of section 20.3.2 and to the table 39 of page 156:
- tS mi n = 2 tSC m in = 2 tCC min = 2 x 24 x TCL = 48 TCL
- tS max = 2 tSC max = 2 x 8 tCC m ax = 2 x 8 x 96 TCL = 1536 T CL
TCL is define d i n section 20.4.5 at page 159.
3. The conversion time formula is:
- tC = 14 tCC + tS + 4 T CL (= 14 tCC + 2 tSC + 4 TCL)
The tC p arameter includes the t S sample time, the t i me for determining the digital result and the t i m e to load the result regist er wi th
the result of the conversi on. Values for the tCC conversion clock depend on the programming. Ref erring to the table 39 of page 156:
- tC mi n = 14 tCC min + t S mi n + 4 T CL = 14 x 24 x TC L + 48 T CL + 4 TCL = 388 TCL
- tC max = 14 tCC max + tS m ax + 4 TCL = 14 x 96 TCL + 1536 T CL + 4 TCL = 2884 T CL
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at VAREF=5.0V,
V
AGND =0V, V
CC = 4.9V. It is guaranteed by design characterization for all other
voltages within th e define d voltage range.
‘LSB’ has a value of VAREF / 1024.
The specified TUE is guaranteed only if an overload condition (see
I
OV specification) occurs on maximum 2 not selec ted analog input
pins and the abs ol ute sum of input over l oad currents o n al l analog input pins does not exceed 10mA .
6. Th e coup lin g factor is measur ed on a c ha nnel whil e an over lo ad c ond itio n oc curs on the a djacen t not sel ect ed c han nel with an
absol ute overload cur rent less than 10mA.
7. Par t i al l y tes ted, gua ranteed by design ch aracterizat i on.
8.To remove noi se and undesirable high frequency components f rom the analo g i nput signal, a low-p ass filt er m ust be conne ct ed at
the A DC i npu t. T he cut-off frequ ency of this fil ter shou l d avoi d 2 opposite transi tions during the ts samp l i ng time of the ST10 A DC:
- fcut-off
≤
1 / 5 ts
to 1/10 t
s
where ts is the sampl i ng tim e of the ST 10 ADC an d i s not related to the Nyquist frequenc y determi ned by the tc conversion time.
Table 38 : A/ D Converter Characteristics
Symbol Parameter Test Condition Limit Values Unit
minimum maximum
VAREF SR Analog Reference voltage 4.0 VDD + 0.1 V
VAIN SR Analog input voltage 1 - 8 VAGND VAREF V
IAREF CC Reference supp ly current
running mode
power-down mode
7–
–500
1µA
µA
CAIN CC ADC input capacitanc e
Not sampling
Sampling
7–
–10
15 pF
pF
tSCC Sample time 2 - 4 48 TCL 1 536 TCL
tCCC Conversion time 3 - 4 388 TCL 2 884 TCL
DNL CC Differential Nonlinearity 5-0.5 +0.5 LSB
INL CC Integral Nonlinearity 5-1.5 +1.5 LSB
OFS CC Offset Error 5-1.0 +1.0 LSB
TUE CC Total unadjusted error 5-2.0 +2.0 LSB
RASRC SR Internal resistance of analog source tS in [ns] 2 - 7 –(t
S
/ 150) - 0.25 kΩ
K CC Coupling Factor between inputs 6 - 7 – 1/500
ST10F280
159/186
20.3.2 - Co nv ersion Timing Con trol
When a conversion is started, first the
capacitances of the converter are loaded via the
respective analog input pin to the current analog
input v oltage. The time to load the capacitances is
referred to as the sample time ts. Next the
sample d voltage is conver ted to a digital value in
10 successive steps, which correspond to the
10-bit resolution of the ADC. The next 4 steps are
used for equalizing internal levels (and are keep
for exact timing matching with the 10-bit A/D
conv erter modul e implemented in ST10F168).
The current that has to be drawn from the sources
for sampling and changing charges depends on
the tim e that eac h respect ive step takes, bec ause
the capacitors must reach their final voltage level
within the given time, at least with a certain
approximation. The maximum current, however,
that a so urce can deliver, depends on its interna l
resistance.
The sample time tS (= 2 tSC) and the conversion
time tC (= 14 tCC + 2 tSC + 4 TCL) can be
programmed relatively to the ST10F280 CPU
clock. This allows adjusting the A/D converter of
the ST10F 280 to the properties of the system :
Fast Conversion can be achieved by
programming the respective times to their
absolute possible minimum. This is pre ferable for
scanning high frequency signals. The internal
resistance of analog source and analog supply
must be sufficiently low, however.
High Internal Resistance can be achieved by
programming the respective times to a higher
value , or the possib l e maximum. This is preferab le
when usi ng anal og sour ces and s upply with a high
intern al resistance in order to keep the c urrent as
low as possible. However, the conversion rate in
this case may be considerably lower.
The conversion times are programmed via the
upper four bit of regist er ADCON. Bit field ADCTC
(conversion time control) selects the basic
conversion clock tCC, used for the 14 steps of
conv erting. The sample time t S is a multiple of this
conversion time and is selected by bit field
ADSTC (sample time control). The table below
lists the possible combinations. The timings refer
to the unit TCL, where fCPU = 1/2 TCL.
A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fas test convertion rate = 4.85µs at 40MHz). This
time includes the conversion itself, the sample time and the time req uired to transfer the digital value to
the result register.
Table 39 : A DC Sa mpling and Convers ion Timing
ADCTC
Conversion Clock tCC
ADSTC
Sample Clock tSC
TCL = 1/2 x fXTAL At fCPU = 40MHz tSC = At fCPU = 40MHz
and ADCTC = 00
00 TCL x 24 0.3µs00 t
CC 0.3µs
01 Reserved, do not use Reserved 01 tCC x 2 0.6µs
10 TCL x 96 1.2 µs10t
CC x 4 1.2µs
11 TCL x 48 0.6 µs11t
CC x 8 2.4µs
ST10F280
160/186
20.4 - AC characteristics
20.4.1 - Test W aveforms
20.4.2 - Defi nition of Internal Timing
The internal operation of the ST10F280 is
controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for
example pipeline) or external (for example bus
cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
between two consecuti ve edges of the CPU cloc k,
calle d “TCL”.
The CPU clock signal can be generated by
different mechanisms. The duration of TCL and its
variation (and also the derived external timing)
depends on the mechanism used to generate
fCPU.
This influence must be regarded whe n ca lculating
the timi ngs for the S T10F280.
The example for PLL operation shown in Figure
77 refers to a PLL factor of 4.
Figu re 75 : Input / Output Waveforms
Figu re 76 : Float Waveforms
2.4V
0.45V
Test Points
0.2VDD+0.9 0.2VDD+0.9
0.2VDD-0.1 0.2VDD-0.1
A
C inputs during test ing are driv en at 2.4V f or a logic ‘1’ and 0.4V f o r a logic ‘0’.
T
iming measurements are made at VIH min for a l ogic ‘1’ and VIL max for a logic ‘0’ .
Timing
Reference
Points
VLoad +0.1V
VLoad -0.1V
VOH -0.1V
VOL +0.1V
VLoad
VOL
VOH
F or timing purposes a port pin is no longer floating when VLOAD changes of ±100mV.
It begins to float when a 100m V change from the loaded VOH/VOL le vel oc c urs (IOH/IOL = 20mA).
ST10F280
161/186
The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins
P0.15-13 (P 0H.7-5).
2 0.4. 3 - Cloc k Ge neration Mode s
The Table 40 assoc i ates the combinations of t hese th ree bit with the respec tive clock gener at i on mode .
Notes: 1. The ex t ernal clock input rang e refers to a CPU cloc k rang e of 1...40M Hz.
2. The max i m um depen ds on the du ty cy cle of the ext ernal cl ock signal.
3. Th e maximum inpu t fr equency is 25MHz when using a n externa l crystal with t he internal oscillator; providin g that internal serial
resistance of the crystal is less than 40
Ω
. Howev er, higher frequencies c an be applied with an extern al clock sourc e on pi n XTAL1,
but in this cas e, the in put clock si gnal mus t reach the defi ned le vels VIL and VIH2..
4. The PLL fre e-runni ng frequency is from 2 to 10MHz.
Fi gure 7 7 : Generation Mechanis ms for the CPU Clock
Table 40 : CP U Frequency Generation
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1Notes
111 f
XTAL x 4 2.5 to 10MHz Default configuration
110 f
XTAL x 3 3.33 to 13.33MHz
101 f
XTAL x 2 5 to 20MHz
100 f
XTAL x 5 2 to 8MHz
011 f
XTAL x 1 1 to 40MHz Direct drive 2 4
010 f
XTAL x 10 1 to 4MHz
001 f
XTAL x 0.5 2 to 80MHz CPU clock via prescaler3
000 f
XTAL x 2.5 4 to 16MHz
TCL TCL
fCPU
fXTAL
fCPU
fXTAL
Phase locked loop operation
Direct Clock Drive
TCL TCL
fCPU
fXTAL
Prescaler Operation TCL TCL
ST10F280
162/186
20.4.4 - Prescaler Op eration
When pin s P0.1 5-13 (P0H. 7-5) equal ’001’ during
reset, the CPU clock is derived from the internal
oscillator (input clock signal) by a 2:1 prescaler.
The frequency of fCPU is half the frequency of
fXTAL and the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the
per iod of the input clock fXTAL.
The timings listed in the AC Characteristics that
refer t o TCL therefore can be calculated usin g the
peri od of fXTAL for an y TCL .
Note that if the bit OWDDIS in SYSCON register
is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the
Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is swi tched off.
20.4.5 - Di rect Drive
When pin s P0.1 5-13 (P0H. 7-5) equal ’011’ during
reset the on-chip phase locked loop is disabled
and the CPU clock is directly driven from the
inter nal oscillator with the input clock signal.
The frequency of fCPU directly follows the
frequency of fXTAL so the hi gh and l ow time of fCPU
(i.e. the duration of an individual TCL) is defined
by the duty cycle of the input cl ock fXTAL.
Therefor, the timings gi ven in this chapter refer to
the minimum TCL. This minimum value can be
calculated by the fo llowing for m ula:
For two consecutive TCLs, the deviation caused
by the duty cycle of fXTAL is comp ensated, so t he
duration of 2 TCL is always 1/fXTAL.
The minimum value TCLmin has to be used only
once for timings that require an odd number of
TCLs (1,3,...). Timings that require an even
number of TCLs (2,4,...) may use t he formula:
Note: The address float timings in Multiplexed
bus mode (t11 a nd t45) use the maximu m
duration of TCL (TCLmax = 1/fXTAL x
DCmax) instead of TCLmin.
If the bit OWDDIS in SYSCON register is
cleared, the PLL runs on its free-running
frequency and del i v ers t he clock signal for
the Oscillator Watchdo g. If bit OW DDIS is
set, then the PLL is switched off.
20.4.6 - Oscillator Watchdog (OWD)
An on-chip watchdog oscillator is i mpl emented in
the ST10F280. This feature is used for safety
operation with external crystal oscillator (using
direct drive mode with or without prescaler). This
watchdog oscil lator operates as f ollo wing :
The reset default configuration enables the
watchdog oscillator. It can be disabled by setting
the OWDDIS (bi t 4 ) of SYSCO N register.
When the OWD is enabled, the PLL runs at its
free-running frequency, and it increments the
watchdog counter. The PLL free-running
frequency is from 2 t o 10MHz. On eac h transition
of external clock, the w atchdog counter is cleared.
If an external clock failure occurs, then the
watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to th e PLL
free-running clock signal, and the oscillator
watchdog Interrupt Request (XP3INT) is flagged.
The CPU clock will not switch back to the ext ernal
clock even if a valid ext ernal clock exits on XTAL1
pin. Only a hardware reset can switch the CPU
clock source bac k to direct clock input.
When the OWD is disabled, the CPU clock is
always external oscillator clock and the PLL is
switched off to decrease consumption supply
current.
20.4.7 - Phase Locked Loop
For all other combinations of pins P0.15-13
(P0H.7-5) during reset the on-chip phase locked
loop is enabled and i t provides the CPU cloc k (see
Table 40). The PLL multiplies the input frequency
by the factor F which is selected via the
combination of pins P0.15-13 (fCPU = fXTAL x F).
With every F’th transition of fXTAL the PLL circuit
synchronizes the CPU clock to the input clock.
This synchronization is done smoothly, so the
CPU cloc k frequency does not change abruptly.
Due to this adaptation to the input clock the
frequency of fCPU is constantly adjusted so it is
lo cke d t o fXTAL. The sl ight var iation causes a jitter
of fCPU which also effects the duration of
individual TC Ls.
The timings listed in the AC Characteristics that
refer to TCLs therefore must be calculated using
the minimum TCL that is possible under the
respectiv e circumstances.
TCLmin 1f⁄XTALlxlDCmin
=
DC duty cycle=
2TCL 1 fXTAL
⁄=
ST10F280
163/186
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is refered to one TCL
perio d. It decreases acc ording to the fo rmula a nd
to the Figure 78 given below. F or
N
peri ods of TCL
the minimum value is computed using the
correspon ding deviation D
N
:
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period o f 3 TCL periods
(N = 3):
D3 = 4 - 3/15 = 3.8%
3TCL
min =3 TCL
NOM x (1 - 3.8/100)
=3 TCL
NOM x 0. 962
3TCL
min = (36.075n s at fCPU = 40MHz )
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train gener ation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
20.4.8 - External Clock Drive XTAL1
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +12 5 °C
Not es: 1. Th eoret ic al min imu m. The real mini mum value depe nds on t he duty cycle of the inpu t c lock si gnal . 25MHz is the max imu m input
frequency when using an ex ter na l cry sta l oscillator. Howevwer, 40MHz can be applied with an ext erna l clock source.
2. The i nput clock signal must reac h th e defin ed l evels VIL and VIH2.
TCLMIN TCLNOM 1DN
100
-------------–
×=
D
N
4N15)%[]⁄–(±=
Fi gure 7 8 : A pproximated Maximum PLL Jitter
Parameter Symbol fCPU = fXTAL f
CPU = fXTAL / 2 fCPU = fXTAL x F
F = 2 / 2.5 / 3 / 4 / 5 / 10 Unit
min max min max min max
Oscillator period tOSC SR 25 1– 12.5 – 40 x N 100 x N ns
High time t1SR 10 2–5 2–10 2–ns
Low time t2SR 10 2–5 2–10 2–ns
Rise time t3SR – 3 2–3 3–3 2ns
Fall time t4SR – 3 2–3 2–3 2ns
3216
8
42
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formul a is vali d for
1 ≤ N ≤ 40 and 10MHz ≤ fCPU ≤ 40MHz.
ST10F280
164/186
Figu re 79 : External Clock Drive XTAL1
20.4.9 - M emory Cyc le Variab les
The tables below use three var iables which are der ived from the BUS CONx registers and rep resent the
special characteristics of the programmed memory cycle. The following table describes, how these
variables are to be computed.
Description Symbol Values
ALE Extension tATCL x [AL ECTL]
Memory Cycle Time wait states tC2 TCL x (15 - [MCTC])
Memory Tri-state Time tF2 TCL x (1 - [MTTC])
t1t3t4
VIH2
t2tOSC
VIL
ST10F280
165/186
20.4.10 - Multiplexed Bus
VDD = 5V ± 10% , VSS = 0V, TA = -40 to +125°C , CL = 50pF,
ALE cycl e time = 6 TCL + 2 tA + tC + tF (75ns at 40MHz CPU clock wi thout wait states).
Table 41 : M ultiplexed B us Characteristics
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
t5CC ALE high time 4 + tA– TCL - 8.5 + tA–ns
t
6
CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t
7
CC Address hold after ALE 14 + tA– TCL - 8.5 + tA–ns
t
8
CC ALE falling edge to RD, WR
(with RW-delay) 4 + tA– TCL - 8.5 + tA–ns
t
9
CC ALE falling edge to RD, WR (no
RW-delay) -8.5 + tA– -8.5 + tA–ns
t
10 CC Address float after RD, WR
(with RW-delay) 1–6 – 6ns
t
11 CC Address float after RD, WR
(no RW-delay) 1– 18.5 – TCL + 6 ns
t12 CC RD, W R low time
(with RW-delay) 15.5 + tC– 2 TCL -9.5 + tC–ns
t
13 CC RD, W R low time
(no RW-delay) 28 + tC– 3 TCL -9.5 + tC–ns
t
14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5
+ tA + tC– 3 TCL - 19
+ tA + tCns
t17 SR Address/Unlatched CS to va lid
data in – 22 + 2tA +
tC
– 4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t
19 SR Data float after RD 1– 16.5 + tF– 2 TCL - 8.5 + tFns
t22 CC Data valid to WR 10 + tC– 2 TCL -15 + tC–ns
t
23 CC Data hold after WR 4 + tF– 2 TCL - 8.5 + tF–ns
t
25 CC ALE rising edge after RD, WR 15 + tF– 2 TCL -10 + tF–ns
t
27 CC Address/Unlatched CS hold
after RD, WR 10 + tF– 2 TCL -15 + tF–ns
t
38 CC ALE falling edge to Latched CS -4 - tA10 - tA-4 - tA10 - tAns
t39 SR Latched CS low to Valid Data In – 18.5 + tC +
2tA
– 3 TCL - 19
+ tC + 2tAns
t40 CC Latched CS hold after RD, WR 27 + tF– 3 TCL - 10.5 + tF–ns
ST10F280
166/186
Note: 1. Partially tested, guaranted by desi gn charact erization.
t42 CC ALE fall. edge to RdCS, WrCS
(with RW delay) 7 + tA– T CL - 5.5+ tA–ns
t
43 CC ALE fall. edge to RdCS, WrCS
(no RW delay) -5.5 + tA– -5.5 + tA–ns
t
44 CC Address float after RdCS,
WrCS (with RW delay) 1–0 – 0ns
t
45 CC Address float after RdCS,
WrCS (no RW delay) 1– 12.5 – TCL ns
t46 SR RdCS to Valid Data In
(with RW delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW delay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t
49 CC RdCS, WrCS Low Time
(no RW delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
50 CC Data valid to WrCS 10 + tC– 2 TCL - 15+ tC–ns
t
51 SR Data hold after RdCS 0– 0 –ns
t
52 SR Data float after RdCS 1– 16.5 + tF– 2 TCL - 8.5+tFns
t54 CC Address hold after
RdCS, WrCS 6 + tF– 2 TCL - 19 + tF–ns
t
56 CC Data hold after WrCS 6 + tF– 2 TCL - 19 + tF–ns
Table 41 : M ultiplexed B us Characteristics
Symbol Parameter
Max. CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
ST10F280
167/186
Fi gure 8 0 : Ex ternal M emo ry Cycle : Multiplexed Bus , With / Without Read / Write Delay, Normal ALE
Data In
Data Out
Address
Address
t
38
t
10
Read Cycle
Write Cycle
t
5
t
16
t
39
t
40
t
25
t
27
t
18
t
14
t
22
t
23
t
12
t
8
t
8
t
6m
t
19
Address
t
17
t
6
t
7
t
9
t
11
t
13
t
15
t
16
t
12
t
13
Address
t
9
t
17
t
6
t
27
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
Address/Data
RD
WR
WRL
BHE
WRH
Bus (P0)
Address/Data
Bus (P0)
ST10F280
168/186
Fi gure 8 1 : Ex ternal M emo ry Cycle: Multiplexed Mus, With / W ithout Read / Write Delay, Extended ALE
Data Out
Address
Data In
Address
Address
t
5
t
16
t
6
t
7
t
39
t
40
t
14
t
8
t
18
t
23
t
6
t
27
t
38
t
10
t
19
t
25
t
17
t
9
t
11
t
15
t
12
t
13
t
8
t
10
t
9
t
11
t
12
t
13
t
22
t
27
t
17
t
6
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
A23-A16
(A15-A8)
RD
WR
WRL
BHE
WRH
Address/Data
Bus (P0)
Address/Data
Bus (P0)
ST10F280
169/186
Fi gure 8 2 : E xternal Memor y Cycle: Multipl exed Bus, With / Wit hout Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
Data In
Data Out
Address
Address
t
44
t
5
t
16
t
25
t
27
t
51
t
46
t
50
t
56
t
48
t
42
t
42
t
6
t
52
Address
t
17
t
6
t
7
t
43
t
45
t
49
t
47
t
16
t
48
t
49
Address
t
43
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
ST10F280
170/186
Fi gure 8 3 : External Memory Cycl e: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE,
Read / Write Chip Select
Data Out
Address
Data In
Address
Address
t
5
t
16
t
6
t
7
t
46
t
42
t
42
t
50
t
18
t
56
t
6
t
54
t
44
t
19
t
25
t
17
t
43
t
45
t
47
t
48
t
49
t
49
t
43
t
48
t
44
t
45
Read Cycle
Write Cycle
CLKOUT
ALE
A23-A16
(A15-A8)
BHE
RdCSx
WrCSx
Address/Data
Bus (P0)
Address/Data
Bus (P0)
ST10F280
171/186
20.4.11 - Demultiplexed Bus
VDD = 5V ± 10%, VSS = 0V , TA = - 40 to +12 5°C, CL = 50pF,
ALE cycl e time = 4 TCL + 2 tA + tC + tF (50ns at 40MHz CPU clock wi thout wait states).
Table 42 : Dem ultiplexed Bu s Characteristics
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t5CC ALE high time 4 + tA– TCL - 8.5 + tA–ns
t
6
CC Address setup to ALE 2 + tA– TCL - 10.5 + tA–ns
t
80 CC Address/Unlatched CS setup to
RD, WR
(with RW-delay)
16.5 + 2tA– 2 TCL - 8.5 + 2tA–ns
t
81 CC Address/Unlatched CS setup to
RD, WR
(no RW-delay)
4 + 2tA– TCL - 8.5 + 2tA–ns
t
12 CC RD, WR low time
(with RW-delay) 15.5 + tC– 2 TCL - 9.5 + tC–ns
t
13 CC RD, WR low time
(no RW-delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
14 SR RD to valid data in
(with RW-delay) –6 + t
C– 2 TCL - 19 + tCns
t15 SR RD to valid data in
(no RW-delay) – 18.5 + tC– 3 TCL - 19 + tCns
t16 SR ALE low to valid data in – 18.5 + tA +
tC
– 3 TCL - 19
+ tA + tCns
t17 SR Add ress/U nlatc hed C S to valid
data in –22 + 2t
A
+
tC
– 4 TCL - 28
+ 2tA + tCns
t18 SR Data hold after RD
rising edge 0– 0 –ns
t
20 SR Data float after RD rising edge
(with RW-delay) 1 3 – 16.5 + tF– 2 TCL - 8.5
+ tF + 2tA 1 ns
t21 SR Data float after RD rising edge
(no RW-delay) 1 3 –4 + t
F– TCL - 8.5
+ tF + 2tA 1 ns
t22 CC Data valid to WR 10 + tC– 2 TCL - 15 + tC–ns
t
24 CC Data hold after WR 4 + tF– TCL - 8.5 + tF–ns
t
26 CC ALE rising edge after RD, WR -10 + tF– -10 + tF–ns
t
28 CC Add ress/U nlatc hed C S hold
after RD, WR 20 (no tF)
-5 + tF
(tF > 0)
– 0 (no tF)
-5 + tF
(tF > 0)
–ns
t
28h CC Address/U nlatc hed C S hold
after WRH -5 + tF– -5 + tF–ns
t
38 CC ALE falling edge to Latched CS -4 - tA6 - tA-4 - tA6 - tAns
t39 SR Latc hed C S low to Valid Data In – 18.5
+ tC + 2tA– 3 TCL - 19
+ tC + 2tAns
ST10F280
172/186
Notes: 1. RW-del ay and
t
A ref er to the next following bus cycle.
2. R ead data are latched with the same clock edge that triggers the address cha nge and the rising RD edge. Therefore address
changes befor e the end of RD have no impact on read cycles.
3. Par t i al l y tes ted, gua ranteed by design ch aracterizat i on.
t41 CC Latc hed C S hold after RD, WR 2 + tF– TCL - 10.5 + tF–ns
t
82 CC Address setup to RdCS, WrCS
(with RW-delay) 14.5 + 2tA– 2 TCL - 10.5 +
2tA–ns
t
83 CC Address setup to RdCS, WrCS
(no RW-delay) 2 + 2tA– TCL - 10.5 + 2tA–ns
t
46 SR RdCS to Valid Data In
(with RW-delay) –4 + t
C– 2 TCL - 21 + tCns
t47 SR RdCS to Valid Data In
(no RW-delay) – 16.5 + tC– 3 TCL - 21 + tCns
t48 CC RdCS, WrCS Low Time
(with RW-delay) 15.5 + tC– 2 TCL - 9.5
+ tC–ns
t
49 CC RdCS, WrCS Low Time
(no RW-delay) 28 + tC– 3 TCL - 9.5 + tC–ns
t
50 CC Data valid to WrCS 10 + tC– 2 TCL - 15 + tC–ns
t
51 SR Data hold after RdCS 0– 0 –ns
t
53 SR Data float after RdCS
(with RW-delay) 3– 16.5 + tF– 2 TCL - 8.5 + tFns
t68 SR Data float after RdCS
(no RW-delay) 3–4 + t
F– TCL - 8.5 + tFns
t55 CC Address hold after
RdCS, WrCS -8.5 + tF– -8.5 + tF–ns
t
57 CC Data hold after WrCS 2 + tF– TCL - 10.5 + tF–ns
Table 42 : Dem ultiplexed Bu s Characteristics
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
ST10F280
173/186
Fi gure 8 4 : Ex ternal Memo ry Cycle: Demultiplexed Bus, W ith / Without Read / Write Delay, Normal ALE
Note: 1. Un-latched CSx = t41u = t41 TCL =10.5 + t F
.
Write Cycle
CLKOUT
ALE
A23-A16
A15-A0 (P1)
BHE
WR
WRL
WRH
Data In
Data Out
t
38
t
5
t
16
t
39
t
41
t
18
t
14
t
22
t
12
Address
t
17
t
13
t
15
t
12
t
13
t
21
t
20
t
81
t
80
t
26
t
24
t
17
t
6
t
41u
t
6
t
80
t
81
t
28 (or
t
28h)
CSx
Read Cycle
Data Bus (P0)
RD
1)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
ST10F280
174/186
Figure 85 :
External M em ory Cycle: Dem ul tipl ex ed Bus, With / Without Read / Write Delay, Ext ended ALE
Address
t
5
t
16
t
39
t
41
t
14
t
24
t
6
t
38
t
20
t
26
t
17
t
15
t
12
t
13
t
12
t
13
t
22
Data In
t
18
t
21
t
6
t
17
t
28
t
28
Data Out
t
80
t
81
t
80
t
81
Read Cycle
Write Cycle
CLKOUT
ALE
CSx
RD
WR
WRL
WRH
Data Bus (P0)
(D15-D8) D7-D 0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F280
175/186
Fi gure 8 6 : External Memory Cycl e: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE,
Read / Write Chip Select
Read Cycle
Write Cycle
CLKOUT
ALE
Data In
Data Out
t
5
t
16
t
51
t
46
t
50
t
48
Address
t
17
t
49
t
47
t
48
t
49
t
68
t
53
t
83
t
82
t
26
t
57
t
55
t
6
t
82
t
83
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F280
176/186
Fi gure 8 7 : Ex ternal M emo ry Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read /
Wri te Chip S e lect
Address
t
5
t
16
t
46
t
57
t
6
t
53
t
26
t
17
t
47
t
48
t
49
t
48
t
49
t
50
Data In
t
51
t
68
t
55
Data Out
t
82
t
83
t
82
t
83
Read Cycle
Write Cycle
CLKOUT
ALE
RdCSx
WrCSx
Data Bus (P0)
(D15-D8) D7-D0
Data Bus (P0)
(D15-D8) D7-D0
A23-A16
A15-A0 (P1)
BHE
ST10F280
177/186
20.4.12 - CLKOUT and READY
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +12 5°C, CL = 50pF
Notes: 1. T hese tim i ngs are gi ven for test pur poses onl y, in order to as sure recognition at a sp ecific cl ock edge.
2. Demultiplexed bu s is the wo rst case. For multiplexe d bu s 2 TCL are to be added to the ma ximum values. Th is adds even more
time for deactivating READ Y.
The 2tA and tC re fer to th e next foll owing bus cy cl e, t F refers t o the current bus cyc l e.
Table 43 : CLKOUT and READY Character istics
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t29 CC CLKOUT cycle time 25 25 2 TCL 2TCL ns
t30 CC CLKOUT high time 4 – TCL – 8.5 – ns
t31 CC CLKOUT low time 3 – TCL – 9.5 – ns
t32 CC CLKOUT rise time – 4 – 4 ns
t33 CC CLKOUT fall time – 4 – 4 ns
t34 CC CLKOUT rising edge to
ALE falling edge -2 + tA8 + tA-2 + tA8 + tAns
t35 SR Synchronous READY
setup time to CLKOUT 12.5 – 12.5 – ns
t36 SR Synchronous READY
hold time after CLKOUT 2– 2 –ns
t
37 SR Asynchronous READY
low time 35 – 2 TCL + 10 – ns
t58 SR Asynchronous READY
setup time 1) 12.5 – 12.5 – ns
t59 SR Asynchronous READY
hold time 1) 2– 2 –ns
t
60 SR Async. READY hold time after
RD, WR high (Demultiplexed
Bus) 2)
00 + 2tA + tC + tF
2)
0 TCL - 12.5
+ 2tA + t C + tF 2) ns
ST10F280
178/186
Fi gure 8 8 : CLKOUT and READY
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The l eading edge of the res pective co m m and dep ends on RW-delay.
3. READY sampled HIGH at this samplin g point generates a R EADY contro lled wait state, READY samp led LOW at this sampling
point term i nates the curre ntly running bus cycle.
4. REA DY may be deactivat ed in response to the trailing (ri sing) edge of the correspo nding c om m and (RD or WR).
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because
CLKOUT is not enabled), it must fulfill t37 in order to be saf ely synchronized. This is guaranteed, if READY is removed in response to
the command (see N o t e 4)).
6. M ul tiplexed bus modes have a MUX wai t s tate added after a bus cycle, and an additional MTTC wait st ate may be i nserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycle s, for a demultiplexed bus without MTTC wait state this
delay is zero.
7. The next external bus c ycle may start here.
t30
t34
t35 t36 t35 t36
t58 t59 t58 t59
wait state
READY M UX / Tri-state 6)
t32 t33
t29
Runnin g cycle 1)
t31
t37
3) 3)
5)
t60 4)
6)
2)
7)
3) 3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
ST10F280
179/186
20.4.13 - External Bus Arbitration
VDD = 5V ± 10%, VSS = 0V, TA = - 40 to +12 5°C, CL = 50pF
Note: 1. Partially tested, guaranteed by de sign character i zation.
Notes: 1. The ST10F280 will complete the currently running bus c ycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t
64
.
Symbol Parameter
Maximum CPU Clock
= 40MHz Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
Minimum Maximum Minimum Maximum
t61 SR HOLD input setup time
to CLKOUT 15 – 15 – ns
t62 CC CLKOUT to HLDA high
or BREQ low delay – 12.5 – 12.5 ns
t63 CC CLKOUT to HLDA low
or BREQ high delay – 12.5 – 12.5 ns
t64 CC CSx release 1– 15 – 15 ns
t65 CC CSx drive -4 15 -4 15 ns
t66 CC Other signals release 1– 15 – 15 ns
t67 CC Other signals drive -4 15 -4 15 ns
Fi gure 8 9 : External Bus Arbitration, Releasing the Bus
t61
t63
t66
1)
t64
1)
2)
t62
3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
ST10F280
180/186
Fi gure 9 0 : External Bus Arbitration, (regaining the bus)
Notes: 1. This is the last chance for BREQ to trigger the indi cated regain-sequence. Even if B REQ is ac tivated earli er, the r egain-s equence
is initiated by HOLD going high. Please note that HOLD m ay also be di sactivated without the ST10F280 requesting t he bus.
2. The next ST10F 280 d rive n bus c ycle may start h ere.
CLKOUT
HOLD
HLDA
Other
Signals
t62
CSx
(On P6.x)
t67
t62
1)
2)
t65
t61
BREQ
t63
t62
ST10F280
181/186
20.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing
20.4.14.1 Master Mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +12 5°C, CL = 50pF
Note: 1. Timin g guaranteed by design.
The for mula for SSC Clock Cycle time is : t300 = 4 TCL * (<S SCBR> + 1)
Where <SSCBR> represents the content of the SSC B aud rate register, taken as unsigned 16-bit i nteger.
Notes: 1. The phase and pol arity of shift and latc h edge of SCLK is programm able. This figure uses the leading clock edge as shift edge (drawn
in bold), with latch on trailing edge (SSCPH = 0b), Idle c lock line is low, leading cloc k edge is lo w -to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Symbol Parameter Maxim um Baud rate = 10M Baud
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t300 CC SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t301 CC SSC clock high time 40 – t300/2 - 10 –ns
t
302 CC SSC clock low time 40 – t300/2 - 10 –ns
t
303 CC SSC clock rise time – 10 – 10 ns
t304 CC SSC clock fall time – 10 – 10 ns
t305 CC Write data valid after shift edge – 15 – 15 ns
t306 CC Write data hold after shift edge 1-2 – -2 – ns
t307p SR Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
37.5 – 2 TCL + 12.5 – ns
t308p SR Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
50 – 4 TCL – ns
t307 SR Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
25 – 2 TCL – ns
t308 SR Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
0–0–ns
Fi gure 9 1 : SS C Ma ster Timing
t
303
t
304
t
305
t
305
t
305
t
306
1st Ou t Bit Last O u t Bit2nd Out Bit
t
300
t
302
t
301
1) 2)
t
307
2nd.In Bit
1st.In Bit
t
308
t
307
Last.In Bit
t
308
SCLK
MTSR
MRST
ST10F280
182/186
20.4.14.2 S lave mode
VCC = 5V ±10%, VSS = 0V, CPU clock = 40MHz, TA = -40 to +12 5°C, CL = 50pF
The for mula for SSC Clock Cycle time is: t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC B aud rate register, taken as unsigned 16-bit i nteger.
Notes: 1. The phase and pol arity of shift and latc h edge of SCLK is programm able. This figure uses the leading clock edge as shift edge (drawn
in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading clock edge is low-to-high transiti on (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
Symbol Parameter
Maximum Baud rate=10MB d
(<SSCBR> = 0001h) Variable Baud rate
(<SSCBR>=0001h-FFFFh) Unit
Minimum Maximum Minimum Maximum
t310 SR SSC clock cycle time 100 100 8 TCL 262144 TCL ns
t311 SR SSC clock high time 40 – t310/2 - 10 –ns
t
312 SR SSC clock low time 40 – t310/2 - 10 –ns
t
313 SR SSC clock rise time – 10 – 10 ns
t314 SR SSC clock fall time – 10 – 10 ns
t315 CC Write data valid after shift edge – 39 – 2 TCL + 14 ns
t316 CC Write data hold after shift edge 0 – 0 – ns
t317p SR
Read data setup time before latch edge,
phase error detection on (SSCPEN = 1)
62 – 4 TCL + 12 – ns
t318p1SR
Read data hold time after latch edge,
phase error detection on (SSCPEN = 1)
87 – 6 TCL + 12 – ns
t317 SR
Read data setup time before latch edge,
phase error detection off (SSCPEN = 0)
6–6–ns
t
318 SR
Read data hold time after latch edge,
phase error detection off (SSCPEN = 0)
31 – 2 TCL + 6 – ns
Fi gure 9 2 : SS C S lave Timing
t
313
t
314
t
315
t
315
t
315
t
316
1st Out Bit Last Out Bit2nd Out Bi t
t
310
t
312
t
311
1) 2)
t
317
2nd.In Bit1st.In Bit
t
318
t
317
Last.In Bit
t
318
SCLK
MRST
MTSR
ST10F280
183/186
21 - PACKAGE MECHANICA L DATA
Fi gure 9 3 : Package Outline PBGA 208 (23 x 23 x 1.96 mm)
Dimensions Millimeters Inches (approx)
Minimum Typical Maximum Minimum Typical Maximum
A 1.960 0.077
A1 0.500 0.600 0.700 0.019 0.024 0.028
A2 1.360 0.054
A3 0.560 0.022
φ
b 0.600 0.760 0.900 0.024 0.030 0.035
D 22.900 23.000 23.100 0.902 0.906 0.909
D1 20.320 0.800
E 22.900 23.000 23.100 0.902 0.906 0.909
E1 20.320 0.800
e 1.270 0.50
f 1.240 1.340 1.440 0.049 0.053 0.057
aaa 0.150 0.006
A1
E1
φ
b (208 + 25 BALLS)
U
T
R
P
N
M
L
K
10 11 12 13 14 15 16 17
000
6789
J
G
F
H
E
D
B
A
C
45123
A1 BA LL PAD CORNE R 2
f
E
e
e
D1
D
f
A2
A3
C
SEATING
PLANE
A
C
ST10F280
184/186
Notes:1. PB GA stands for Plastic Ball Grid Array.
2. The term inal A1 corn er must be identified on t he top surface of the package by u sing a cor ner
chamfer, ink or metalized markings, identation or other feature of package body or integral
heastslug. A distinguishing feature is allowable on the bottom of the package to identify the
term inal A1 corner. Exact shape and size of this feature is optional.
22 - ORDERING I NF ORMATI ON
Salest ype Tem pera ture rang e Package
ST10F280-JT3 -40°C to +125°C PBGA 208 (23 x 23 x 1.96 mm)
ST10F280
185/186
186/186
ST10F280
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
conseque nces of use of such i nformation nor for any infringement of patents or ot her rights of third parties which may result from
its use. No licens e is granted by implication or otherwise under any pat ent or patent rights of STMicroelectron ics. S pec ific at ions
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems with out expres s written approval of STMicroelec tronics .
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroe lectro n ic s Al l Rights Rese rved
STMi croelectronics GROUP OF COMPANIES
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Singapore - Spain - Sw eden - Swit zerla nd - United K i ngdom - U ni ted Stat es
http://www.st.com
ST10F280.REF
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