Features
••Monolithic CMOS A/D Converters
Microprocessor Compatible
Parallel and Serial Output
Inherent Track/Hold Input
••True 12, 14 and 16-Bit Precision
••Conversion Times:
CS5016 16.25 µs
CS5014 14.25 µs
CS5012A 7.20 µs
••Self Calibration Maintains Accuracy
Over Time and Temperature
••Low Power Dissipation: 150 mW
••Low Distortion
General Description
The CS5012A/14/16 are 12, 14 and 16-bit monolithic
analog to digital converters with conversion times of
7.2µs, 14.25µs and 16.25µs. Unique self-calibration cir-
cuitry insures excellent linearity and differential non-
linearity, with no missing codes. Offset and full scale
errors are kept within 1/2 LSB (CS5012A/14) and
1 LSB (CS5016), eliminating the need for calibration.
Unipolar and bipolar input ranges are digitally select-
able.
The pin compatible CS5012A/14/16 consist of a DAC,
conversion and calibration microcontroller, oscillator,
comparator, microprocessor compatible 3-state I/O,
and calibration circuitry. The input track-and-hold, in-
herent to the devices’ sampling architecture, acquires
the input signal after each conversion using a fast
slewing on-chip buffer amplifier. This allows throughput
rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and
50 kHz (CS5016).
An evaluation board (CDB5012/14/16) is available
which allows fast ev aluation of ADC performance.
ORDERING INFORMATION: Pages 2-45, 2-46, & 2-47
MAR ’95
DS14F6
2-7
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 FAX : (512) 445 7581
16, 14 & 12-Bit, Self-Calibrating A/D Converters
Semiconductor Corporation CS5016 CS5014 CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MS B )
D4 (LSB) CS5012A
6
7
8
9
12
13
14
15
16
17
18
19
D2 (LSB) CS5014
D0 (LSB) CS5016
D1
SCLKEOT EOC SDATA
2
3
4
5
37 38 39 40
D3
CLKIN
CLOCK
GENERATOR
20
INTRLV
34
RST
3221
A0
23
RD
22
HOLD
1
BW
3324
CAL
35
CS BP/UP
REFBUF
AGND
29
VREF
28
AIN 26
27
CHARGE
REDISTRIBUTION
DAC
COMPARATOR
VA+ VA- VD+ VD- DGND TST
25 30 11 36 10 31
+
-
+
-
+
-
+
-
CONTROL
CALIBRATION
MEMORY
MICROCONTROLLER
STATUS REGISTER
Copyright
Crystal Semiconductor Corporation 1995
(All Rights Reserved)
CS5012A
CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200 Ω)
CS5012A-K CS5012A-B CS5012-T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error (Note 1)
Drift (Note 2) ±1/4
±1/8 ±1/2 ±1/4
±1/8 ±1/2 ±1/4
±1/8 ±1/2 LSB12
∆LSB12
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 LSB12
∆LSB12
Full Scale Error (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/8 ±1/2 LSB12
∆LSB12
Unipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Bipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Bipolar Negative Full-Scale Error (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1/4
±1/4 ±1/4
±1/4 ±1/4
±1/4 LSB12
∆LSB12
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 k Hz Input
Full Scale, 12 k Hz Input 84
84 92
88 84
84 92
88 84
84 92
88 dB
dB
Total Harmonic Distortion 0.008 0.008 0.008 %
Signal-to-Noise Ratio (Note 1)
1 kHz, 0 dB Input
1 kHz, - 60 dB Input 72 73
13 72 73
13 72 73
13 dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 45
90 45
90 µVrms
µVrms
Notes: 1. Applies after calibration at any temperature within the specified temper ature range.
2. Total drift over specified temperature range since calibration at power-up at 25 °C
3. Wideband noise aliased into the baseband. Referred to the input.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
2-8 DS14F6
CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A-K CS5012A-B CS5012-T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode CS5012
CS5012A
Bipolar Mode CS5012
CS5012A
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
pF
pF
pF
pF
Conversion & Throughput
Conversion Time -7 (Notes 5 and 6)
-12 7.2
12.25 7.2
12.25 12.25 µs
µs
Acquisition Time -7 (Note 6)
-12 2.5
3.0 2.8
3.75 2.5
3.0 2.8
3.75 3.0 3.75 µs
µs
Throughput -7 (Note 6)
-12 100
62.5 100
62.5 62.5 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
(CS5012) ID+
(CS5012A) ID+
ID-
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
-3
19
-19
6
-6
mA
mA
mA
mA
mA
Power Dissipation (Note 7) 150 250 150 250 150 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
Notes: 4. Applies only in track mode. When c onverting or calibrating, input capacitanc e will not exceed 15 pF.
5. Measured from falling transition on HOLD to falling transition on EOC.
6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s
conversion clock , interleave calibrate is disabled, and operation is from the full-rated, external clock.
Refer to the sec tion
Conversion Time/Throughput
for a detailed discussion of conversion timing.
7. All outputs unloaded. A ll inputs CMOS levels .
8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.
CS5012A
DS14F6 2-9
CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V ; CLKIN = 4 MHz for -14, 2 MHz for -28; A nalog Source Impedance = 200 Ω)
CS5014-K CS5014-B CS5014-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/8
±1/2 ±1/4
±1/8
±1/2 ±1/4
±1/2
±1/8
±1/2
±1.5 LSB14
LSB14
∆LSB14
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 LSB14
∆LSB14
Full Scale Error (Note 1)
Drift (Note 2) ±1/2
±1/4 ±1±1/2
±1/4 ±1±1/2
±1/2 ±1LSB14
∆LSB14
Unipolar Offset K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/4
±3/4 ±1/4
±1/4
±3/4 ±1/4
±1/2
±3/4
±1LSB14
LSB14
∆LSB14
Bipolar Offset K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/4
±3/4 ±1/4
±1/2
±3/4 ±1/4
±1/2
±3/4
±1LSB14
LSB14
∆LSB14
Bipolar Negative Full-Scale Error (Note 1)
K, B, T
S
Drift (Note 2)
±1/2
±1/4
±1±1/2
±1/4
±1±1/2
±1/2
±1
±1.5 LSB14
LSB14
∆LSB14
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1
±1/2 ±1
±1±1
±1LSB14
∆LSB14
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input K, B, T
S
Full Scale, 12 kHz Input K, B, T
S
94
84
98
87
94
84
98
87
94
85
84
80
98
87
dB
dB
dB
dB
Total Harmonic Distortion 0.003 0.003 0.003 %
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input K, B, T
S
1 kHz, - 60 dB Input
82 84
23
82 84
23
82
80 84
23
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 45
90 45
90 µVrms
µVrms
Notes: 9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28
for the CS5016.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
CS5014
2-10 DS14F6
CS5014
CS5014 ANALOG CHARACTERISTICS (continued)
CS5014-K CS5014-B CS5014-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 275
165 375
220 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -14 (Notes 5 and 6)
-28 14.25
28.5 14.25
28.5 14.25
28.5 µs
µs
Acquisition Time -14 (Note 6)
-28 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 µs
µs
Throughput -14 (Note 6)
-28 55.6
27.7 55.6
27.7 55.6
27.7 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 120 250 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
DS14F6 2-11
CS5016
CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V ; CLKIN = 4 MHz for -16, 2 MHz for -32; A nalog Source Impedance = 200 Ω;
Synchronous S ampling.)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error J, A, S (Note 1)
K, B, T
Drift (Note 2)
0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.0076
0.0015 %FS
%FS
∆LSB16
Differential Linearity (Note 10) 16 16 16 Bits
Full Scale E rror J, A, S (Note 1)
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±1
±3
±3±2
±2
±2
±4
±3LSB16
LSB16
∆LSB16
Unipolar Offset J, A, S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±1
±3
±3±1
±1
±2
±4
±3LSB16
LSB16
∆LSB16
Bipolar Offset J, A, S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±2
±2
±2±1
±1
±2
±4
±2LSB16
LSB16
∆LSB16
Bipolar Negative Full-Scale Error (Note 1)
J, A, S
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±2
±3
±3±2
±2
±2
±5
±3LSB16
LSB16
∆LSB16
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input J, A, S
K, B, T
Full Scale, 12 kHz Input J, A, S
K, B, T
96
100
85
85
100
104
88
91
96
100
85
85
100
104
88
91
92
100
82
85
100
104
88
91
dB
dB
dB
dB
Total Harmonic Distortion J, A, S
Full Scale, 1 kHz Input K, B, T 0.002
0.001 0.002
0.001 0.002
0.001 %
%
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input J, A, S
K, B, T
1 kHz, - 60 dB Input J, A, S
K, B, T
87
90 90
92
30
32
87
90 90
92
30
32
84
90 90
92
30
32
dB
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 35
70 35
70 35
70 µVrms
µVrms
Notes: 10. Minimum resolution for which no missing codes is guaranteed
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
2-12 DS14F6
CS5016
CS5016 ANALOG CHARACTERISTICS (continued)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 275
165 375
220 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -16 (Notes 5 and 6)
-32 16.25
32.5 16.25
32.5 16.25
32.5 µs
µs
Acquisition Time -16 (Note 6)
-32 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 µs
µs
Throughput -16 (Note 6)
-32 50
26.5 50
26.5 50
26.5 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 120 250 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
DS14F6 2-13
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+)
Parameter Symbol Min Typ Max Units
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied: -7
-12
fCLK 1.75
100 kHz
100 kHz
-
-
-
-
6.4
4.0
MHz
MHz
MHz
CS5014/5016 CLKIN Frequency:
Internally Generated: -14, -16
-28, -32
Externally Supplied: -14, -16
-28, -32
fCLK 1.75
1
100 kHz
100 kHz
-
-
-
-
-
-
4
2
MHz
MHz
MHz
MHz
CLKIN Duty Cycle 40 - 60 %
Rise Times: Any Digital Input
Any Digital Output trise -
--
20 1.0
-µs
ns
Fall Times: Any Digital Input
Any Digital Output tfall -
--
20 1.0
-µs
ns
HOLD Pulse Width thpw 1/fCLK+50 - tcns
Conversion Time: CS5012A
CS5014
CS5016
tc49/fCLK+50
57/fCLK
65/fCLK
-
-
-
53/fCLK+235
61/fCLK+235
69/fCLK+235
ns
ns
ns
Data Delay Time tdd - 40 100 ns
EOC Pulse Width (Note 11) tepw 4/fCLK-20 - - ns
Set Up Times: CAL, INTRLV to CS Low
A0 to CS and RD Low tcs
tas 20
20 10
10 -
-ns
ns
Hold Times: CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid tah
tch 50
50 30
30 -
-ns
ns
Access Times: CS Low to Data Valid A, B, J, K
S, T
RD Low to Data Valid A, B, J, K
S, T
tca
tra
-
-
-
-
90
115
90
90
120
150
120
150
ns
ns
ns
ns
Output Float Delay: K, B
CS or RD High to Output Hi-Z T tfd -
-90
90 110
140 ns
ns
Serial Clock Pulse Width Low
Pulse Width High tpwl
tpwh -
-2/fCLK
2/fCLK -
-ns
ns
Set Up Times: SDATA to SCLK Rising tss 2/fCLK-50 2/fCLK -ns
Hold Times: SCLK Rising to S DATA tsh 2/fCLK-100 2/fCLK -ns
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
CS5012A, CS5014, CS5016
2-14 DS14F6
90%
10%
t
fall
rise
t
90%
10%
Hi-Z Hi-Z
ch
t
t
cs
t
ah
t
fd
tas
tra
tca
HOLD
EOC
Output Data
thpw
t
c
LA ST CON VERSION D ATA VALID
t
dd NEW DAT A V AL ID
tepw
D0-D15
A0
CS
RD
CAL, INTRLV
SDATA
t
ss tsh
SCLK
t
pwl
t
pwh
Rise and Fall Times
Conversion Timing
Serial Output Timing
Read and Calibration Control Timing
CS5012A, CS5014, CS5016
DS14F6 2-15
CS5012A, CS5014, CS5016
DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage VIH 2.0 - - V
Low-Level Input Voltage VIL --0.8V
High-Level Output Voltage (Note 12) VOH (VD+) - 1.0V - - V
Low-Level Output Voltage Iout = 1.6mA VOL --0.4V
Input Leakage Current Iin --10
µA
3-State Leakage Current IOZ --
±10 µA
Digital Output Pin Capacitance Cout -9-pF
Notes: 12. Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ I out = -40 µA).
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13)
Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Digital
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
Analog Reference Voltage VREF 2.5 4.5 (VA+) - 0.5 V
Analog Input Voltage: (Note 14)
Unipolar
Bipolar VAIN
VAIN AGND
-VREF -
-VREF
VREF V
V
Notes: 13. All voltages with respect to ground.
14. The CS5012A/14/16 can ac cept input voltages up to the analog supplies (VA+ and V A-).
It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode
and -VREF in bipolar mode.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.)
WARNING: Operation at or beyond these limits may reult in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
DC Power Supplies: Positive Digital (Note 15)
Negative Digital
Positive A nalog
Negative Analog
VD+
VD-
VA+
VA-
-0.3
0.3
-0.3
0.3
6.0
-6.0
6.0
-6.0
V
V
V
V
Input Current, Any P in Except Supplies (Note 16) Iin -±10 mA
Analog Input Voltage (AIN and V REF pins) VINA (VA-) - 0.3 (VA+) + 0.3 V
Digital Input Voltage VIND -0.3 (VA+) + 0.3 V
Ambient Operating Temperature TA-55 125 °C
Storage Temperature Tstg -65 150 °C
Notes: 15. In addition, VD+ s hould not be greater than (VA+) + 0.3V.
16. Transient currents of up to 100 mA will not cause SCR latch-up.
2-16 DS14F6
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
A unique charge redistribution architecture is
used to implement the successive approximation
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
vice is not calibrating or converting, all capacitors
are tied to AIN forming Ctot. Switch S1 is closed
and the charge on the array, Qin, tracks the input
sign al V in (Figure 2a).
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capaci-
tor array and creates a floating node at the
comparator’s input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
AIN
VREF
AGND
CC/2
C/4 C/8
MSB
LSB
Bit 11 Bit 10
Bit 9
Bit 8
Bit 0
Dummy
C/X S1
Bit 13
Bit 15
Bit 12
Bit 14 Bit 11
Bit 13
Bit 10
Bit 12
CS5012A:
CS5014:
CS5016:
C/X
X = 2048
X = 8192
X = 32768
CS5012A
CS5014
CS5016
C = C + C/2 + C/4 + ... + C/X
tot
Figure 1. Charge Redistribution DAC
(1-D) C tot
in
Q+
-
Vfn To MCU
S1
Ctot
D.
VREF
AGND
D for
VREF
Vin =0V
fn
V=
Figure 2b. Conve rt M ode
in
Q
Ctot
S1
V
in
AIN
+
-
To MCU
=V
in
C
tot
in
-Q
Figure 2a. Tr acking Mode
CS5012A, CS5014, CS5016
DS14F6 2-17
during conversion much like a hold capacitor in a
sample/hold amplifier.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND
to form a capacitive divider. Since the charge at
the floating node remains fixed, the voltage at
that point depends on the proportion of capaci-
tance tied to VREF versus AGND. The
successive-approximation algorithm is used to
find the proportion of capacitance, termed D in
Figure 2b, which when connected to the refer-
ence will drive the voltage at the floating node
(Vfn) to zero. That binary fraction of capacitance
represents the converter’s digital output.
This charge redistribution architecture easily sup-
ports bipolar input ranges. If half the capacitor
array (the MSB capacitor) is tied to VREF rather
than AIN in the track mode, the input range is
doubled and is offset half-scale. The magnitude
of the reference voltage thus defines both positive
and negative full-scale (-VREF to +VREF), and
the digital code is an offset binary representation
of the input.
Calibration
The ability of the CS5012A/14/16 to convert ac-
curately clearly depends on the accuracy of their
comparator and DAC. The CS5012A/14/16 util-
ize an "auto-zeroing" scheme to null errors
introduced by the comparator. All offsets are
stored on the capacitor array while in the track
mode and are effectively subtracted from the in-
put signal when a conversion is initiated.
Auto-zeroing enhances power supply rejection at
frequencies well below the conversion rate.
To achieve complete accuracy from the DAC, the
CS5012A/14/16 use a novel self-calibration
scheme. Each bit capacitor, shown in Figure 1,
actually consists of several capacitors which can
be manipulated to adjust the overall bit weight.
An on-chip microcontroller adjusts the subarrays
to precisely ratio the bits. Each bit is adjusted to
just balance the sum of all less significant bits
plus one dummy LSB (for example, 16C = 8C +
4C + 2C + C + C). Calibration resolution for the
array is a small fraction of an LSB resulting in
nearly ideal differential and integral linearity.
DIGITAL CIRCUIT CONNECTIONS
The CS5012A/14/16 can be applied in a wide va-
riety of master clock, sampling, and calibration
conditions which directly affect the devices’ con-
version time and throughput. The devices also
feature on-chip 3-state output buffers and a com-
plete interface for connecting to 8-bit and 16-bit
digital systems. Output data is also available in
serial format.
Master Clock
The CS5012A/14/16 operate from a master clock
(CLKIN) which can be externally supplied or in-
ternally generated. The internal oscillator is
activated by externally tying the CLKIN input
low. Alternatively, the CS5012A/14/16 can be
synchronized to the external system by driving
the CLKIN pin with a TTL or CMOS clock sig-
nal.
CLKIN
Master Clock
(Optional)
HOLD
EOT
CS5012A/14/16
Figure 3b. Synchronous Sampling
CLKIN
Master Clock
(Optional)
HOLD
Sampling
Clock
CS5012A/14/16
Figure 3a. Asynchronous Sampling
CS5012A, CS5014, CS5016
2-18 DS14F6
All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16’s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD in-
put (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional con-
version cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gat-
ing the devices’ decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16’s base address will initiate a
conversion. However, the write cycle must be to
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS return-
ing high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 plac-
ing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16’s base address will initiate or ter-
minate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microproces-
sor data bus.
Conversion Time/Throughput
Upon completing a conversion cycle and return-
ing to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25 µs (1.32 µs for the CS5012A -7 version
only). This adds to the conversion time to define
the converter’s maximum throughput. The con-
version time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
HOLD
CS5012A/14/16
Addr
Dec
A3
AN
Address
Bus
WR
RD
CS
RD
INTRLV
A2
A1
CAL
A0
A0
ADDR VALID
Figure 4b. Conversions under M icroprocessor Control
CS5012A/14/16
CS
Addr
Dec
A3
AN
Address
Bus
RDRD
CONCLK HOLD
INTRLV
CAL
A0
A2
A1
A0
ADDR VALID
Figure 4a. Conversions Asynchronous to CLKIN
CS5012A, CS5014, CS5016
DS14F6 2-19
Asynchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
CLKIN (fCLK/4). If sampling is not synchronized
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clo ck cycles add to the mini-
mum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maxi-
mum conversion time (see Figure 5a and
Table 1).
Synchronous Sampling
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) out-
put to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the ana-
log input has been acquired to the
CS5012A/14/16’s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization un-
certainty is removed yielding throughput at
[1/64]fCLK for the CS5012A, [1/72]fCLK for
CS5014 and [1/80]fCLK for CS5016 where fCLK
is the CLKIN frequency (see Figure 5b and Ta-
ble 1).
*
Conversion
(49 + N cycles)
1 / Throughput
(64 + N cycles)
Output
EOT
Output
EOC
Input
HOLD
Acquisition
(15 cycles)
*Dashed li ne: C S & RD = 0 CS50 12A N = 0
Solid line: See Figure 9 CS5014 N = 8
CS50 16 N = 16
Figure 5b. Synchronous (Loopback Mode)
Conversion
Synchronization Uncertainty (4 cycles)
Input
Output
Output
Acquisition
HOLD
EOC
EOT
1 / Throughput
Figure 5a. Asynchronous Sampling (External Clock)
Throughput TimeConversion Time
Sampling Mode
Synchronous (Loopback)
Asynchronous
Min
64 tclk
N/A
N/A
Max
64 tclk
59 1.32
µ
s
tclk+
59 2.25
µ
s
tclk+
Max
+ 235 ns53 tclk
49 tclk
+ 235 ns53 tclk
Min
49 tclk
49 tclk
49 tclk
-7
-12,-24
CS5012A
CS5014
57 tclk
57 tclk + 235 ns61 tclk
57 tclk 72 tclk
N/A
72 tclk
67 2.25
µ
s
tclk+
Synchronous (Loopback)
Asynchronous
65 tclk
65 tclk + 235 ns69 tclk
65 tclk 80 tclk
N/A
80 tclk
75 2.25
µ
s
tclk+
Synchronous (Loopback)
Asynchronous
CS5016
Table 1. Conversion and Throug hput Times (tclk = Master Clock Period)
CS5012A, CS5014, CS5016
2-20 DS14F6
Also, the CS5012A/14/16’s internal RC oscillator
exhibits jitter (typically ± 0.05% of its period),
which is high compared to crystal oscillators. If
the CS5012A/14/16 is configured for synchro-
nous sampling while operating from its internal
oscillator, this jitter will directly affect sampling
purity. The user can obtain best sampling purity
while synchronously sampling by using an exter-
nal crystal-based clock.
Reset
Upon power up, the CS5012A/14/16 must be re-
set to guarantee a consistent starting condition
and initially calibrate the devices. Due to the
CS5012A/14/16’s low power dissipation and low
temperature drift, no warm-up time is required
before reset to accommodate any self-heating ef-
fects. However, the voltage reference input
should have stabilized to within 5%, 1% or
0.25% of its final value, for the CS5012A/14/16
respectively, before RST falls to guarantee an ac-
curate calibration. Later, the CS5012A/14/16 may
be reset at any time to initiate a single full cali-
bration. Reset overrides all other functions. If
reset, the CS5012A/14/16 will clear and initiate a
new calibration cycle mid-conversion or mid-cali-
bration.
Resets can be initiated in hardware or software.
The simplest method of resetting the
CS5012A/14/16 involves strobing the RST pin
high for at least 100 ns. When RST is brought
high all internal logic clears. When it returns low,
a full calibration begins which takes 58,280
CLKIN cycles for the CS5012A (approximately
9.1 ms with a 6.4 MHz clock) and 1,441,020
CLKIN cycles for the CS5016, CS5014 and
CS5012 (approximately 360 ms with a 4 MHz
CLKIN). A simple power-on reset circuit can be
built using a resistor and capacitor, and a
Schmitt-trigger inverter to prevent oscillation (see
Figure 6). The CS5012A/14/16 can also be reset
in software when under microprocessor control.
The CS5012A/14/16 will reset whenever CS, A0,
and HOLD are taken low simultaneously. See the
Microprocessor Interface section (below) to
eliminate the possibility of inadvertent software
reset. The EOC output remains high throughout
the calibration operation and will fall upon its
completion. It can thus be used to generate an
interrupt indicating the CS5012A/14/16 is ready
for operation. While calibrating, the HOLD input
is ignored until EOC falls. After EOC falls, six
CLKIN cycles plus 2.25 µs (1.32 µs for the
CS5012A -7 version only) must be allowed for
signal acquisition before HOLD is activated. Un-
der microprocessor-independent operation (CS,
RD low; A0 high) the CS5014’s and CS5016’s
EOC output will not fall at the completion of the
calibration cycle, but EOT will fall 15 CLKIN
cycles later.
Initiating Calibration
All modes of calibration can be controlled in
hardware or software. Accuracy can thereby be
insured at any time or temperature through ou t op-
erating life. After initial calibration at power-up,
the CS5012A/14/16’s charge-redistribution design
yields better temperature drift and more graceful
aging than resistor-based technologies, so calibra-
tion is normally only required once, after
power-up.
The first mode of calibration, reset, results in a
single full calibration cycle. The second type of
calibration, "burst" cal, allows control of partial
calibration cycles. Due to an unforeseen con-
didtion inside the part, asynchronous termination
of calibration may result in a sub-optimal result.
Burst cal should not be used.
C
R
+5V
RST
CS5012A/14/16
Figure 6. Pow er-on Reset Circ uit
CS5012A, CS5014, CS5016
DS14F6 2-21
The reset calibration always works perfectly, and
should be used instead of burst mode. The
CS5012’s and CS5012A/14/16’s very low drift
over temperature means that, under most circum-
stances, calibration will only need to be
performed at power-up, using reset.
The CS5012A/14/16 feature a background cali-
bration mode called "interleave." Interleave
appends a single calibration experiment to each
conversion cycle and thus requires no dead time
for calibration. The CS5012A/14/16 gathers data
between conversions and will adjust its transfer
function once it completes the entire sequence of
experiments (one calibration cycle per 2,014 con-
versions in the CS5012A and one calibration per
72,051 conversions in the CS5012, CS5014 and
CS5016). Initiated by bringing both the INTRLV
input and CS low (or hard-wiring INTRLV low),
interleave extends the CS5012A/14/16’s effective
conversion time by 20 CLKIN cycles. Other than
reduced throughput, interleave is totally transpar-
ent to the user. Interleave calibration should not
be used intermittently.
The fact that the CS5012A/14/16 offer several
calibration modes is not to imply that the devices
need to be recalibrated often. The devices are
very stable in the presence of large temperature
changes. Tests have indicated that after using a
single reset calibration at 25 °C most devices ex-
hibit very little change in offset or gain when
exposed to temperatures from -55 to +125 °C.
The data indicated 30 ppm as the typical worst
case total change in offset or gain over this tem-
perature range. Differential linearity remained
virtually unchanged. System error sources outside
of the A/D converter, whether due to changes in
temperature or to long-term aging, will generally
dominate total system error.
Microprocessor Interface
The CS5012A/14/16 feature an intelligent micro-
processor interface which offers detailed status
information and allows software control of the
self-calibration functions. Output data is available
in either 8-bit or 16-bit formats for easy interfac-
ing to industry-standard microprocessors.
Strobing both CS and RD low enables the
CS5012A/14/16’s 3-state output buffers with
either output data or status information depending
on the status of A0. An address bit can be con-
nected to A0 as shown in Figure 4b thereby
memory mapping the status register and output
data. Conversion status can be polled in software
by reading the status register (CS and RD strobed
low with A0 low), and masking status bits S0-S5
and S7 (by logically AND’ing the status word
with 01000000) to determine the value of S6.
Similarly, the software routine can determine
calibration status using other status bits (see Ta-
ble 2). Care must be taken not to read the status
register (A0 low) while HOLD is low, or a soft-
ware reset will result (see Reset above ).
Alternatively, the End-of-Convert (EOC) output
can be used to generate an interrupt or drive a
DMA controller to dump the output directly into
memory after each conversion. The EOC pin falls
as each conversion cycle is completed and data is
valid at the output. It returns high within four
CLKIN cycles of the first subsequent data read
operation or after the start of a new conversion
cycle.
CS5012A, CS5014, CS5016
2-22 DS14F6
To interface with a 16-bit data bus, the BW input
to the CS5012A/14/16 should be held high and
all data bits (12, 14 and 16 for the CS5012A,
CS5014 and CS5016 respectively) read in paral-
lel on pins D4-D15 (CS5012A), D2-D15
(CS5014), or D0-D15 (CS5016). With an 8-bit
bus, the converter’s result must be read in two
portions. In this instance, BW should be held low
and the 8 MSB’s obtained on the first read cycle
following a conversion. The second read cycle
will yield the remaining LSB’s (4, 6 or 8 for the
CS5012A/14/16 respectively) with 4, 2 or 0 trail-
ing zeros. Both bytes appear on pins D0-D7. The
upper/lower bytes of the same data will continue
to toggle on subsequent reads until the next con-
version finishes. Status bit S2 indicates which
byte will appear on the next data read operation.
The CS5012A/14/16 internally buffer their output
data, so data can be read while the devices are
tracking or converting the next sample. Therefore,
retrieving the converters’ digital output requires
no reduction in ADC throughput. Enabling the 3-
state outputs while the CS5012A/14/16 is
converting will not introduce conversion errors.
Connecting CMOS logic to the digital outputs is
recommended. Suitable logic families include
4000B, 74HC, 74AC, 74ACT, and 74HCT.
PIN STATUS BIT STATUS DEFINITION
D0 S0 END OF CONV ERSION Fa lls up on com pletion of a conversio n,
and retur ns high on the first subsequent read.
D1 S1 RESERVED Reserved for factory use.
D2 S2 LOW BYTE/HIGH BY TE Wh en data is to be re ad in an 8-bi t form at (BW =0),
indica tes w hich byte will a ppear at the output next.
D3 S3 END OF TRACK When low, indicates the input has been acquired to
the devices specified accuracy.
D4 S4 RESERVED Reserved for factory use.
D5 S5 TRACKING High when the device is tracking the input.
D6 S6 CONV ERTIN G High w hen the device is c onverting the h eld input.
D7 S7 CALIB RATING High whe n the dev ice is cal ibrating .
Table 2. Status Pin Definitions
D7 D0D5 D3 D2 D1D6 D4D12 D11 D10 D9 D8D15 D14 D13
XXXXX XX X S7 S6 S5 S4 S3 S2 S1 S0 8- or 16-Bit
Data Bus
Data
(A0=1)
Status
(A0=0)
"X" Denotes High Impedance Output
XXXXX XXX
8-Bit Bus
(BW=0)
16-Bit Bus
(BW=1)
B5 B4B11 B10 B7 B6B8B9
CS5012A
CS5014
CS5016 B13 B11 B9 B7 B6
B12 B10 B8
B5 B4B11 B10 B7 B6B8B9
B15 B13 B11 B9 B8
B14 B12 B10
B3 B2 B1 B0 0 000
B5 B4 B3 B2 0 0B1 B0
B7 B6 B5 B4 B1 B0B3 B2
B3 B2 B1 B0 0 000
XXXXX XXX B7 B6B13 B12 B9 B8B10B11
B5 B4 B3 B2 0 0B1 B0
XXXXX XXX B9 B8B15 B14 B11 B10B12B13
B7 B6 B5 B4 B1 B0B3 B2
CS5016
CS5014
CS5012A
Figure 7. CS5012A/14/16 Data Format
CS5012A, CS5014, CS5016
DS14F6 2-23
Microprocessor Independent Operation
The CS5012A/14/16 can be operated in a stand-
alone mode independent of intelligent control. In
this mode, CS and RD are hard-wired low. This
permanently enables the 3-state output buffers
and allows transparent latch inputs (CAL and
INTRLV) to be active. A free-running condition
is established when BW is tied high, CAL is tied
low, and HOLD is continually strobed low or tied
to EOT. The CS5012A/14/16’s EOC output can
be used to externally latch the output data if de-
sired. With CS and RD hard-wired low, EOC will
strobe low for four CLKIN cycles after each con-
version. Data will be unstable up to 100 ns after
EOC falls, so it should be latched on the rising
edge of EOC.
Serial Output
All successive-approximation A/D converters de-
rive their digital output serially starting with the
MSB. The CS501 2A /14/16 present each bit to the
SDATA pin four CLKIN cycles after it is derived
and can be latched using the serial clock output,
SCLK. Just subsequent to each bit decision
SCLK will fall and return high once the bit infor-
mation on SDATA has stabilized. Thus, the rising
edge of the SCLK output should be used to clock
the data from the CS5012A/14/16 (See Figure 9).
ANALOG CIRCUIT CONNECTIONS
Most popular successive-approximation A/D con-
verters generate dynamic loads at their analog
connections. The CS5012A/14/16 internally buff-
er all analog inputs (AIN, VREF, and AGND) to
ease the demands placed on external circuitry.
However, accurate system operation still requires
careful attention to details at the design stage re-
garding source impedances as well as grounding
and decoupling schemes.
Reference Considerations
An application note titled "Voltage References for
the CS501X Series of A/D Converters" is avail-
able for the CS5012A/14/16. In addition to
working through a reference circuit design exam-
ple, it offers several built-and-tested reference
circuits.
During conversion, each capacitor of the cali-
brated capacitor array is switched between VREF
and AGND in a manner determined by the suc-
cessive-approximation algorithm. The charging
and discharging of the array results in a current
load at the reference. The CS5012A/14/16 in-
clude an internal buffer amplifier to minimize the
external reference circuit’s drive requirement and
preserve the reference’s integrity. Whenever the
array is switched during conversion, the buffer is
used to pre-charge the array thereby providing
the bulk of the necessary charge. The appropriate
array capacitors are then switched to the unbuf-
fered VREF pin to avoid any errors due to offsets
and/or noise in th e buffer.
The external reference circuitry need only pro-
vide the residual charge required to fully charge
the array after pre-charging from the buffer. This
creates an ac current load as the CS5012A/14/16
sequence through conversions. The reference cir-
cuitry must have a low enough output impedance
to drive the requisite current without changing its
output voltage significantly. As the analog input
signal varies, the switching sequence of the inter-
nal capacitor array changes. The current load on
the external reference circuitry thus varies in re-
sponse with the analog input. Therefore, the
external reference must not exhibit significant
BW
CAL
RST
Reset
A0
CS
HOLD
+5V
Sampling
Clock
RD
D4
D15
Data
Out
12-Bit
EOC
Latching
Output
INTRLV
CS5012A
CS5014
CS5016
Figure 8. Microprocessor-Independent Connections
CS5012A, CS5014, CS5016
2-24 DS14F6
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The magnitude of the current load on the external
reference circuitry will scale to the CLKIN fre-
quency. At full speed, the referen ce must supply a
maximum load current of 10
µA peak-to-peak
(1
µA typical). For the CS5012A an output im-
pedance of 15 Ω will therefore yield a maximum
error of 150 mV. With a 2.5V reference and LSB
size of 600 mV, this would insure better than 1/4
LSB accuracy. A 1 µF capacitor exhibits an im-
pedance of less than 15 Ω at frequencies greater
than 10 kHz. Similarly, for the CS5014 with a
4.5V reference (275µV/LSB), better than
1/4 LSB accuracy can be insured with an output
impedance of 4Ω or less (maximum error of
40 µV). A 2.2 µF capacitor exhibits an imped-
ance of less than 4Ω at frequencies greater than
5kHz. For the CS5016 with a 4.5V reference
(69µV/LSB), better than 1/4 LSB accuracy can
be insured with an output impedance of less than
2Ω (maximum error of 20 µV). A 20 µF capaci-
tor exhibits an impedance of less than 2Ω at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ce-
ramic capacitor is recommended.
CLKIN
EOC
Status
EOT
HOLD
SCLK
SDATA
t
d
t
d
Determined
LSB Fine Charge Determined
MSB
Determined
MSB - 1
Determined
MSB - 2
Coarse Cha rge
LSB+1 LSB MSB
MSB - 1
LSB+2
246
8
10 12646260 80/076 787472706866
CS5016:
246
8
10 125654 72/068 70666462605852
CS5014:
246
8
10 12484644 64/060 625856545250
CS5012A:
Figure 9. Serial Output Timing
Notes: 1. Synchronous (loopback) mode is illustrated. After EOC falls the converter goes into coarse charge mode for
6 CLKIN cycles, then to fine charge mode for 9 cycles, then EOT fal ls. In loop back mode, EOT trip s HOLD
which captures the analog sample. Conversion begins on the next rising edge of CLKIN. If operated asynchro-
nously, EOT will remain low until after HOLD is taken low. When HOLD occur s the analo g sam ple is captu red
immediately, but conversion may not begin until four C LKIN cycles later. EOT will return high
when co nversion begins.
2. Tim ing delay td (relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range
and over ± 10% sup ply variation
3. EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Micro processor Inde pendent Mode);
within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after HOLD = 0
is recognized on a rising edge of CLKIN/4.
CS5012A, CS5014, CS5016
DS14F6 2-25
Peaking in the reference’s output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capaci-
tors (Figure 10). The equation in Figure 10 can
be used to help calculate the optimum value of R
for a particular reference. The term "fpeak" is the
frequency of the peak in the output impedance of
the reference befo re th e resistor is added.
The CS5012A/14/16 can operate with a wide
range of reference voltages, but signal-to-noise
performance is maximized by using as wide a
signal range as possible. The recommended refer-
ence voltage is between 2.5 and 4.5 V for the
CS5012A and 4.5 V for the CS5014/16. The
CS5012A/14/16 can actually accept reference
voltages up to the positive analog supply. How-
ever, the buffer’s offset may increase as the
reference voltage approaches VA+ thereby in-
creasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer en-
lists the aid of an external 0.1
µF ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-. For
more information on references, consult the applica-
tion note: Voltage References for the CS501X Se-
ries of A/D Converters. For an example of using
the CS5012A/14/16 with a 5 volt reference, see
the application note: A Collection of Application
Hints for the CS501X Series of A/D Converters.
Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six CLKIN cycles in the track mode, the buffered
version of the analog input is used for pre-charg-
ing the capacitor array. An additional period is
required for fine-charging directly from AIN to
VREF
REFBUF
VA-
0.1
µ
F
-5V
R
29
28
30
ref
V
C1
1.0
µ
F
0.01
µ
F
C2
+V
ee
CS5012A
CS5014
CS5016
1
R= 2
π
(C1 + C2) fpeak
Figure 10. Reference Connectio ns
Internal Charge Error (LSB's)
Fine-ChargePre-Charge
Acquisition Time (us)
0.5 1.0 1.5 2.0 2.5
(Delay from EOC)
+12.5
0
-12.5
-25.0
+50
0
-50
-100
+200
0
-200
-400
CS5012ACS5014CS5016
Figure 11. Internal Acquisition Time
CS5012A, CS5014, CS5016
2-26 DS14F6
obtain the specified accuracy. Figure 11 illustrates
this operation. During pre-charge the charge on
the capacitor array first settles to the buffered ver-
sion of the analog input. This voltage is offset
from the actual input voltage. During fine-charge,
the charge then settles to the accurate unbuffered
version.
The acquisition time of the CS5012A/14/16 de-
pends on the CLKIN frequency. This is due to a
fixed pre-charge period. For instance, operating
the CS5012A -12, CS5014 -14 or CS5016 -16
version with an external 4 MHz CLKIN results in
a 3.75 µs acquisition time: 1.5 µs for pre-charging
(6 clock cycles) and 2.25
µs for fine-charging.
Fine-charge settling is specified as a maximum of
2.25 µs for an analog source impedance of less
than 200
Ω. (For the CS5012A -7 version it is
specified as 1.32 µs.) In addition, the comparator
requires a source impedance of less than 400
Ω
around 2 MHz for stability, which is met by prac-
tically all bipolar op amps. Large dc source
impedances can be accommodated by adding ca-
pacitance from AIN to ground (typically 200 pF)
to decrease source imp edance at high frequen cies.
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
essary acquisition time. For more information on
input applications, consult the application note:
Input Buffer Amplifiers for the CS501X Family of
A/D Converters.
During the first six clock cycles following a con-
version (pre-charge) in unipolar mode, the
CS5012A is capable of slewing at 20V/µs and the
CS5014/16 can slew at 5V/µs. In bipolar mode,
only half the capacitor array is connected to the
analog input so the CS5012A can slew at 40V/µs,
and the CS5014/16 can slew at 10V/µs. After the
first six CLKIN cycles, the CS5012A will slew at
1.25V/µs in unipolar mode and 3.0V/µs in bipolar
mode, and the CS5014/16 will slew at 0.25V/µs
in unipolar mode and 0.5V/µs in bipolar mode.
Acquisition of fast slewing signals (step func-
tions) can be hastened if the step occurs during or
immediately following the conversion cycle. For
instance, channel selection in multiplexed appli-
cations should occur while the CS5012A/14/16 is
converting (see Figure 12). Multiplexer settling is
thereby removed from the overall throughput
equation, and the CS5012A/14/16 can convert at
full speed.
Con vert Ch annel N+ 1Convert Channel N
Address N Address N + 1 Address N + 2 Address N + 3
EOC
Output
HOLD
Input
MUX
Address
MU X Sett ling
to Channel N + 2
Analog
Input
MU X Sett li n g
to Channel N + 1
CS5012A/14/16
CS5012A/14/16
CS5012A/14/16
Figure 12. Pipelined MUX Input Cha nnels
CS5012A, CS5014, CS5016
DS14F6 2-27
Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar
configurations. In the unipolar configuration
(BP/UP low), the first code transition occurs
0.5 LSB above AGND, and the final code transi-
tion occurs 1.5 LSB’s below VREF. Coding is in
straight binary format. In the bipolar configura-
tion (BP/UP high), the first code transition occurs
0.5 LSB above -VREF and the last transition oc-
curs 1.5 LSB’s below +VREF. Coding is in an
offset-binary format. Positive full scale gives a
digital output of all ones, and negative full scale
gives a digital o utput of all zeros.
The BP/UP mode pin may be switched after cali-
bration without having to recalibrate the
converter. However, the BP/UP mode should be
changed during the previous conversion cycle,
that is, between HOLD falling and EOC falling.
If BP/UP is changed at any other time, one
dummy conversion cycle must be allowed for
proper acquisition of the input.
Grounding and Power Supply Decoupling
The CS5012A/14/16 use the analog ground con-
nection, AGND, only as a reference voltage. No
dc power currents flow through the AGND con-
nection, and it is completely independent of
DGND. However, any noise riding on the AGND
input relative to the system’s analog ground will
induce conversion errors. Therefore, bo th the ana-
log input and reference voltage should be referred
to the AGND pin, which should be used as the
entire system’s analog ground reference point.
The digital and analog supplies to the
CS5012A/14/16 are pinned out separately to
minimize coupling between the analog and digital
sections of the chip. All four supplies should be
decoupled to their respective grounds using
0.1 µF ceramic capacitors. If significant low-fre-
quency noise is present on the supplies, 1 µF
tantalum capacitors are recommended in parallel
with the 0.1 µF capacitors.
The positive digital power supply of the
CS5012A/14/16 must never exceed the positive
analog supply by more than a diode drop or the
device could experience permanent damage. If
the two supplies are derived from separate
sources, care must be taken that the analog sup-
ply comes up first at power-up. The system
connection diagram in Figure 36 shows a decou-
pling scheme which allows the CS5012A/14/16
to be powered from a single set of ± 5V rails.
As with any high-precision A/D converter, the
CS5012A/14/16 require careful attention to
grounding and layout arrangements. However, no
unique layout issues must be addressed to prop-
erly apply the device. The CDB5012/14/16
evaluation board is available for the
CS5012A/14/16, which avoids the need to de-
sign, build, and debug a high-precision PC board
to initially characterize the part. The board comes
with a socketed CS5012A/14/16, and can be
quickly reconfigured to simulate any combination
of sampling, calibration, CLKIN, and analog in-
put range conditions.
CS5012A, CS5014, CS5016
2-28 DS14F6
Power Supply Rejection
The CS5012A/14/16’s power supply rejection
performance is enhanced by the on-chip self-cali-
bration and an "auto-zero" process. Drifts in
power supply voltages at frequencies less than the
calibration rate have negligible effect on the
CS5012A/14/16’s accuracy. This is because the
CS5012A/14/16 adjust their offset to within a
small fraction of an LSB during calibration.
Above the calibration frequency the excellent
power supply rejection of the internal amplifiers
is augmented by an auto-zero process. Any
offsets are stored on the capacitor array and are
effectively subtracted once conversion is initiated.
Figure 13 shows power supply rejection of the
CS5012A/14/16 in the bipolar mode with the
analog input grounded and a 300 mVp-p ripple
applied to each supply. Power supply rejection
improves by 6 dB in the unipolar mode.
The plot in Figure 13 shows worst-case rejection
for all combinations of conversion rates and input
conditions in the bipolar mode.
CS5012A/14/16 PERFORMANCE
Differential Nonlinearity
One source of nonlinearity in A/D converters is
bit weight errors. These errors arise from the de-
viation of bits from their ideal binary-weighted
ratios, and lead to nonideal widths for each code.
If DNL errors are large, and code widths shrink
to zero, it is possible for one or more codes to be
entirely missing. The CS5012A/14/16 calibrate
all bits in the capacitor array to a small fraction
of an LSB resulting in nearly ideal DNL. Histo-
gram plots of typical DNL of the CS5012A/14/16
can be seen in Figures 14, 16, 17. Figure 15 il-
lustrates the DNL of the CS5012 for comparison
with the CS5012A (Figure 14).
A histogram test is a statistical method of deriv-
ing an A/D converter’s differential nonlinearity. A
ramp is input to the A/D and a large number of
samples are taken to insure a high confidence
level in the test’s result. The number of occur-
rences for each code is monitored and stored. A
perfect A/D converter would have all codes of
equal size and therefore equal numbers of occur-
rences. In the histogram test a code with the
average number of occurrences will be consid-
ered ideal (DNL = 0). A code with more or less
occurrences than average will appear as a DNL
of greater or less than zero LSB. A missing code
has zero occurrences, and will appear as a DNL
of -1 LSB.
Integral Nonlinearity
Integral Nonlinearity (INL; also termed Relative
Accuracy or just Nonlinearity) is defined as the
deviation of the transfer function from an ideal
straight line. Bows in the transfer curve generate
harmonic distortion. The worst-case condition of
bit-weight errors (DNL) has traditionally also de-
fined the point of maximum INL.
Bit-weight errors have a drastic effect on a con-
verter’s ac performance. They can be analyzed as
step functions superimposed on the input signal.
Power Supply Ripple Frequency
1 kHz 10 kHz 100 kHz 1 MHz
Power Supply Rejection (dB)
90
80
70
60
50
40
30
20
Figure 13. Power Supply Rejection
CS5012A, CS5014, CS5016
DS14F6 2-29
04,095
Codes
2,048
DNL (LSB)
+1
0
-1
+1/2
-1/2
Figure 14. CS5012A Differential Nonlinearity Plot
04,095
Codes
2,048
DNL (LSB)
+1
0
-1
+1/2
-1/2
Figure 15. CS5012 Differential Nonlinearity Plot
016,383
Codes
8,192
DNL (LSB)
+1
0
-1
+1/2
-1/2
Figure 16. CS5014 Differential Nonlinearity Plot
065,535
Codes
32,768
DNL (LSB)
+1
0
-1
+1/2
-1/2
Figure 17. CS5016 Differential Nonlinearity Plot
CS5012A, CS5014, CS5016
2-30 DS14F6
Since bits (and their errors) switch in and out
throughout the transfer curve, their effect is sig-
nal dependent. That is, harmonic and
intermodulation distortion, as well as noise, can
vary with different input conditions. Designing a
system around characterization data is risky since
transfer curves can differ drastically unit-to-unit
and lot-to -lot.
The CS5012A/14/16 achieves repeatable signal-
to-noise and harmonic distortion performance
using an on-chip self-calibration scheme. The
CS5012A calibrates its bit weight errors to a
small fraction of an LSB at 12-bits yielding peak
distortion below the noise floor (see Figure 19).
The CS5014 calibrates its bit weights to within
±1/16 LSB at 14-bits (±0.0004% FS) yielding
peak distortion as low as -105 dB (see Fig-
ure 22). The CS5016 calibrates its bit weights to
within ±1/4 LSB at 16-bits (±0.0004% FS) yield-
ing peak distortion as low as -105 dB (see
Figure 24). Unlike traditional ADC’s, the linear-
ity of the CS5012A/14/16 are not limited by
bit-weight errors; their performance is therefore
extremely repeatable and independent of input
signal conditions.
Quantization Noise
The error due to quantization of the analog input
ultimately dictates the accuracy of any A/D con-
verter. The continuous analog input must be
represented by one of a finite number of digital
codes, so the best accuracy to which an analog
input can be known from its digital code is
±1/2 LSB. Under circumstances commonly en-
countered in signal processing applications, this
quantization error can be treated as a random
variable. The magnitude of the error is limited to
±1/2 LSB, but any value within this range has
equal probability of occurrence. Such a prob-
ability distribution leads to an error "signal" with
an rms value of 1 LSB/√12. Using an rms signal
value of FS/√8 (amplitude = FS/2), this relates to
ideal 12, 14 and 16-bit signal-to-noise ratios of
74, 86 and 98 dB respectively.
Equally important is the spectral content of this
error signal. It can be shown to be approximately
white, with its energy spread uniformly over the
band from dc to one-half the sampling rate. Ad-
vantage of this characteristic can be made by
judicious use of filtering. If the signal is ban-
dlimited, much of the quantization error can be
filtered out, and improved system performance
can be attained.
FFT Tests and Windowing
In the factory, the CS5012A/14/16 are tested us-
ing Fast Fourier Transform (FFT) techniques to
analyze the converter’s dynamic performance. A
pure sinewave is applied to the CS5012A/14/16,
and a "time record" of 1024 samples is captured
and processed. The FFT algorithm analyzes the
spectral content of the digital waveform and dis-
tributes its energy among 512 "frequency bins."
Assuming an ideal sinewave, distribution of en-
ergy in bins outside of the fundamental and dc
can only be due to quantization effects and errors
in the CS5012A/14/16.
If sampling is not synchronized to the input sine-
wave, it is highly unlikely that the time record
will contain an integer number of periods of the
input signal. However, the FFT assumes that the
signal is periodic, and will calculate the spectrum
of a signal that appears to have large discontinui-
ties, thereby yielding a severely distorted
spectrum. To avoid this problem, the time record
is multiplied by a window function prior to per-
forming the FFT. The window function smoothly
forces the endpoints of the time record to zero,
thereby removing the discontinuities. The effect
of the window in the frequency-domain is to con-
volute the spectrum of the window with that of
the actual inpu t.
Figure 18 shows an FFT computed from an ideal
12-bit sinewave. The quality of the window used
for harmonic analysis is typically judged by its
highest side-lobe level. The Blackman-Harris
window used for testing the CS5014 and CS5016
has a maximum side-lobe level of -92 dB. Fig-
CS5012A, CS5014, CS5016
DS14F6 2-31
ures 21 and 23 show FFT plots computed from
an ideal 14 and 16-bit sinewave multiplied by a
Blackman-Harris window. Artifacts of window-
ing are discarded from the signal-to-noise
calculation using the assumption that quantization
noise is white. All FFT plots in this data sheet
were derived by averaging the FFT results from
ten 1024 point time records. This filters the spec-
tral variability that can arise from capturing finite
time records without disturbing the total energy
outside the fun damen tal. All harmonics which ex-
ist above the noise floor and the -92 dB
side-lobes from the Blackman-Harris window are
therefore clearly visible in the plots. For more in-
formation on FFT’s and windowing refer to: F.J.
HARRIS, "On the use of windows for harmonic
dc 50.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0 Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 72.9dB
Input Frequency (kHz)
12.0
Signal
Amplitude
Relative to
Full Scale
(dB)
Figure 20 . FFT Plot of CS 5012A with 12 kH z
Full-Scale Input
dc
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Input Frequency
Signal
Amplitude
Relative to
Full Scale
(dB)
S/N+D: 73.9 dB
f /2
s
Figure 18. Plo t of Ideal 12-bit ADC
dc 50.0
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
Input Frequency (kHz)
1.0
Signal
Amplitude
Relative to
Full Scale
(dB)
Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 73.6dB
Figure 19. Plot of CS5012A with 1 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 28 kHz1 kHz
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 85.3 dB
Input Frequency
Figure 22. CS5014 FFT plot with 1 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
S/(N+D): 86.1 dB
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB f /2
s
Figure 21. Plot of Ideal 14-bit ADC
CS5012A, CS5014, CS5016
2-32 DS14F6
analysis with the Discrete Fourier Transform",
Proc. IEEE, Vol. 66, No. 1, Jan 1978, pp.51-83.
This is available on request from Crystal Semi-
conductor.
Figures 19, 22, and 24 show the performance of
the CS5012A/14/16 with 1kHz full scale inputs.
Figure 20 shows CS5012A performance with
12kHz full scale inputs. Notice that the perform-
ance CS5012A/14/16 closely approaches that of
the corresponding ideal ADC.
CS5012A High Frequency Performance
The CS5012A performs very well over a wide
range of input frequencies as shown in Figure 25.
The figure depicts the CS5012A-KP7 tested un-
der four different conditions. The conditions
include tests with the voltage reference set at 4.5
and at 2.5 volts with input signals at 0.5 dB down
from full scale and 6.0 dB down from full scale.
The sample rate is at 100 kHz for all cases. The
plots indicate that the part performs very well
even with input frequencies above the Nyquist
rate. Best performance at the higher frequencies
is achieved with a 2.5 volt reference.
020 40 60 80 100 120 140 160 180 200
55
60
65
70
75
Signal to
Noise +
Distortion
Input Frequency (kHz)
/2
fsfs
CS5012A-KP7 fs=100 kHz
2
1
3
4
4.5
2.5
4.5
2.5
FS-0.5dB
FS-0.5dB
FS-6.0dB
FS-6.0dB
1.
2.
3.
4.
VREF Signal
(dB)
Figure 25. CS5012A High Frequency Input Performance
Signal
Amplitude
Relative to
Full Scale
dc
Input Frequency
S/(N+D): 97.5 dB
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
f /2
s
Figure 23. Plo t of Ideal 16-bit ADC
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
25 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 92.4 dB
1 kHz
Figure 24. CS5016 FFT plot with 1 kHz
Full Scale Input
CS5012A, CS5014, CS5016
DS14F6 2-33
Signal to Noise + Distortion vs Signal Level
As illustrated in Figures 26 - 2 9, the CS5014/16’s
on-chip self-calibration provides very accurate bit
weights which yield no degradation in quantiza-
tion noise with low-level input signals. In fact,
quantization noise remains below the noise floor
in the CS5016, which dictates the converter’s sig-
nal-to-noise performance.
CS5016 Noise Considerations
All analog circuitry in the CS5016 is wideband in
order to achieve fast conversions and high
throughput. Wideband noise in the CS5016 inte-
grates to 35 µV rms in unipolar mode (70 µV rms
in bipolar mode). This is approximately 1/2 LSB
rms with a 4.5V reference in both modes. Figure
30 shows a histogram plot of output code occur-
rences obtained from 5000 samples taken from a
CS5016 in the bipolar mode. Hexadecimal code
80CD was arbitrarily selected and the analog in-
put was set close to code center. With a noiseless
converter, code 80CD would always appear. The
histogram plot of the CS5016 has a "bell" shape
with all codes other than 80CD due to internal
noise.
In a sampled data system all information about the
analog input applied to the sample/hold appears in
the baseband from dc to one-half the sampling rate.
This includes high-frequency components which
alias into the baseband. Low-pass (anti-alias) filters
Analog Input Amplitude
-100 dB -80 dB -60 dB -40 dB -20 dB 0 dB
100 dB
80 dB
60 dB
40 dB
20 dB
0 dB
S(N+D)
1 kHz
12 kHz
24 kHz
Input
Frequencies
Figure 26. CS5014 S/(N +D) v s. Input Amplitude
(9Vp-p Full-Scale Input)
Analog Input Amplitude
-100 dB -80 dB -60 dB -40 dB -20 dB 0 dB
100 dB
80 dB
60 dB
40 dB
20 dB
0 dB
S(N+D)
1 kHz
12 kHz
24 kHz
Input
Frequency
Figure 28. CS5016 S/(N +D) v s. Input Amplitude
(9Vp-p Full-Scale Input)
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 28 kHz1 kHz
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 24.1 dB
Figure 27. CS5014 FFT plot with 1 kHz
-60 dB Input
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
25 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 9.6 dB
1 kHz
Figure 29. CS5016 FFT plot with 1 kHz
-80 dB Input
CS5012A, CS5014, CS5016
2-34 DS14F6
are therefore used to remove frequency compo-
nents in the input signal which are above one-half
the sample rate. However, all wideband noise in-
troduced by the CS5016 still aliases into the
baseband. This "white" noise is evenly spread
from dc to one-half the sampling rate and inte-
grates to 35 µV rms in un ipolar mode.
Noise can be reduced by sampling at higher than
the desired word rate and averaging multiple
samples for each word. Oversampling spreads the
CS5016’s noise over a wider band (for lower
noise density), and averaging applies a low-pass
response which filters noise above the desired
signal bandwidth. In general, the CS5016’s noise
performance can be maximized in any application
by always sampling at the maximum specified
rate of 50 kHz (for lowest noise density) and
digitally filtering to the desired signal bandwidth.
CS5014 and CS5016 Sampling Distortion
The ultimate limitation on the CS5014/16’s
linearity (and distortion) arises from nonideal
sampling of the analog input voltage. The cali-
brated capacitor array used during conversions is
also used to track and hold the analog input sig-
nal. The conversion is not performed on the
analog input voltage per se, but is actually per-
formed on the charge trapped on the capacitor ar-
ray at the moment the HOLD command is given.
The charge on the array is ideally related to the
analog input voltage by Qin = -Vin x C
tot as
shown in Figure 2. Any deviation from this ideal
relationship will result in conversion errors even
if the conversion process proceeds flawlessly.
At dc, the DAC capacitor array’s voltage coeffi-
cient dictates the converter’s linearity. This
variation in capacitance with respect to applied
signal voltage yields a nonlinear relationship be-
tween charge Qin and the analog input voltage
Vin and places a bow or wave in the transfer
function. This is the dominant source of distor-
tion at low input frequencies (Figures 22 and 24).
The ideal relationship between Qin and Vin can
also be distorted at high signal frequencies due to
nonlinearities in the internal MOS switches. Dy-
namic signals cause ac current to flow through
the switches connecting the capacitor array to the
analog input pin in the track mode. Nonlinear on-
resistance in the switches causes a nonlinear
voltage drop. This effect worsens with increased
signal frequency as shown in Figures 26 and 28
since the magnitude of the steady state current in-
creases. First noticeable at 1 kHz, this distortion
assumes a linear relationship with input fre-
quency. With signals 20 dB or more below
full-scale, it no longer dominates the converter’s
overall S/(N+D) performance (Figures 31-34).
This distortion is strictly an ac sampling phe-
nomenon. If significant energy exists at high
frequencies, the effect can be eliminated using an
external track-and-hold amplifier to allow the ar-
ray’s charge current to decay, thereby eliminating
any voltage drop across the switches. Since the
CS5014/16 has a second sampling function on-
chip, the external track-and-hold can return to the
track mode once the converter’s HOLD input
falls. It need only acquire the analog input by the
time the entire conversion cycle finishes.
Code (Hexadecimal)
Counts: 0 11 911 3470 599 9 0
80CB 80CC 80CD 80CF 80D080CE80CA
1000
2000
3000
4000
5000
Count
Noiseless
CS5016
Converter
Figure 30. Hist ogram Plot of 5000 C onversion
Inputs from the CS5016
CS5012A, CS5014, CS5016
DS14F6 2-35
Clock Feedthrough in the CS5014 and CS5016
Maintaining the integrity of analog signals in the
presence of digital switching noise is a difficult
problem. The CS5014/16 can be synchronized to
the digital system using the CLKIN input to
avoid conversion errors due to asynchronous in-
terference. However, digital interference will still
affect sampling purity due to coupling between
the CS5014/16’s analog input and master clock.
The effect of clock feedthrough depends on the
sampling conditions. If the sampling signal at the
HOLD input is synchronized to the master clock,
clock feedthrough will appear as a dc offset at the
CS5014/16’s output. The offset could theoreti-
cally reach the peak coupling magnitude
(Figure 35), but the probability of this occurring
is small since the peaks are spikes of short dura-
tion.
If sampling is performed asynchronously with the
master clock, clock feedthrough will appear as an
ac error at the CS5014/16’s output. With a fixed
Analog Input
Source Impedance
200
25
50
50
50
4MHz
2MHz
Master Clock Clock Feedthrough
Int/Ext Freq
Internal
External
External
External
External
2MHz
4MHz
4MHz
RMS Peak-to-Peak
15uV
25uV
40uV
25uV
80uV
70uV
110uV
150uV
110uV
325uV
Figure 35. Examples of Measured Clock Feedthrough
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 28 kHz
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 81.5 dB
12 kHz
Figure 31. CS5014 FFT plot with 12 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 25 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 84.3 dB
12 kHz
Figure 33. CS5016 FFT plot with 12 kHz
Full Scale Input
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 25 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 71.9 dB
12 kHz
Figure 34. CS5016 FFT plot with 12 kHz
-20 dB Input
Signal
Amplitude
Relative to
Full Scale
dc Input Frequency
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB 28 kHz
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 64.6 dB
12 kHz
Figure 32. CS5014 FFT plot with 12 kHz
-20 dB Input
CS5012A, CS5014, CS5016
2-36 DS14F6
sampling rate, a tone will appear as the clock fre-
quency aliases into the baseband. The tone
frequency can be calculated using the equation
below and could be selectively filtered in soft-
ware using DSP techniques.
ftone = (N fs - fclk)
where N = fclk/fs rounded to the nearest integer
The magnitude of clock feedthrough depends on
the master clock conditions and the source im-
pedance applied to the analog input. When
operating with the CS5014/16’s internally gener-
ated clock, the CLKIN input is grounded and the
dominant source of coupling is through the de-
vice’s substrate. As shown in Figure 35, a typical
CS5014/16 operating with their internal oscillator
at 2 MHz and 50 Ω of analog input source im-
pedance will exhibit only 15 µV rms of clock
feedthrough. However, if a 2 MHz external clock
is applied to CLKIN under the same conditions,
feedthrough increases to 25 µV rms. Feedthrough
also i ncreases with clock frequency; a 4 MHz
clock yields 40 µV rms.
Clock feedthrough can be reduced by limiting the
source impedance applied at the analog input. As
shown in Figure 35, reducing source impedance
from 50 Ω to 25 Ω yields a 15 µV rms reduction
in feedthrough. Therefore, when operating the
CS5014/16 with high-frequency external master
clocks, it is important to minimize source imped-
ance applied to the CS5014/16’s input.
Also, the overall effect of clock feedthrough can
be minimized by maximizing the input range and
LSB size. The reference voltage applied to VREF
can be maximized, and the CS5014/16 can be op-
erated in bipolar mode which inherently doubles
the LSB size over the unipolar mode.
Differences between the CS5012A and the
CS5012
The differences between the CS5012A and the
CS5012 are tabulated in Table 3. The CS5012 is
a short-cycled version of the CS5016 A/D con-
verter and includes the same 18-bit calibration
circuitry. This calibration circuitry sets the cali-
bration resolution of the CS5012 at 1/64th of an
LSB and achieves the near perfect differential
linearity performance illustrated by the CS5012
DNL plot in Figure 15. The CS5012A calibration
circuitry was modified to provide calibration to
15-bit resolution therefore achieving calibration
to 1/8 of an LSB. This reduction in calibration
resolution for the CS5012A reduces the time re-
quired to calibrate the device (see Table 3) and
reduces the size of the total array capacitance.
The reduced array capacitance improves the high
frequency performance by allowing higher slew
rate in the input circuitry.
Table 3 documents some other improvements in-
cluded in the CS5012A. The burst mode
calibration was made functional, although it
should not be used. The device was also modified
so the EOC signal goes low at the end of a reset
calibration in either microprocessor or microproc-
essor-independent mode. The CS5012A was
modified to maintain a throughput rate of 64
CLKIN cycles in loopback mode for all frequen-
cies of CLKIN.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Call:(512) 445-7222
CS5012A, CS5014, CS5016
DS14F6 2-37
Calibration resolution
Calibration time
reset:
interleave:
burst:
End of calibration
indicator
Throughput rate in
loopback mode
Input capacitance
in fine-charge mode
CS5012
18 bits. Results in DNL calibration
to 1/64 LSB at 12 bits.
1,441,020 CLKIN cycles
72,051 conversions
not functional
EOC falls at the completion of a RESET
calibration cycle in microprocessor mode
only. In microprocessor-independent mode
cycles after completion of a RESET calibration.
The device acquires and converts in 64
CLKIN cycles for CLKIN=4MHz, but will
require 68 CLKIN cycles at 100kHz through-
put. This is due to excess delay on
275pF typical, unipolar mode
CS5012A
15 bits. Results in DNL calibration
to 1/8 LSB at 12 bits.
58,280 CLKIN cycles
2,014 conversions
fully functional
EOC falls in either microprocessor
or microprocessor-independent
mode at the completion of a RESET
calibration cycle.
The device acquires and converts
a sample in 64 CLKIN cycles for all
CLKIN frequencies when in loopback.
103pF typical, unipolar mode
EOT must be used.
EOT.
Slew Rate
Unipolar
Coarse charge
Fine charge
Bipolar
Coarse charge
Fine charge
falls 15 CLKINEOT
20V/us
1.5V/us
40V/us
3.0V/us
5V/us
0.25V/us
10V/us
0.5V/us
72pF typical, bipolar mode 165pF typical, bipolar mode
Table 3. Differences Between the CS5012A and CS5012
CS5012A, CS5014, CS5016
2-38 DS14F6
Figure 36. CS50 12A/14/16 System Co nnection Dia gram
26
28
29
30
25
27
11
10
36
VREF
AIN
REFBUF
VA-
AGND
VA+ VD+
DGND
VD-
+5V
-5V
10
Ω
10
Ω
Voltage
Reference
Reset
Generator
Data
Processor
Serial
Data
Interface
(optional)
Clock
Source
(optional)
Control
Logic
Mode
Select *
Analog
Supply
Source
Signal
Analog
Supply
Analog
TST
BW
RESET
A0
CAL
D0-D15
SCLK
SDATA
CLKIN
24
33
20
40
39
8 or 16
38
37
1
35
34
21
22
23
32
31
0.1
µ
F
0.01
µ
F
0.1
µ
F0.1
µ
F
May be
microprocessor
or discrete logic.
0.1
µ
F
INTRLV
EOC
EOT
HOLD
BP/UP
RD
CS
0.1
µ
F
CS5012A
or
VREF
±VREF
0
10
µ
F
Signal
Conditioning
1000 pF
200
Ω
CS5014
CS5016
Unused Logic inputs should only
be connect ed to VD+ or DGND.
* BW and BP/ UP should always
be terminated to VD+ or DGND,
For b est dynam ic
S/(N+D) performance.
or driven by a logic gate.
Function
RSTA0CAL Hold and Start Convert
Initiate Burst Calibration
Stop Burst Cal and Begin Track
Initiate Interleave Calibration
Terminate Interleave Cal
Read Output Data
Read Status Register
High Impedance Data Bus
High Impedance Data Bus
Reset
Reset
0
0
0
0
0
0
0
X
X
1
X
*
*
*
*
*
1
0
*
*
X
0
X
X
X
X
X
0
0
X
1
X
X
X
X
X
0
1
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
1
X
X
0
X
1
X
X
X
1
X
X
X
0
HOLD CS INTRLV RD
Table 4. CS5012A/14/16 Truth Table
*The status of A0 is n ot critical to the operation sp ecified. However, A0 should not be low with
CS and HOLD low, or a software reset will result.
CS5012A, CS5014, CS5016
DS14F6 2-39
HOLD HOLD SDATA SERIAL OUTPUT
CS5016 (LSB) DATA BUS BIT 0 D0 SCLK SERIAL CLOCK
DATA BUS BIT 1 D1 EOC END OF CONVERSION
CS5014 (LSB) DATA BUS BIT 2 D2 EOT END OF TRACK
DATA BUS BIT 3 D3 VD- NEGATIVE DIGITAL POW ER
CS5012 (LSB ) DATA BUS BIT 4 D4 CAL CALIBRATE
DATA BUS BIT 5 D5 INTRLV INTERLEAVE
DATA BUS BIT 6 D6 BW BUS WIDTH SELECT
DATA BUS BIT 7 D7 RST RESET
DIGITAL GROUND DGND TST TEST
POSITIVE DIGITAL POWER VD+ VA- NEGATI VE ANALOG PO WER
DATA BUS BIT 8 D8 REFBUF REFERENCE BUFFER OUTPUT
DATA BUS BIT 9 D9 VREF VOLTAGE REFERENCE
DATA BUS BIT 10 D10 AGND ANALOG GROUND
DATA BUS BIT 11 D11 AIN ANALOG INPUT
DATA BUS BIT 12 D12 VA+ POSITIVE ANALOG POWE R
DATA BUS BIT 13 D13 BP/UP BIPOLAR/UNIPOLAR SELECT
DATA BUS BIT 14 D14 A0 READ ADDRES S
(MSB) DATA BUS BIT 15 D15 RD READ
CLOCK INPUT CLKIN CS CHIP SELECT
HOLD
D0 SDATA
D1 SCLK
D2 EOC
D3 EOT
D4 VD-
D5 CAL
D6 INTRLV
NC BW
D7 RST
DGND TST
VD+ VA-
NC NC
D8 REFBUF
NC VREF
D9 AGND
D10 AIN
D11 VA+
D12 BP/UP
D13 A0
D14 RD
D15 CS
CLKIN
CS5012A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CS5012
CS5014
CS5016
top
view
18 20 22 24 26 28
1246404244
12
8
10
14
16
7
9
11
13
15
17 29
31
33
35
37
39
34
30
32
36
38
CS5012A
CS5012
CS5014
CS5016
NOTE: All pin references in this data sheet refer to the 40-pin DIP pack age nu mbering.
Use this fig ure to determine p in numbers for 44-pin package.
CS5012A, CS5014, CS5016
2-40 DS14F6
PIN DESCRIPTIONS
Power Supply Connections
VD+ – Positive Digital Power, PIN 11.
Positive digital power supply. Nominally +5 volts.
VD- – Negative Digital Power, PIN 36.
Negative digital power supply. Nominally -5 volts.
DGND – Digital Ground, PIN 10.
Digital ground.
VA+ – Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- – Negative Analog Power, PIN 30.
Negative analog power supply. Nominally -5 volts.
AGND – Analog Ground, PIN 27.
Analog ground.
Oscillator
CLKIN – Clock Input, PIN 20.
All conversions and calibrations are timed from a master clock which can either be supplied by
driving this pin with an external clock signal, or can be internally generated by tying this pin to
DGND.
Digital Inputs
HOLD – Hold, PIN 1.
A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion.
This input must remain low at least one CLKIN cycle plus 50 ns.
CS – Chip Select, PIN 21.
When high, the data bus outputs are held in a high impedance state and the input to CAL and
INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration
(depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and
INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0.
RD – Read, PIN 22.
When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data
bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW
and A0.
CS5012A, CS5014, CS5016
DS14F6 2-41
A0 – Read Address, PIN 23.
Determines whether data or status information is placed onto the data bus. When high during the
read operation, converted data is placed onto the data bus; when low, the status register is driven
onto the bus.
BP/UP – Bipolar/Unipolar Input Select, PIN 24.
When high, the device is configured with a bipolar transfer function ranging from -VREF to
+VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at
AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF.
Unipolar encoding is in straight binary format. Once calibration has been performed, eith er bipolar
or unipolar mode may be selected without the need to recalibrate.
RST – Reset, PIN 32.
When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full
calibration sequence is initiated.
BW – Bus Width Select, PIN 33.
When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read
cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the
eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing
zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s
status, a read cycl e wi th A0 low yields the status information on D0-D7.
INTRLV – Interleave, PIN 34.
When latched low using CS, the device goes into interleave calibration mode. A full calibration
will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the
CS5014/16. The effective conversion time extends by 20 clock cycles.
CAL – Calibrate, PIN 35. (See Addendum appending this data sheet))
When latched high using CS, burst calibration results. The device cannot perform conversions
during the calibration period which will terminate only once CAL is latched low again.
Calibration picks up where the previous calibration left off, and calibration cycles complete every
58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If
the device is converting when a calibration is signaled, it will wait until that conversion completes
before beginning.
Analog Inputs
AIN – Analog Input, PIN 26.
Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to
+VREF. The output impedance of buffer driving this input should be less than or equal to 200 Ω.
CS5012A, CS5014, CS5016
2-42 DS14F6
VREF – Voltage Reference, PIN 28.
The analog reference voltage which sets the analog input range. It represents positive full scale for
both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode.
Digital Outputs
D0 through D15 – Data Bus Outputs, PINS 2 thru 9, 12 thru 19.
3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format
consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data.
EOT – End Of Track, PIN 37.
If low, indicates that enough time has elapsed since the last conversion for the device to acquire
the analog input signal.
EOC – End Of Conversion, PIN 38.
This output indicates the end of a conversion or calibration cycle. It is high during a conversion
and will fall to a low state upon completion of the conversion cycle indicating valid data is
available at the output. Returns high on the first subsequent read or the start of a new conversion
cycle.
SDATA – Serial Output, PIN 40.
Presents each output data bit after it is determined by the successive approximation algorithm.
Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid
until the next bit appears.
SCLK – Serial Clock Output, PIN 39.
Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the
rising edge of SCLK.
Analog Outputs
REFBUF – Reference Buffer Output, PIN 29.
Reference buffer output. A 0.1 µF cerami c capacitor must be tied between this pin and VA-.
Miscellaneous
TST – Test, PIN 31.
Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be
tied to DGND.
CS5012A, CS5014, CS5016
DS14F6 2-43
PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB
below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units in %
Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full Scale Error
The deviation of the last code transitio n from the ideal (VRE F-3/2 LSB’s).
Units in LSB’s.
Unipolar Offset
The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in
unipolar mode (BP/UP low). Units in LSB’s.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 LSB below
AGND) wh en in bipolar mode (BP/UP high). Units in LSB’s.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The
ideal is defined as lying on a straight line which passes through the final and mid-scale code
transitions. Units in LSB’s.
Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise)
The ratio of the rms value of the signal to the rms value of the next largest spectral component
below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the
signal frequency is a significant proportion of the sampling rate. E xpressed in d ecibels.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.
Signal-to-Noise Ratio
The ratio of the rms value of the signal to the rms sum of all other spectral components below
the Nyquist rate (excepting dc), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a
sampling delay w hich can be nulled by advancing th e sampling signal. Un its in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the "sampling window" which ultimately
dictates the maximum input signal slew rate acceptable for a given accuracy. Units in
picoseconds.
NOTE: Tempera ture s specified defin e amb ient conditions in free-air during test and do not refer to the junction
temp erature of th e devic e.
CS5012A, CS5014, CS5016
2-44 DS14F6
CS5012A Ordering Guide
Model Thr oughput Con version Time Maximum DNL T emp. Range Package
CS5012A-KP12 63 kHz 12.25 µs±1/2 LSB 0 to 70 °C 40-Pin Plastic DIP
CS5012A-KP7 100 kHz 7.20µs±1/2 LSB 0 to 70 °C 40-Pin Plastic DIP
CS5012A-KL12 63 kHz 12.25 µs±1/2 LSB 0 to 70 °C 44-Pin PLCC
CS5012A-KL7 100 kHz 7.20 µs±1/2 LSB 0 to 70 °C 44-Pin PLCC
CS5012A-BP12 63 kHz 12.25 µs±1/2 LSB -40 to +85 °C 40-Pin Plastic DIP
CS5012A-BP7 100 kHz 7.20 µs±1/2 LSB -40 to +85 °C 40-Pin Plastic DIP
CS5012A-BL12 63 kHz 12.25 µs±1/2 LSB -40 to +85 °C 44-Pin PLCC
CS5012A-BL7 100 kHz 7.20 µs±1/2 LSB -40 to +85 °C 44-Pin P LCC
5962-8967901QA 63 kHz 12.25 µs±1/2 LSB -55 to +125 °C 40-Pin CerDIP
5962-8967901XA 63 kHz 12.25 µs±1/2 LSB -55 to +125 °C 44-Pin Ceramic LCC
The CS5012A is recommended for new designs. The following is a list of upgraded par t numbers.
Discontinued Equivalent
Par t Number Recommended Device.
CS5012-KP24 CS5012A-KP12
CS5012-KP12 CS5012A-KP12
CS5012-KP7 CS5012A-KP7
CS5012-KL24 CS5012A-KL12
CS5012-KL12 CS5012A-KL12
CS5012-KL7 CS5012A-KL7
CS5012-BD24 CS5012A-BP12
CS5012-BD12 CS5012A-BP12
CS5012-BD7 CS5012A-BP7
CS5012-BL24 CS5012A-BL12
CS5012-BL12 CS5012A-BL12
CS5012-BL7 CS5012A-BL7
CS5012-TD24B 5962-897901QA
CS5012-TD12B 5962-897901QA
CS5012-TE24B 5962-897901XA
CS5012-TE12B 5962-897901XA
CS5012A, CS5014, CS5016
DS14F6 2-45
AS PER EOL MAY 22, 2000
CURRENT PRODUCT REPLACEMENT
BEING OBSOLETED PRODUCT
CS5012A -KP12 40 pin DIP CS5012A -BP7
CS5012A -KP7 40 pin DIP CS5012A -BP7
CS5012A -BP12 40 pin DIP CS5012A -BP7
CS5012A -KL12 44 pin PLCC CS5012A -BL7
CS5012A -KL7 44 pin PLCC CS5012A -BL7
CS5012A -BL12 44 pin PLCC CS5012A -BL7
CS5014 Ordering Guide
Model Thr oughput Con version Time Linearity T emp. Range Pac kage
CS5014-KP28 28 kHz 28.50 µs±0.5 LSB 0 to 70 °C 40-Pin Plastic DIP
CS5014-KP14 56 kHz 14.25 µs±0.5 LSB 0 to 70 °C 40-Pin Plastic DIP
CS5014-KL28 28 kHz 28.50 µs±0.5 LSB 0 to 70 °C 44-Pin PLCC
CS5014-KL14 56 kHz 14.25 µs±0.5 LSB 0 to 70 °C 44-Pin PLCC
CS5014-BP28 28 kHz 28.50 µs±0.5 LSB -40 to +85 °C 40-Pin Plastic DIP
CS5014-BP14 56 kHz 14.25µs ±0.5 LSB -40 to +85 °C 40-Pin Plastic DIP
CS5014-BL28 28 kHz 28.50 µs±0.5 LSB -40 to +85 °C 44-Pin PLCC
CS5014-BL14 56 kHz 14.25 µs±0.5 LSB -40 to +85 °C 44-Pin PLCC
CS5014-SD14 56 kHz 14.25 µs±1.5 LSB -55 to +125 °C 40-P in CerDIP
CS5014-TD14 56 kHz 14.25 µs±0.5 LSB -55 to +125 °C 40-Pin CerDIP
CS5014-SE14 56 kHz 14.25 µs±1.5 LSB -55 to +125 °C 44-Pin Ceramic LCC
CS5014-TE14 56 kHz 14.25 µs±0.5 LSB -55 to +125 °C 44-Pin Ceramic LCC
5962-8967401QA 56 kHz 14.25 µs±1.5 LS B -55 to + 125 °C 40-Pin CerDIP
5962-8967402QA 56 kHz 14.25 µs±0.5 LSB -55 to +125 °C 40-Pin CerDIP
5962-8967401XA 56 kH z 14.25 µs±1.5 LSB -55 to +125 °C 44-Pin Ceramic LCC
5962-8967402XA 56 kH z 14.25 µs±0.5 LSB -55 to +125 °C 44-Pin Ceramic LCC
The following is a list of upgraded par t numbers.
Disc ontinued E quivalent
Par t Number Recommended Device
CS5014-SD14B 5962-8967401QA
CS5014-TD14B 5962-8967402QA
CS5014-SE14B 5962-8967401XA
CS5014-TE14B 5962-8967402XA
CS5012A, CS5014, CS5016
2-46 DS14F6
AS PER EOL MAY 22, 2000
CURRENT PRODUCT REPLACEMENT
BEING OBSOLETED PRODUCT
CS5014 -KP28 40 pin DIP CS5014 -BP14
CS5014 -KP14 40 pin DIP CS5014 -BP14
CS5014 -BP28 40 pin DIP CS5014 -BP14
CS5014 -KL28 44 pin PLCC CS5014 -BL14
CS5014 -KL14 44 pin PLCC CS5014 -BL14
CS5014 -BL28 44 pin PLCC CS5014 -BL14
CS5016 Ordering Guide Signal to
Model Linearity Noise Ratio Con version Time T emp. Range Pac kage
CS5016-JP32 .0030% 87 dB 32.50 µs 0 to 70 °C 40-Pin Plastic DIP
CS5016-JP16 .0030% 87 dB 16.25 µs 0 to 70 °C 40-Pin Plastic DIP
CS5016-KP32 .0015% 90 dB 32.50 µs 0 to 70 °C 40-Pin Plastic DIP
CS5016-KP16 .0015% 90 dB 16.25 µs 0 to 70 °C 40-Pin Plastic DIP
CS5016-JL32 .0030% 87 dB 32.50 µs 0 to 70 °C 44-Pin PLCC
CS5016-JL16 .0030% 87 dB 16.25 µs 0 to 70 °C 44-Pin PLCC
CS5016-KL32 .0015% 90 dB 32.50 µs 0 to 70 °C 44-Pin PLCC
CS5016-KL16 .0015% 90 dB 16.25 µs 0 to 70 °C 44-Pin PLCC
CS5016-AP32 .0030% 87 dB 32.50 µs -40 to +85 °C 40-Pin Plastic DIP
CS5016-AP16 .0030% 87 dB 16.25 µs -40 to +85 °C 40-Pin Plastic DIP
CS5016-BP32 .0015% 90 dB 32.50 µs -40 to +85 °C 40-Pin Plastic DIP
CS5016-BP16 .0015% 90 dB 16.25 µs -40 to +85 °C 40-Pin Plastic DIP
CS5016-AL32 .0030% 87 dB 32.50 µs -40 to +85 °C 44-Pin PLCC
CS5016-AL16 .0030% 87 dB 16.25 µs -40 to +85 °C 44-Pin PLCC
CS5016-BL32 .0015% 90 dB 32.50 µs -40 to +85 °C 44-Pin PLCC
CS5016-BL16 .0015% 90 dB 16.25 µs -40 to +85 °C 44-Pin PLCC
CS5016-SD16 .0076% 87 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP
CS5016-TD16 .0015% 90 dB 16.25 µs -55 to +125 °C 40-Pin CerDIP
CS5016-SE16 .0076% 87 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC
CS5016-TE16 .0015% 90 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC
5962-8967601QA .0076% 87 dB 16.25 µs -55 to +125 °C 40-P in CerDIP
5962-8967602QA .0015% 90 dB 16.25 µs -55 to +125 °C 40-P in CerDIP
5962-8967601XA .0076% 87 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC
5962-8967602XA .0015% 90 dB 16.25 µs -55 to +125 °C 44-Pin Ceramic LCC
The following i s a list of upgraded p ar t numbers.
Discontinued Equivalent
Pa rt Num ber Recomme nded Device
CS5016-SD16B 5962-8967601QA
CS5016-TD16B 5962-8967602QA
CS5016-SE16B 5962-8967601XA
CS5016-TE16B 5962-8967602XA
CS5012A, CS5014, CS5016
DS14F6 2-47
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
D
B
A
L
C
13.72
51.69
1.02
0.36
0.51
3.94
3.18
0.20
0°
2.41
15.24
14.22
52.71
1.65
0.56
1.02
5.08
3.81
0.38
15°
0.540
2.035
0.095
0.040
0.014
0.020
0.155
0.125
0.600
0.008
0°
0.560
2.075
0.065
0.022
0.040
0.200
0.150
0.015
15°
40 pin
Plastic DIP
1
40 21
20
15.87 0.625
E1
D
B
SEATING
PLANE
A
B1 e1
A1 LC
eA
∝∝
2.67
0.105
∝∝
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
NOM
13.97
52.20
1.27
0.46
0.76
4.32
-
0.25
-
2.54
-
NOM
0.550
2.055
0.100
0.050
0.018
0.030
0.170
-
-
0.010
-
A1
B1
E1
e1
eA
E
E1
D1
D
D2/E2
44 pin
PLCC
NO. OF TERMINALS
D2/E2
MAXMIN MAXMIN
MILLIMETERS INCHES
DIM
A
D/E
17.6517.40 0.685
B
e
A
A1
Be
0.695
16.6616.51 0.650 0.656
4.574.20 0.1800.165
0.530.33 0.0210.013
2.29 0.090
16.0014.99 0.590 0.630
1.19 1.35 0.047 0.053
NOM
17.53
16.59
4.45
0.41
2.79
15.50
1.27
NOM
0.690
0.653
0.175
0.016
0.110
0.610
0.050
3.04 0.120
D1/E1
A1
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
40 pin
CerDIP
1
40 21
20
E1
D
B
SEATING
PLANE
A
B1 e1 A1 LC
eA
∝∝
0.46
0.25
52.32
14.73
2.54
15.24
3.81
0.018
0.010
2.060
0.580
0.100
0.600
0.150
12.70
50.29
1.27
0.38
0.51
4.06
2.92
0.20
5°
2.41
15.11
15.37
52.57
1.65
0.56
1.27
5.84
4.06
0.30
15°
15.37
2.67 0.500
1.980
0.095
0.050
0.015
0.020
0.160
0.115
0.595
0.008
5°
0.605
2.070
0.065
0.022
0.050
0.230
0.160
0.012
15°
0.605
0.105
MILLIMETERS INCHES
DIM MIN MAX MIN
E1
D
e1
B1
B
A1
A
L
eA
C
∝∝
NOM NOM
MAX
28 44
NO. OF TERMINALS
MAXMIN MAXMINMAXMIN MAXMIN
MILLIMETERS MILLIMETERSINCHES INCHES
DIM
A
3.432.54 0.1350.100 3.432.54 0.1350.100
B
0.580.33 0.0230.013 0.580.33 0.0230.013
0.810.51 0.0320.02
B1
0.810.51 0.0320.02
D2
1
E1
Top View
D1
E
D
28/44 pin
CLCC
A
B
B1
e1
D4/E4
NOM
3.05
0.46
NOM
0.120
0.018
NOM
3.05
0.46
NOM
0.120
0.018
E2
D/E
0.6600.64016.26 16.76
17.78 0.70017.27 0.68012.19 12.70
11.18 11.68
0.480 0.500
0.440 0.460
e1
1.401.14 0.0550.045 1.401.14 0.0550.045
D2/E2
0.5050.49512.57 12.837.49 7.75 0.295 0.305
D4/E4
0.6350.62515.88 16.1310.80 11.05 0.425 0.435
12.46
11.43
1.27
7.62
10.92
0.490
0.450
0.050
0.300
0.430
16.51
17.53
1.27
12.70
16.00
0.650
0.690
0.050
0.500
0.630
0.64 0.025 0.64 0.025
D1/E1
Smart
Analog
TM is a Trademark of Crystal Semiconductor Corporation
