1 of 10
FEATURES
10 years minimu m data r et ent io n in the
absence o f exter na l po w er
Dat a is automatically pro tect ed d uring power
loss
Rep laces 128k x 8 vo lat ile static RAM,
EEPROM or Flash memory
Unlim ited write c ycles
Low-po wer CMOS
Read and wr it e access times of 100ns
Lit h iu m energy so u r ce is elect ricall y
d iscon nect ed to retain fres hness unt il power is
applied for the first time
Optional indust r ial t e mperat ure r ange of
-40°C to +85°C, designated IND
JEDEC standard 32-pin DIP package
Power Cap Modu le (PCM) packag e
- D ir ect ly sur face-mountable mo dule
- Rep laceab le snap-on Po werCap provides
lit hiu m backup bat ter y
- Standardized pino ut for all non volatile
SRAM products
- Det ach ment featur e o n Po w erCap a llows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A16 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip Enable
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+3.3V)
GND - Ground
NC - No Connect
DS1245W
3.3V 1024k Nonvolatile SRAM
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
11
12
14
31
32-PIN Encapsulated Package
740-Mil Extended
A14
A7
A5
A4
A3
A2
A1
A0
DQ1
DQ0
VCC
A15
NC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ5
DQ6
32
30
29
28
27
26
25
24
23
22
21
19
20
A16
A12
A6
NC
DQ2
GND
15
16
18
17
DQ4
DQ3
1
NC
2
3
A15
A16
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A14
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
34
NC
GND
V
BAT
34-Pin PowerCap Module (PCM)
(Uses DS9034PC+ or DS9034PCI+ PowerCap)
19-5640; Rev 11/10
DS1245W
2 of 10
DESCRIPTION
The DS1245W 3.3V 1024k Nonvolatile SRAM is a 1,048,576-bit, fully static, nonvolatile SRAM
organized as 131,072 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
c on tr ol c irc uitry whi c h c ons ta n tl y mon itor s VCC fo r an out-of-toler a nc e c o nd itio n. Whe n s uch a cond ition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enab led to pr event data corruption . DIP-package DS 1245W devices can be us ed in place of existing 128k
x 8 stat ic RAMs direct ly confor ming to the popula r bytew ide 32-pin DIP standard. DS1245W devices in
t he Power Cap Mod ule p ackage ar e d ir ect ly sur fac e mo unt able and are nor mally p aired wit h a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be execut ed and no additio nal supp ort cir cuitry is required for microp r ocesso r interfac ing.
READ MODE
The DS1245W executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Ena ble ) and
OE
(Output Enable) are active (low). The unique address specified by the 17 address inputs
(A0 - A16) de fines which of the 131,0 72 bytes of data is to be accessed. Valid data will be a vailable t o t he
e ig ht dat a out put dr ivers w it hin t ACC (Access T ime) after the last address input sig nal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
sat isfied, t he n dat a acces s must be measur ed fro m t he lat er o ccurr ing s ignal (
CE
or
OE
) a nd t he l imit ing
parameter is either tCO for
CE
or tOE for
OE
rather than address access.
WRITE MODE
The DS1245W executes a write cycle whenever the
WE
and
CE
signals are active (low) after address
input s are stab le. The lat er occu r r ing fa ll ing edge of
CE
or
WE
w ill det ermine the st ar t o f the wr ite c ycle.
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during write
c ycle s t o a void bus co ntent io n. H oweve r, if t he o ut put driver s ar e e nabled (
CE
and
OE
ac tive) t he n
WE
will dis ab le the outp uts i n tODW from its fall ing edge.
DATA RETENTION MODE
The DS1245W provides full fu nctional capabilit y fo r VCC great er t han 3.0 vo lt s and wr ite pr ot ect s by 2.8
vo lt s. Dat a is ma inta ined in t he abse nce o f VCC w ithout any add itio nal suppor t circuit ry. The nonvo latile
static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically
writ e protect t he mselve s, all input s become “don’t car e, ” and a l l o utputs become h ig h i mpeda nc e. As VCC
falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when VCC rises above approximately 2.5 volts, the power
switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal
RAM op er ation can resu me after VCC exceeds 3.0 vol ts.
FRESH NESS SEAL
Each DS1245 W device is shipped fro m Maxim wit h its l ithium energ y so ur ce disco nn ected , gu ar ant eeing
fu ll e ne r g y c ap acity. Whe n VCC is fir st a pplie d at a le ve l g r ea t e r t ha n 3 . 0 volt s, the lith iu m e ner gy s o ur ce
is enabled for bat tery back-up o peration.
PACKAGES
The DS1245W is available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
DS1245W
3 of 10
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1245W PCM
device to be surface mounted without subjecting its lithium backup battery to destructive high-
t emp erat ure r eflo w so lder ing. After a DS1245W modu le base is re flow soldered, a DS90 34PC PowerCap
is snapped o n top of the base to for m a co mplete No nvo latile SRAM mo dule. T he DS9034PC is keyed t o
prevent impro per att achment. DS1245W mo dule bases and DS9034PC Po werCaps are ordered separately
and shipped in separate containers. See the DS90 34P C data sheet for furt her informat ion.
DS1245W
4 of 10
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +4. 6V
Operating Te mperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
Stor ag e T emperat ur e Range
EDIP -40°C to +85°C
PowerCap -55°C to +125°C
Lead Temperature ( soldering, 10s) +260°C
Soldering Temper ature (reflow, PowerCap) +260°C
Note: EDIP is wave or hand soldered o nly.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Po wer Supply Voltage VCC 3.0 3.3 3.6 V
Logic 1 VIH 2.2 VCC V
Logic 0 VIL 0.0 0.4 V
DC ELECTRICAL CHARACTERISTICS (tA: See Note 10) (VCC=3.3V
0.3V)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -1.0 +1.0 µA
I/O Leakage Cu r r ent
CE
≥ VIH ≤ VCC IIO -1.0 +1.0 µA
Output Current @ 2.2V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Current
CE
=2.2V ICCS1 50 250 µA
St andby Current
CE
=VCC-0.2V ICCS2 30 150 µA
Operating Current ICCO1 50 mA
Writ e P r otect ion Voltage VTP 2.8 2.9 3.0 V
CAPACITANCE
(tA=25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
I nput/O utput C a pacit a nce CI/O 5 10 pF
DS1245W
5 of 10
AC ELECTRICAL CHARACTERISTICS (TA: See Note 10) (VCC = 3.3V ±0.3V)
PARAMETER SYMBOL DS1245W-100 UNITS NOTES
MIN MAX
Read Cyc le Time tRC 100 ns
Access Time tACC 100 ns
OE
to O utp ut Valid tOE 50 ns
CE
to O utp ut Valid tCO 100 ns
OE
or
CE
to O utp ut Active tCOE 5 ns 5
Out put High Z from Deselection tOD 35 ns 5
Output Hold from Address Change tOH 5 ns
Write Cycle Time tWC 100 ns
Writ e P ulse Width tWP 75 ns 3
A ddress Setup Time tAW 0 ns
Writ e Recover y Ti me tWR1
tWR2
5
20 ns
ns 12
13
Outpu t High Z f rom
WE
tODW 35 ns 5
Output Active from
WE
tOEW 5 ns 5
Da ta Setu p Time tDS 40 ns 4
Da ta Hold Time tDH1
tDH2
0
20 ns
ns 12
13
READ CYCLE
DS1245W
6 of 10
WRITE CYCLE 1
\SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
DS1245W
7 of 10
WRITE CYCLE 2
\SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
POWER-DOWN/POWER-UP CONDITION
DS1245W
8 of 10
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC slew from VTP to 0V tF 150 15 ms
VCC slew from 0V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Pr otection tREC 125 ms
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Ret ent io n T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH dur ing wr it e cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
go ing lo w t o t he ear lier o f
CE
or
WE
go ing h ig h.
4. tDH, tDS are measur ed from the ear lier of
CE
or
WE
go ing h ig h.
5. T hese para met er s ar e samp led w ith a 5 pF load and are not 100% t ested.
6. I f the
CE
low transitio n occurs simu lta neously wit h o r latter t han the
WE
low t ransit ion, the o utput
buffer s remain in a high impedance state during thi s per iod.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high impedance st ate during t his period.
8. If
WE
is low or the
WE
lo w t ra ns ition o cc ur s pr ior t o o r s imu lt ane o u s l y w it h t he
CE
lo w t ra ns ition ,
t he output buffers remain in a high impeda nce state during this period.
9. Each DS1245W has a built-in sw it ch t hat d isco nnect s t he lit hiu m so ur ce u nt il VCC is fir st app lied b y
the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the
t ime power is first applied by the user.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For indu strial product s (IND), this range is -40°C t o
+85°C.
11. In a power-dow n c onditio n the volt a ge on a ny p i n may not e xc ee d the volt age on VCC.
12. tWR1 and tDH1 are measur ed fro m
WE
go ing h ig h.
13. tWR2 and tDH2 are measur ed fro m
CE
go ing h ig h.
14. DS1245 modules are reco gnized by Underwrit ers Laborator ies (UL) under file E 99151.
DS1245W
9 of 10
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200ns for operating current Input P ulse Levels: 0 to 2.7V
All voltages are refer enced to grou nd Timing Measurement Referen ce Le vels
Input: 1.5V
Output : 1.5V
Input pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-
PACKAGE
SPEED GRADE
(ns)
DS1245W-100+
0°C to +70°C
3.3V ± 0.3V
32 740 EDIP
100
DS1245WP-100+
0°C to +70°C
3.3V ± 0.3V
34 PowerCap*
100
DS1245W-100IND+
-40°C to +85°C
3.3V
±
0.3V
32 740 EDIP
100
DS1245WP-100IND+
-40°C to +85°C
3.3V ± 0.3V
34 PowerCap*
100
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (Pow erCap) required. Must be order e d s e parately.
PACKAGE INFORMATION
For the latest package outline information a nd land patterns, go to www.maxim-ic.com/packages. N ote that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr awing pertains to t he p ackage re gardless of RoHS sta tus.
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
32 EDIP MDT32+6 21-0245 —
34 PCAP PC2+3 21-0246 —
DS1245W
10 of 10
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
121907
Added the Package Information table; remov ed th e DIP module
package drawing and dimension t able
8
11/10
Updated t he storage informat ion, sold ering temperature, and lead
t emperat ur e info rmatio n in the Absolute Maximum Ratings section;
r emo ved the -150 M IN /M AX i n form a tion fr om th e AC Electrical
Characteristics table; updated the Ordering Inf ormation table
(removed -150 part s and leaded -100 parts); removed the Power Cap
module drawings and updated the Package Information table
1, 4, 5, 9
