3CN00577BA - Alcatel Optronics

Description

These SERDE S Tra n sc eiv er s a re

intended to be used at 10 Gbit/s

optical SDH and SONET bit rate and

provide electrical accesses at lower

622 Mbit/s bit rat e. The m odules are

housed in a space-saving 300-p in

package, p r o v i d i n g the same electr i c a l

access for overall applications. The

transmitter side contains an in-house

cooled EA-ILM laser with a laser driver

and temperature control loop. The

transmit path starts with 16 : 1

serializer Asic. The receiver contains an

in-house III-V PIN detector with

preamplifier in a front-end module, a

main amplifier Asic, a clock and data

recovery function with accurate

decision circuit. The receive path ends

with 1 : 16 deserializer Asic. The

Alcatel 1964 TRX family is a range of

SERDE S t r a n sc ei v er s m o dules,

providing convenient and flexible

opti c a l i n t er fa c es fo r SD H / SO N E T

systems operating at 9.95 Gbit/s or

10.709 Gbit/s and exceed t h e

applicable ITU- T G. 691, Telcord ia

GR-253-ed.3 and Op t ical I nt erworking

Forum OIF99.102 stand a rd s.

Features

• New International Standard

• Multisource Optical Interfaces

• Upward compatibility with the

different features

• Applications:

Short-Reach or Intra-Office (25 km)

and Intermediate-Reach or Short-

Haul (40 km)

• Optical 9.95 Gbit/s rat e or 10. 709

Gbit/s rate (FEC)

• Electrical 622 Mbit/s rate or 669

Mbit/s rate (FEC)

• Operating at 1.5 µm wavelength

• Full performance in operating case

temperature from - 5 to + 65 °C

• Space-sa v in g package : 3.5 inch x 4

inch (8.9 cm x 10.16 cm)

• Alcatel Reliability and Qualification

Program for built in quality

Transmitter:

• EA-ILM 1.5µ cooled laser

• Up to +2 dBm optical output

• 16x2 input dat a 622 Mb it /s LVDS

• 1x2 ref. clock 155 or 622 MHz PECL

compatible

• Shut down command

• Analog monitoring

• Digital alarms

• Power supplies: +5 V, - 5 V & + 3.3 V

• Power consumption: 4.2 W typical

Receiver:

• InGaAs PIN-preamp detector

• High typical sensitivity - 15 dBm

• 16x2 output data 622 Mbit/s LVDS

• 1x2 ref. clock 155 MHz PECL

compatible

• Analog monitoring

• Digital alarms

• Power supplies: +5 V, - 5 V & + 3.3 V

• Power consumption: 2.8 W typical

Applications

Used in transm ission syst em s from

high-speed for intermediate-reach to

long-reach applications, the

Alcatel 1900 TRX family operates at

SONET OC-192 rates as well as at

ITU-T SDH STM-64 rates. Covering all

types of SDH / SONET optical

interfa ces (trib u t a r i es a n d a g gregat es)

the Alcatel 1900 TRX mod u les are

suitable for line syst em s, Ad d Drop

Multiplexers and digital cross-connects

as well as ATM or IP switches and

routers.

As part of the global Alcat el 1900 TRX

family, the Alcatel 1964 TRX Short-

Haul module is the first version for all

types of STM-64 (Intra-office, Short-

Haul and Long-Haul) and OC-192

(Short-Reach, Intermediate-Reach and

Long-Reach) optical interfaces. These

modules en su re ease of u se and offer

new flexibility to get 10 Gbit/s optical

links to system designers.

lcatel 1964 T R

SDH / SONET integrated modules

SERDES Transceiver (Transponder) STM-64 / OC-192

Optical characteristics

Condition Symb Min Typ Max Min Typ Max Unit

I-64.2 / SR-2 S-64.2b / IR-2

Target distance Note 1 25 40 Km

Optical budget Note 1 0 7 3 11 dB

Dispersion Note 1 500 800 ps/nm

Path penalty 2 2 dB

Transmitter

Center wavelength λc 1530 1550 1565 1530 1550 1565 nm

Optical output power Note 3 SNOM - 5 - 1 - 1 + 2 dBm

Spect r a l w i dth Note 4 ∆λ 11nm

SMSR 30 30 dB

Extinction ratio Note 5 Er 8.2 8.2 dB

Shutdown optical power SIDLE -50 -40 -50 -40 dBm

Generated jitter Note 2 0.1 0.1 UIpp

Return loss 24 24 dB

Receiver

Receiver sensitivity Note 6 RNOM - 14 - 15 - 14 - 15 dBm

Receiver overload Note 6 RNOM - 1 - 1 dBm

Generated jitter Note 2 0.1 0.1 UIpp

Reflectance - 27 - 27 dB

Note 1: Optical budgets are defined based on Telcordia GR-253-ed.3 & ITU-T G.691.

Note 2: From 50 kHz to 80 MHz bandwidth and no jitter on TxREFCLK.

Note 3: Measured at connector interface.

Note 4: The maximum full width of the central wavelength peak; measu red 20 dB down fr om the maximum amplitude

under modulation condition NRZ at 9.95328 Gbit/s and PRBS 223-1.

Note 5: Measured at connector interface under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1.

Note 6: Measured at BER 10-12 and under modulation conditions NRZ at 9.95328 Gbit/s and PRBS 223-1

All parameters are specified End-of-Life within the overall relevant operating temperature range.

The typical values are referenced to + 25 °C, nominal power supply, beginning of life.

Electrical characteristics

Parameter Condition Symbol Min Typical Max Unit

Negative supply voltage VEE - 4.94 - 5.2 - 5.45 V

Negative supply current IEE 900 1300 mA

1st Positive supply voltage VDD 3.13 3.3 3.47 V

1st Positive supply current IDD 760 2000 mA

2nd Positive supply voltage VCC 4.75 5.0 5.25 V

2nd Positive supply current ICC 130 200 mA

Power dissipation Total 7.0 14 W

Common mode LVDS input voltage LVDSVI 800 1700 mV

Differential LVDS input swing LVDSVIDTH 100 1000 mV

LVDS output differential voltage Note 7 LVDSVOD 250 600 mVpp

LVDS differential input impedance LVDSRIN 80 120 Ω

LVTTL input low voltage LVTTLVIL 00.8V

LVTTL input high voltage LVTTLVIH 2.0 3.3 V

LVTTL input low current VIN = 0.5 V LVTTLIIL -500 µA

LVTTL input high current VIN = 2.4 V LVTTLIIH 50 µA

LVTTL output low voltage IOL = 4 mA LVTTLVOL 0.4 V

LVTTL output high voltage IOH = -100 µA LVTTLVOH 2.4 V

LVPECL differential input voltage swing Note 8 LVPECL VDIF 300 930 mV

Note 7: Peak to peak single ended voltage.

Note 8: Internally AC coupled

All parameters are specified End-of-Life within the overall relevant operating temperature range. The typical values are

referenced to + 2 5 °C, nominal power supply, beginning of life.

Outline drawing

Framer to Transceiver clocking Clocking definition

TxREFCLK Transmitter Reference Clock Input:

Differential clock PECL compatible

input, internally AC coupled with 50

Ω terminated.

TxDin Transmitter Parallel Data Input:

Differential 622 Mbit/s LVDS input,

internally 100 Ω differential

terminated.

TxPICLK Transmitter Reference Parallel Clock

Input: Differential clock LVDS input,

internally 100 Ω differential

terminated.

TxPCLK Transmitter Reference Parallel Clock

Output: Differential clock LVDS

output.

TxMCLK Transmitter Monitor Clock: LVDS

clock output signal. This signal

represents the synthesized frequency

of the serializer.

RxDout Receiver Parallel Data Output:

Differential 622 Mbit/s LVDS output.

RxPOCLK Receiver Reference Par allel Clock

Output: Differential clock LVDS

output.

RxMCLK Receiver Monitor Clock: Differential

LVDS output signal. This signal

represents the PLL VC0 clock.

RxREFCLK Receiver Reference Clock Input:

Differential clock PECL compatible

input.

SONET Framer OC192 SERDES

TxREFCLK

TxDin

TxPICLK

TxPCLK

RxDout

RxPOCLK

RxREFCLK

xMCLK

RxMCLK

Pin out from customer line card

Receiver pin description

RxDout##P Receiver NRZ Data Output

Positive: 622 Mbit/s LVDS

output signal. D ata are

synchronized at the output of

the module with the ou tput

clock RxPOCLK signal.

RxDou t15 is the most significant

bit and first bit received.

RxDout##N Receiver NRZ Data Output

Negative: 622 Mbit/s LVDS

output signal. D ata are

synchronized at the output of

the module with the ou tput

clock RxPOCLK signal.

RxDou t15 is the most significant

bit and first bit received.

RxPOCLKP Receiver Parallel Ou tput Clock

Positive: 622 MHz LVDS output.

Regenerated clock synchroniz ed

to the data. The falling edge of

RxPOCLKP is in the middle of

the data pattern.

RxPOCLKN Receiver Parallel Ou tput Clock

Negative: 622 MHz output

signal. Regenerated clock

synchronized to the data. The

rising edge of RxPOCLKN is in

the middle of the data pattern.

RxREFCLKP Receiver Reference Clock

Positive: 155 MHz PECL,

compatible, internally AC

coupled 50 Ω terminated.

RxREFCLKN Receiver Reference Clock

Negative: 155 MHz PECL ,

compatible, internally AC

coupled 50 Ω terminated.

RxMCLKP Receiver Monitor Cloc k P ositiv e:

622 MHz LVDS output signal.

This signal represents the

PLL VC0 clock.

RxMCLKN Receiver Monitor Output Clock

Negative: 622 MHz LVDS

output signal. This signal

represents the PLL VC0 clock.

RxLCKREF Receiver Lock Clock Reference:

LVTTL input command. Selects

the reference frequency mode

of RxPOCLK. When is at logic

low, the RxPOCLK is forced to

lock to the RxREFCLK. When at

logic high, the RxPOCL K is

locked to the CDR reference

clock.

RxRESE T Receiver deserializer RESET:

LVTTL input command. When

at logic low, the deserializer

function is reinitialized.

RxPOWMON Receiver Power Monitoring:

analog output monitor. This

voltage is proportional to the

mean optical input power.

Typical slope is 1 V / mW fr om

–1 to–17dBm.

RxPOWALM Receiver Power Alarm: LVTTL

output alarm. Set to logic low

when the incoming optical

power is less than –17dBm+/-

2dB.

RxLOCKERR Receiver Loss of Clock Error:

LVTTL output alarm. Set to logic

low when the clock recovery is

not locked onto the optical data

stream. Set to logic high in

normal operation.

RxRAT ESEL Receiver rate Selection : LV T TL

input comm a nd. Selects the bit

rate. When is at logic high, the

standard 9.95328Gbits/s bit

rate is selected, if it’s logic low

the FEC bit rate 10.709Gbit/s

is selected. Note that in this

case the RxREFCLK frequency

has to be 167.328MHz.

FFU Reserve For Future Use.

NUC No User Connection.

KJHGFEDCBA

1Rx+5VA FFU FGND RxDout12P FFU RxDout8P RxDigGND RxDout4P RxDigGND RxDout0P

2Rx+5VA FFU FGND RxDout12N FFU RxDout8N RxDigGND RxDout4N RxDigGND RxDout0N

3RxRATESEL FFU FFU RxDigGND RxPOWMON RxDigGND FFU RxDigGND FFU RxDigGND

4Rx3.3VA NUC FGND RxDout13P Rx3.3VD RxDout9P RxDigGND RxDout5P RxDigGND RxDout1P

5Rx3.3VA NUC FGND RxDout13N Rx3.3VD RxDout9N RxDigGND RxDout5N RxDigGND RxDout1N

6RxRESET NUC FFU RxDigGND RxPOWALM RxDigGND FFU RxDigGND FFU RxDigGND

7FFU FFU RxAGND RxDout14P Rx3.3VD RxDout10P RxDigGND RxDout6P RxDigGND RxDout2P

8FFU FFU RxAGND RxDout14N Rx3.3VD RxDout10N RxDigGND RxDout6N RxDigGND RxDout2N

9FFU NUC FFU RxDigGND FFU RxDigGND FFU RxDigGND RxLCKREF RxDigGND

10 Rx-5.2VA FFU RxAGND RxDout15P Rx-5.2VD RxDout11P RxDigGND RxDout7P RxDigGND RxDout3P

11 Rx-5.2VA FFU RxAGND RxDout15N Rx-5.2VD RxDout11N RxDigGND RxDout7N RxDigGND RxDout3N

12 FFU NUC FFU RxDigGND FFU RxDigGND FFU RxDigGND FFU RxDigGND

13 Rx-5.2VA FFU RxAGND FFU Rx-5.2VD RxPOCLKP RxDigGND RxMCLKP RxDigGND RxREFCLKP

14 Rx-5.2VA FFU RxAGND FFU Rx-5.2VD RxPOCLKN RxDigGND RxMCLKN RxDigGND RxREFCLKN

15 FFU NUC TBD RxDigGND FFU RxDigGND FFU RxDigGND RxLOCKERR RxDigGND

16 Tx+5VA FFU TxAGND TxDin12P FFU TxDin8P TxDigGND TxDin4P TxDigGND TxDin0P

17 Tx+5VA FFU TxAGND TxDin12N FFU TxDin8N TxDigGND TxDin4N TxDigGND TxDin0N

18 FFUNUCFFUTxDigGNDLsBIASMON TxDigGND LsPOWMON TxDigGND TxSKEWSEL0 TxDigGND

19 Tx3.3VA FFU TxAGND TxDin13P Tx3.3VD TxDin9P TxDigGND TxDin5P TxDigGND TxDin1P

20 Tx3.3VA FFU TxAGND TxDin13N Tx3.3VD TxDin9N TxDigGND TxDin5N TxDigGND TxDin1N

21 TxRATESEL FFU FFU TxDigGND LsENABLE TxDigGND LsTEMPMON TxDigGND TxSKEWSEL1 TxDigGND

22 Tx3.3VA FFU TxAGND TxDin14P Tx3.3VD TxDin10P TxDigGND TxDin6P TxDigGND TxDin2P

23 Tx3.3VA FFU TxAGND TxDin14N Tx3.3VD TxDin10N TxDigGND TxDin6N TxDigGND TxDin2N

24 TxRESET NUC FFU TxDigGND LsBIASALM TxDigGND FFU TxDigGND FFU TxDigGND

25 Tx-5.2VA NUC FGND TxDin15P Tx-5.2VD TxDin11P TxDigGND TxDin7P TxDigGND TxDin3P

26 Tx-5.2VA NUC FGND TxDin15N Tx-5.2VD TxDin11N TxDigGND TxDin7N TxDigGND TxDin3N

27 FFUNUCFFUTxDigGNDLsTEMPALM TxDigGND FFU TxDigGND TxPICLKSEL TxDigGND

28 Tx-5.2VA FFU FGND TxPICLKP Tx-5.2VD TxPCLKP TxDigGND A Tx155MCKP TxDigGND TxREFCLKP

29 Tx-5.2VA FFU FGND TxPICLKN Tx-5.2VD TxPCLKN TxDigGND Tx155MCKN TxDigGND TxREFCLKN

30 FFUNUCFFUTxDigGNDTxREFSEL TxDigGND FFU TxDigGND TxLOCK ERR TxDigGND

Receiver power & GND supplies Transmitter power & GND supplies NUC No User Connection

Receiver d.c. signals Transmitter d.c. signals FFU Re se rve For Futur e U se

622 differential signals 622 differential signals

TransmitterReceiver

Transmitter pin description

TxDin# #P Transmitter NRZ Data Input

Positive: 622 Mbit/s LVDS input

signal. Data are retimed at the

input of the modu le by the input

clock TxPICLK signal. TxDin15

is the most significant and the

first bit transmitted

TxDin# #N Transmitter NRZ Data Input

Negative: 622 Mbit/s LVDS

input signal. Data are retimed

at the input of the modu le by

the input clock TxPICL K signal.

TxDin15 is the most significant

and the first bit transm itted.

TxPICLKP Transmitter Parallel Input Clock

Positive: 622 MHz or 311 MHz

LVDS input signal. When

TxPICLKSEL is at logic low, the

frequency has to be 622 MHz

and the rising edge of

TxPICLKN is in the middle of the

data pattern. When TxPICLKSEL

is at logic high, the frequency

has to be 311 MHz and the

rising/falling edges of

TxPICLKN are in the m iddle of

the data crossing point.

TxPICLKN Transmitter Parallel Input Clock

Negative: 622 MHz or 311

MHz LVDS input signal. When

TxPICLKSEL is at logic low, the

frequency has to be 622 MHz

and the falling edge of

TxPICLKN is in the middle of the

data pattern. When TxPICLKSEL

is at logic high, the frequency

has to be 311 MHz and the

falling edge of TxPICLKN is in

the middle of the data crossing

point.

TxPCLKP Transmitter Parallel Clock

output Positive: 622 MHz LVDS

output signal. Refer ence clock

generated from the TxREFCLK

signal. Usable to synchronize

the output data stage of the

framer A SIC.

TxPCLKN Transmitter Parallel Clock

output Negative: 622 MHz

LVDS ou tput signal. Reference

clock generated from the

TxREFCLK signal. Usable to

synchronize the output data

stage of the framer ASIC .

TxREFCLKP Transmitter Reference Clock

Positive: 622 MHz or 155 MHz

PECL compatible inpu t signal.

When TxREFSEL0 is at logic low,

the frequency is 155 MHz.

When RxREFSEL0 is at logic

high, the frequency is 622 MHz.

TxREFCLKN Transmitter Reference Clock

Negative: 622 MHz or 155

MHz PECL compatible input

signal. When TxREFSEL0 is at

logic low, the frequency is 155

MHz. When RxREFSEL0 is at

logic high, the frequency is 622

MHz.

TxMCLKP Transmitter Monitor Clock

Positive: 155 MHz LVDS clock

output signal. This signal

represents the synthesized

frequency of the serializer.

TxMCLKN Transmitter Monitor Clock

Negative: 155 MHz LVDS clock

output signal. This signal

represents the synthesized

frequency of the serializer.

TxPICLKSEL Transmitter Par a llel Clock

Select: LVTT L input command.

Selects the referenc e frequency

mode of TxPICLK. When at

logic low, the frequency has to

be 622 MHz. When at logic

high, the frequency has to be

311 MHz.

TxREFSEL Transmitter Reference clock

Select : LVTT L input command.

Selects the referenc e frequency

mode of TxREFCLK. When at

logic low, the frequency is 155

MHz. When at logic high, the

frequency is 622 MHz.

TxSKEWSEL0 Transmitter Adjusts Skew of

TxPICLK Select: LVTTL input

command. This LSB digital logic

input allows delaying internally

the TxPICLK in the 311 MHz

mode.

TxSKEWSEL1 Transmitter Adjusts Skew of

TxPICLK Select: LVTTL input

command. This MSB digital

logic input allows delaying

internally the TxPICL K in the

311 MHz mode.

TxRAT ESEL Transmitter Rate Selection:

LVTTL input command. Selects

the bit rate. When is at logic

high, the standard

9.95328Gbits/s bit rate is

selected, if it’s logic low the FEC

bit rate 10.709Gbit/s is

selected. Note that in this case

the TxREFCLK frequency has to

be 167.328MHz or

669.312MHz.

TxRESET Transmitter serializer RESET:

LVTTL input command. When at

logic low, the serializer function

is reinitialized.

LsENABLE Laser Enable: LVTTL input

command. When at logic high,

the laser is disabled. When at

logic low, the laser is enabled.

TxLOCKERRTransmitter Lock Error: LVTTL

output alarm. When at logic

low, it indicates that the

serializer is not locked on the

TxREFCLK. When at logic high,

the serializer is in normal

operating.

LsBIASALM Laser Bias Alar m: LVTTL output

alarm. When at logic low, the

laser has reached its end of life

condition. When at logic high,

the laser is in normal operating.

LsTEMPA LMLaser Tem perature Alarm:

LVTTL output alarm. When at

logic low, the laser temperature

is approximately 3°C above or

below the normal operating.

When at logic high, the laser is

in normal operating.

LsBIASMon Laser Bias Monitoring: analog

output monitor. This voltage is

proportional to the laser

current. The typical slope is 20

mV / mA.

LsPOWMonLaser Power Monitoring: analog

output monitor. This voltage is

proportional to the laser output

power. Normalized at 0.5V

over lifetime, the 50 % drift in

output power correlates with a

50 % variation in output

voltage.

LsTEMPMonLaser temper ature Monitoring:

analog output monitor. This

voltage represents the laser

temperature deviation.

Normalized at 2. 5V over

lifetime.

FFU Reserved for further additional

features.

NUC No User Connection. This pin

has to be left open.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Maximum optical input power + 2 dBm

Negative supply voltage VEE - 6 0 V

1st Positive supply voltage VDD 0+ 3.6V

2nd Positive supply voltage VCC 0+ 6V

Control input voltage 0 VDD V

Digital output voltage 0 VDD V

Analog output voltage 0 VDD V

Alarm output voltage 0 VDD V

Stora g e temper a ture TSTG - 20 + 70 °C

Storage 72h max - 40 + 85 °C

Operating case temperature TOP - 5 + 65 °C

Ordering information

Alc a tel 1964 TRX

Dispersion Span Part Number

(ps/nm) (km)

I-64.2 / SR- 2 400 25 3CN 00576 xx

I-64.2 / SR- 2 FEC 400 25 3CN 00578 xx

S-64.2b / IR - 2 800 40 3CN 00532 xx

S-64.2b / IR - 2 FEC 800 40 3CN 00577 xx

Options

3CN xxxxx xA → FC/PC Ax → With heat sink

xB → SC/PC Bx → Without heat sink

July 2001

Alcatel Optronics

Customized versions are available for lar ge

quantities.

Performance figures contained in this

document must be specifically confirmed in

writing by Alcatel Optronics before they

become applicable to any particular or der

or contract. Alcatel Optronics reserves the

right to make changes to the pr oducts or

information contained herein without

notice.

Standards

Compliant with ITU-T G.691

Telcordia GR-253-ed.3

Optical Interworking Forum

OIF99.102

Optical fiber according to ITU-T G.652

Environment according to IEC 68-2 and

MIL STD 883

Telcordia TR-EOP-000063

LASER RADIATION

AVOID E XPOSURE TO BEAM

Class 3A la ser product

ATTENTION

OBSERVE

PRECAUTIONS FOR

HANDLING

ELECTROSTATIC

DISCHARGE

SENSITIVE DEVICES

EUROPE

Route de Villejust

F-91625 NOZAY CEDEX

Tel : (+33) 1 64 49 49 10

Fax : (+33) 1 64 49 49 61

USA

15036, Conference Centre Drive

CHANTILLY - VA 20151

Tel : (+1) 703 679 3600

Fax : (+1) 703 679 6667

CANADA

45, De Villebois, suite 200

Gatineau (PQ)

Canada, J8T 8J7

Tel : (+1) 703 715 3922

Fax : (+1) 703 860 1183

JAPAN

Dai-Tokyo Kasai

Shinjuku Building 13F

3-25-3, Yoyogi, Shibuya-Ku

TOKYO 151 - 0053

Tel : (+81) 3 5302 4341

Fax : (+81) 3 5302 4331