1/16October 2004
■HIGH SPE ED GTL/ GTL+ UN IVERSAL
TRANSCEIVER:
tPD = 4.6 ns (MAX.) A t o B at VCC = 3V
■COMBIN ES D-TYPE L ATCHES AN D D-TYPE
FLIP-FLOPS FOR OPERATION IN
TRANSPAREN T, LATCHED, OR CLOCKED
MODE
■OPERATI NG VOLTAGE RAN GE:
VCC(O PR) = 3.0V to 3.6V
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT)
■OUTPUT IMPEDANCE:
IOL = 100mA (MIN) at VCC = 3V (B PORT)
■HIGH-IMPEDANCE STA TE DURING POWE R
UP AND POWER DOWN up to
VCC=BIASVCC=1.5V PERMITT LIVE
INSERTION
■B-PORT PRECHARGED BY BIASVCC
REDUC E NOISE ON THE LINE DURING
LIVE INSERTIO N
■EDGE RATE-CON TROL INP UT
CONFIGURES THE B-PORT OUTPUT RISE
AND FALL TIMES
■BUS HOLD ON DATA INPUTS ELIMINATES
THE NEED FOR EXTERN AL PULL- U P/
PULL-D OWN RESISTORS (A PORT)
■DISTRIBUTED VCC AND GND PIN
CONFIGURATION MINIMIZES HIGH-SPEED
SW ITCHING NOISE IN PARALLEL
COMUNICATIONS
■PIN AND FUNCTION COMPAT IBLE WITH
74 SERIES 1655
DESCRIPTION
The 74GTL1655A devices are 16-bit high-drive
(100mA), low-output-impedance universal bus
transc eivers designed fo r backplane a pplications.
The 74GTL1655A devices provide live-insertion
capability for backplane applications by tolerating
active signal s on th e da ta ports when the devices
are powered off. In addition, a biasing pin
preconditions the GTL/GTL+ port to minimize
disru ption to an active backplane.
The edg e rate-control (VERC) inp ut is provided so
the rise and fall time of the B outputs can be
configured to optimize for various backplane
loading conditions. Data flow in each direction is
74GTL1655A
16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS
TRANSCEIVERS WITH LIVE INSERTIO N
Table 1: Order Codes
PACKAGE T & R
TSSOP 74GTL1655ATTR
TSSOP
Fi gure 1: Pin Connec t ion
Rev. 1
74GTL1655A
2/16
controlled by output-enable (OEAB and OEBA),
latch-enable (LEAB and LEBA), and clock (CLK)
inputs. For A-to-B data flow, the devices operate
in the transparent mode when LEAB is high. When
LEAB i s low, the A data is latched if CLK is held at
a high o r l o w log ic leve l . If LEAB is low, th e A d a ta
is stored in the latch/flip-flop on the low-to-high
transition o f CLK. When O E AB is low, the outputs
are active. When OEAB is high, the outputs are in
the high-impedance state. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA,
and CLK. The output enable (OE) is used to
disable both ports simu ltaneous ly.
Act ive bus-hold circuitry is prov ided on the A port
to hold unused or floating data inputs at a valid
logic level. When VCC is between 0 and 1.5 V, the
device is in the high-impedance state during
power up or power down. Howe ve r, to en sure the
high-impedance state above 1.5V, OE should be
tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the
current -s ink ing capability of the driver.
All input and output are equipped with protection
circuits against static discharge, giving them 2KV
ESD immun ity and transient excess voltage .
Fig ure 2: In put And Ou tp ut E qui v al e n t Ci rcui t
Table 2: Pin Descrip tion
PIN N°SYMBO L NAME AND FUNC TION
1, 2 1OEAB, 1OEBA Output Enable Input
4, 6, 7, 9, 11, 13, 14, 16 1A1 to 1A8 Data Inputs/Outputs LVTTL
17, 19, 20, 22, 23, 25, 27, 29 2A1 to 2A8 Data Inputs/Outputs LVTTL
31, 32 2OEAB, 2OEBA Output Enable Input
33 OE Output Enable Input
34, 35 2LEBA, 2LEAB Latch Enable
36 BIAS VCC Pre-Charge Supply Voltage
37, 38, 40, 42, 43, 45, 46, 48 2B8 to 2B1 Data Inputs/Outputs GTL/GTL+
41 VREF GTL Voltage Reference Input
49, 51, 52, 54, 55, 56, 58, 59 2A1 to 2A8 Data Inputs/Outputs GTL/GTL+
61 VERC E dge Rate Contr ol
62, 63 1LEBA, 1LEAB Latch Enable
64 CLK Clock Input (LOW to HIGH edge triggered)
5, 8, 10, 12, 18, 21, 24, 26, 30,
39, 44, 47, 53, 57, 60 GND Ground (0V)
3, 15, 28, 50 VCC Positive Supply Voltage
74GTL1655A
3/16
Table 3: Function Table (1)
1) A t o B data flow is shown. B to A f l ow i s s i m i l ar, but uses OEBA, LEBA and CLK
2) Output le vel before the indi cated st eady-st at e i n put con di tions were established, pro vided that CLK was hi gh before LEAB we n t low
3) Output level before the indicated steady-state input conditions were established
Ta bl e 4 : O utput Ena bl e Truth Tab le
Table 5: B-Port Edge Rate Control (VERC) Trut h Tabl e
INPUTS OUTPUT MODE
OEAB LEAB CLK A B
HXXXZIsolation
L H X L L Transparent
L H X H H Transparent
LL LLRegistered
L L H H Registered
LLHX
B0(2) Previous State
LLLX
B0(3) Previous State
INPUTS OUTPUTS
OE OEAB OEBA A PORT B PORT
L L L Active Active
LLHZActive
LHLActiveZ
LHHZZ
HXXZZ
INPUT VERC OUTPUT B PORT EDGE RATE
LOGIC LEVEL NOMINAL VOLTAGE
HVCC Slow
LGNDFast
74GTL1655A
4/16
Figure 3: Logic Diagram
74GTL1655A
5/16
Table 6: Absolute Maximum Ratings
Absolute Maximum Rating are those value beyond which damage to the devi ce may occur. Functional operation under these condition is not
implied
Table 7: Recomme nded Op erating Condi tions
1) VTT and RTT ca n be adjusted to ada pt b ackplane i m pedance if DC re commended IOL ratings are not exceeded
2) VREF can be adjusted to optimize noise m argin (ty p two-th i rds VTT)
Symbol Parameter Value Unit
VCC Supply Volt age, Bias VCC -0.5 to +4.6 V
VIA DC Input Voltage A Side, Control Input -0.5 to +4.6 V
VIB DC Input Voltage B Side, VERC, VREF -0.5 to +4.6 V
VOA DC Output Voltage A Side -0.5 to +4.6 V
VOB DC Output Voltage B Side -0.5 to +4.6 V
IIK DC Input Diode Current - 50 mA
IOK DC Output Diode Current - 50 mA
IOA DC Output Current A Side ± 48 mA
IOB DC Output Current B Side in the Low State 200 mA
Tstg Storage Temp eratu re -65 to +150 °C
TLLead Temperature (10 sec) 300 °C
Symbol Parameter Value Unit
Min. Typ. Max.
VCC Supply Volt age 3.0 3.3 3.6 V
VTT Termination Voltage GTL 1.14 1.2 1.26 V
GTL+ 1.35 1.5 1.65
VREF Supply Voltage GTL 0.74 0.8 0.87 V
GTL+ 0.87 1 1.1
VIInput Voltage B port 0VTT V
other 0VCC
VIH High Level Input Voltage B port VREF+0.05 V
other 2
VIL Low Level Input Voltage B port VREF-0.05 V
other 0.8
IIK Input Clamp Current -18 mA
IOH High Level Output Current A port -24 mA
IOL Low Level Output Current A port 24 mA
B port 100
dt/dVCC Power -up ramp rate 200 µs/V
Top Operating Temperature -40 85 °C
74GTL1655A
6/16
Table 8: DC Specifications
(* ) F or I/O po rts, the parame ter IOZ includes the in put leakage current
(* *) Is also g uaranteed when c onnect in g BiasVCC with VCC.
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
-40 to 85 °C
Min. Typ. Max.
VIK High Level Input Voltage 3-1.2V
VOHA High Level Output
Voltage A Port 3 to 3.6 IO=-100µAV
CC-0.2
V3 IO=-12mA 2.4
3IO=-24mA 2.2
VOLA Low Level Output
Voltage A Port 3 to 3.6 IO=100µA0.2 V3 IO=12mA 0.4
3IO=24mA 0.55
VOLB Low Level Output
Voltage B Port 3IO=40mA 0.2 V3 IO=80mA 0.4
3IO=100mA 0.5
IIInput Current Control 3.6 VI = VCC or GND ±10 µA
B Port 3.6 VI = VTT or GND ±10 µA
Ioff Power Off Leakage
Current 0V
I or VO = 0 to 3.6V ±100 µA
II(HOLD) Bus Hold A Port Input
Current 3VI = 0.8V 75 20 µA3 VI = 2V -75
3.6 VI = 0 to VCC ± 500
IOZHB 3-S t ate Output Current B
Port 3.6 VO = 1.5V 10 µA
IOZLB 3-S t ate Output Current B
Port 3.6 VO = 0.4V -10 µA
IOZ (*) 3-St ate Output Current A
Port 3.6 VO = VCC or GND ±10 µA
IOZPU** 3-S t ate Output Current A
Port 0 to 1.5 VO = 0.5 to 3V
OE = LOW ±50 µA
IOZPD** 3-S t ate Output Current A
Port 1.5 to 0 VO = 0.5 to 3V
OE = LOW ±50 µA
ICC Quiescent Supply
Current 3.6 VI = VCC or GND
IO=0 10 40 mA
∆ICC ∆ Supply Current except
B port 3.6 VIN = VCC or GND
One input VCC =0.6V 1mA
CIControl Input Capaci-
tance VIN = VCC or GND 35pF
COInput Capacit ance A Port VO = VCC or GND 56
pF
Input Capacit ance B Port 6 8
74GTL1655A
7/16
Table 9: Live Insertion S pecifications
Table 10: AC Electrical Characteristics for GTL
(VCC=3.3 ± 0.3V, VTT=1.2V, VREF=0.8V, VERC=VCC or GND)
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
-40 to 85 °C
Min. Typ. Max.
ICC (Bi as
VCC)Quiescent Bias Current 0 to 3.0 VO(Bport) = 0 to 1.2V 5 mA
3 to 3.6 VI(Bias Vcc) = 3 to 3.6V 10 µA
VOOutput Voltage B Port 0 VI(Bias Vcc) = 3.3V 1 1.2 V
IOOutput Current B Port 0 VO(Bport) = 0.4V
VI(Bias Vcc) = 3 to 3.6V -1 µA
0 to 3.6 OE = 3.3V 100 µA
0 to 1.5 OE = 0 to 3.3V 100 µA
Symbol Parameter Test Condition
Value
Unit-40 to 85 °C
Min. Typ. Max.
fMAX Maximum Frequency
A to B or B to A 160 MHz
tPLH Propagation Delay Time
A to B VERC=VCC R1=12.5Ω CL=30pF 1.5 5.2 ns
tPHL 1.5 6.2
tPLH Propagation Delay Time
CK to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.5 ns
tPHL 1.5 5.8
tPLH Propagation Delay Time
LEAB to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.8 ns
tPHL 1.5 6.4
tEN Enable Delay Time
OEAB or OE to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.4
ns
tDIS Disable Delay Time
OEAB or OE to B 1.5 6.2
tPLH Propagation Delay Time
A to B VERC=GND RL=12.5Ω CL=30pF 1.5 4.3 ns
tPHL 1.5 4.6
tPLH Propagation Delay Time
CK to B VERC=GND RL=12.5Ω CL=30pF 1.5 4.3 ns
tPHL 1.5 4.9
tPLH Propagation Delay Time
LEAB to B VERC=GND RL=12.5Ω CL=30pF 1.5 4.9 ns
tPHL 1.5 4.8
tEN Enable Delay Time
OEAB or OE to B VERC=GND RL=12.5Ω CL=30pF 1.5 4.8
ns
tDIS Disable Delay Time
OEAB or OE to B 1.5 4.2
tPLH Propagation Delay Time
B to A RL=500Ω C
L=50pF 1.5 4.7 ns
tPHL 1.5 4.8
tPLH Propagation Delay Time
CK to A RL=500Ω C
L=50pF 1.5 4 ns
tPHL 1.5 4
tPLH Propagation Delay Time
LEBA to A RL=500Ω C
L=50pF 1.5 4 ns
tPHL 1.5 3.7
74GTL1655A
8/16
Table 11: AC Electrical Characteristics for GTL+
(VCC=3.3 ± 0.3V, VTT=1.5V, VREF=1.0V, VERC=VCC or GND)
tEN Enable Delay Time
OEBA or OE to A RL=500Ω R1=500ΩCL=50pF 1 4.6
ns
tDIS Disable Delay Time
OEBA or OE to A 16.1
tSU Set-up Time Data before clock 2.7 nsData before LE Ck High 2.8
Ck Low 2.6
tHHold Time Data after clock 0.4 ns
Data after LE Ck High or LOW 0.9
tWPulse duration LE High 3 ns
CK High or Low 3
Slew rate Slew rate B output both
transition (0.6 to 1.3V) VERC=VCC 1
ns/V
VERC=GND 1
tsk Skew between drivers (in
the same package) Switching in the same direction 1 ns
Switching in any direction 1
Symbol Parameter Test Condition
Value
Unit-40 to 85 °C
Min. Typ. Max.
fMAX Maximum Frequency
B to A or A to B 160 MHz
tPLH Propagation Delay Time
A to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.1 ns
tPHL 1.5 6.5
tPLH Propagation Delay Time
CK to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.4 ns
tPHL 1.5 6.2
tPLH Propagation Delay Time
LEAB to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.7 ns
tPHL 1.5 6.7
tEN Enable Delay Time
OEAB or OE to B VERC=VCC RL=12.5Ω CL=30pF 1.5 5.5
ns
tDIS Disable Delay Time
OEAB or OE to B 1.5 5.8
tPLH Propagation Delay Time
A to B VERC=GND RL=12.5Ω CL=30pF 1.0 4.3 ns
tPHL 1.0 4.9
tPLH Propagation Delay Time
CK to B VERC=GND RL=12.5Ω CL=30pF 1.0 4.0 ns
tPHL 1.0 5.5
tPLH Propagation Delay Time
LEAB to B VERC=GND RL=12.5Ω CL=30pF 1.0 4.0 ns
tPHL 1.0 5.4
tEN Enable Delay Time
OEAB or OE to B VERC=GND RL=12.5Ω CL=30pF 1.0 5.1
ns
tDIS Disable Delay Time
OEAB or OE to B 1.0 4.9
Symbol Parameter Test Condition
Value
Unit-40 to 85 °C
Min. Typ. Max.
74GTL1655A
9/16
Fi gure 4: T est Circuit For "A" Outp uts
CL = 50pF or equival ent (includes jig and probe capacit ance)
RL = R 1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typ ically 50Ω)
tr=tf <=2.5ns
tPLH Propagation Delay Time
B to A RL=500Ω C
L=50pF 1.5 4.8 ns
tPHL 1.5 4.7
tPLH Propagation Delay Time
CK to A RL=500Ω C
L=50pF 1.5 4.4 ns
tPHL 1.5 4.1
tPLH Propagation Delay Time
LEBA to A RL=500Ω C
L=50pF 1.5 4 ns
tPHL 1.5 3.7
tEN Enable Delay Time
OEBA or OE to A RL=500Ω R1=500ΩCL=50pF 1 4.2
ns
tDIS Disable Delay Time
OEBA or OE to A 16.1
Slew rate Slew rate B output both
transition (0.6 to 1.3V) VERC=VCC RL=12.5Ω CL=30pF 1 ns/V
VERC=GND RL=12.5Ω CL=30pF 1
tWPulse duration LE High 3 ns
CK High or Low 3
tSU Set-up Time Data before clock 2.7 nsData before LE Ck High 2.8
Ck Low 2.6
tHHold Time Data after clock 0.4 ns
Data after LE Ck High or LOW 0.9
tsk Skew between drivers (in
the same package) Switching in the same direction 1 ns
Switching in any direction 1
Test Switch
tPLH, tPHL Open
tPZL, tPLZ 6V
tPZH, tPHZ GND
Symbol Parameter Test Condition
Value
Unit-40 to 85 °C
Min. Typ. Max.
74GTL1655A
10/16
Table 12: Test Cir cuit For "B" Outpu ts
CL = 30pF or equival ent (includes jig and probe capacit ance)
RL = R 1 = 12.5Ω or eq ui valen t
RT = ZOUT of pulse generator (typ ically 50Ω)
tr=tf <=2.5ns
Figure 5 : W a v eform - Pu ls e Duration ( A Port, Control Pin)
Figure 6: Waveform - Clock To B Port Propagation Delay Ti me
74GTL1655A
11/16
Figure 7: Waveform - Clock To A Port Propagation Delay Ti me
Fi gure 8: Waveform - Setu p An d Hold Time
74GTL1655A
12/16
Figure 9: Waveform - Ena ble An d Disable Time (A Port)
74GTL1655A
13/16
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.1 0.043
A1 0.05 0.15 0.002 0.006
A2 0.9 0.035
b 0.17 0.27 0.0067 0.011
c 0.09 0.20 0.0035 0.0079
D 16.9 17.1 0.665 0.673
E 8.1 0.318
E1 6.0 6.2 0.236 0.244
e 0.5 BSC 0.0197 BSC
K0˚ 8˚0˚ 8˚
L 0.50 0.75 0.020 0.030
TSSOP64 MECHANICAL DATA
cE
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1 L
K
e
7187824A
74GTL1655A
14/16
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 30.4 1.197
Ao 8.7 8.9 0.342 0.350
Bo 17.2 17.4 0.677 0.685
Ko 1.4 1.6 0.055 0.063
Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
Tape & Reel TSSOP64 MECHANICAL DATA
74GTL1655A
15/16
Table 13: Revision History
Date Revisio n Description of Ch anges
18-Oct-2004 1 First Release.
74GTL1655A
16/16
Information fur nished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsib ility for the consequences
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by implication or otherwise under any patent or patent rights of STMicroelectronics . Specifications mentioned in this publication are subject
to change wi thout notice. This publication supersedes and replaces all information previously supplied. STMic roelectronics products ar e not
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