X9315WSIZT1 - Intersil Corporation

FN8179.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X9315

Low Noise, Low Power, 32 Taps

Digitally Controlled Potentiometer

(XDCP™)

The Intersil X9315 is a digitally controlled potentiomete r

(XDCP). The device consists of a resistor array, wiper

switches, a control section, and nonvolatile me mory. The

wiper position is controlled by a 3-wire interface .

The potentiometer is implemented by a resistor ar ray

composed of 31 resistive elements and a wiper switching

network. Between each element and at either end are tap

points accessible to the wiper terminal. The position of the

wiper element is controlled by the CS, U/D, and INC inputs.

The position of the wiper can be stored in nonvolatile

memory and then be recalled upon a subseque nt power-up

operation.

The device can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide vari ety of

applications including:

• Control

• Parameter Adjustments

• Signal Processing

Features

• Solid-state potentiometer

• 3-wire serial interface

• 32 wiper tap points

- Wiper positio n stored in nonvolatile memory and

recalled on power-up

• 31 resistive elements

- Temperature compensated

- End to end resi stance range ± 20%

- Terminal voltage, 0 to VCC

• Low powe r CMOS

-V

CC = 2.7V or 5V

- Activ e current, 80/400µA max.

- Standby current, 5µA max.

• High reliability

- Endurance, 100,000 data changes per bit

- Register data retention, 100 years

•R

TOTAL values = 10kΩ, 50kΩ, 100kΩ

• Packages

- 8 Ld SOIC, MSOP and PDIP

• Pb-free available (RoHS co mpliant)

Block Diagram

5-Bit

Up/Down

Counter

5-Bit

Nonvolatile

Memory

Store and

Recall

Control

Circuitry

One

Decoder

Resistor

Array

RH/VH

U/D

INC

Transfer

Gates

Thirty

VCC

VSS

RL/VL

RW/VW

Control

and

Memory

Up/Down

(U/D)

Increment

(INC)

Device Select

(CS)

VCC (Supply Voltage)

VSS (Ground)

RH/VH

RW/VW

RL/VL

General

Detailed

Two

Data Sheet December 21, 2009

2FN8179.2

December 21, 2009

Ordering Information

PART NUMBER PART MARKING VCC LIMITS

(V) RTOTAL

(kΩ)TEMP RANGE

(°C) PACKAGE PKG.

DWG. #

X9315WMZ (Note 2) DDT 5 ±10% 10 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMZT1 (Notes 1, 2) DDT 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMIT2 (Note 1) AAX -40 to 85 8 Ld MSOP M8.118

X9315WMIZ (Note 2) AKW -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WMIZT1 (Notes 1, 2) AKW -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WP X9315WP 0 to 70 8 Ld PDIP MDP0031

X9315WST1 (Note 1) X9315W 0 to 70 8 Ld SOIC M8.15E

X9315WSZ (Note 2) X9315W Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSZT1 (Notes 1, 2) X9315W Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSI X9315W I -40 to 85 8 Ld SOIC M8.15E

X9315WSIT1 (Note 1) X9315W I -40 to 85 8 Ld SOIC M8.15E

X9315WSIZ (Note 2) X9315W ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WSIZT1 (Notes 1, 2) X9315W ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315UMZ (Note 2) DDS 50 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMZT1 (Notes 1, 2) DDS 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMI AEB -40 to 85 8 Ld MSOP M8.118

X9315UMIT1 (Notes 1, 2) AEB -40 to 85 8 Ld MSOP M8.118

X9315UMIZ (Note 2) DDR -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UMIZT1 (Notes 1, 2) DDR -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UST2 (Note 1) X9315U 0 to 70 8 Ld SOIC M8.15E

X9315USZ (Note 2) X9315U Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USZT1 (Notes 1, 2) X9315U Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USIZ (Note 2) X9315U ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315USIZT1 (Notes 1, 2) X9315U ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TMZ (Note 2) DDN 100 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMZT1 (Notes 1, 2) DDN 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMIZ (Note 2) DDL -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TMIZT1 (Notes 1, 2) DDL -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TSZ (Note 2) X9315T Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSZT1 (Notes 1, 2) X9315T Z 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ (Note 2) X9315T ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TSIZT1 (Notes 1, 2) X9315T ZI -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WMZ-2.7 (Note 2) AOI 2.7 to 5.5 10 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMZ-2.7T1 (Notes 1, 2) AOI 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315WMI-2.7T2 (Note 1) AAV -40 to 85 8 Ld MSOP M8.118

X9315WMIZ-2.7 (Note 2) AKX -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WMIZ-2.7T1 (Notes 1, 2) AKX -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315WS-2.7 X9315W F 0 to 70 8 Ld SOIC M8.15E

X9315

3FN8179.2

December 21, 2009

X9315WS-2.7T1 (Note 1) X9315W F 2.7 to 5.5 10 0 to 70 8 Ld SOIC M8.15E

X9315WSZ-2.7 (Note 2) X9315W ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSZ-2.7T1 (Notes 1, 2) X9315W ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315WSI-2.7T1 (Note 1) X9315W G -40 to 85 8 Ld SOIC M8.15E

X9315WSIZ-2.7 (Note 2) X9315W ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315WSIZ-2.7T1 (Notes 1, 2) X9315W ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315UMZ-2.7 (Note 2) AKU 50 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMZ-2.7T1 (Notes 1, 2) AKU 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315UMIZ-2.7 (Note 2) AJG -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315UMIZ-2.7T1 (Notes 1, 2) AJG -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315US-2.7T2 (Note 1) X9315U F 0 to 70 8 Ld SOIC M8.15E

X9315USZ-2.7 (Note 2) X9315U ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USZ-2.7T1 (Notes 1, 2) X9315U ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315USI-2.7 X9315U G -40 to 85 8 Ld SOIC M8.15E

X9315USIZ-2.7 (Note 2) X9315U ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315USIZ-2.7T1 (Notes 1, 2) X9315U ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TMZ-2.7 (Note 2) DDP 100 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMZ-2.7T1 (Notes 1, 2) DDP 0 to 70 8 Ld MSOP (Pb-free) M8.118

X9315TMI-2.7T1 (Note 1) ADY -40 to 85 8 Ld MSOP M8.118

X9315TMIZ-2.7 (Note 2) DDM -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TMIZ-2.7T1 (Notes 1, 2) DDM -40 to 85 8 Ld MSOP (Pb-free) M8.118

X9315TSZ-2.7 (Note 2) X9315T ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSZ-2.7T1 (Notes 1, 2) X9315T ZF 0 to 70 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ-2.7 (Note 2) X9315T ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

X9315TSIZ-2.7T1 (Notes 1, 2) X9315T ZG -40 to 85 8 Ld SOIC (Pb-free) M8.15

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

Ordering Information (Continued)

PART NUMBER PART MARKING VCC LIMITS

(V) RTOTAL

(kΩ)TEMP RANGE

(°C) PACKAGE PKG.

DWG. #

X9315

4FN8179.2

December 21, 2009

Pin Configuration X9315

(8 LD MSOP, SOIC, PDIP)

TOP VIEW

Pin Description

RH/VH and RL/VL

The high (RH/VH) and low (RL/VL) terminals of the X9315

are equivalent to the fixed terminals of a mech anical

potentiometer. The minimum voltage is VSS and the

maximum is VCC. The terminology of RL/VL and RH/VH

references the relative position of the terminal in relation to

wiper movement direction selected by the U/D input, and not

the voltage potential on the terminal.

RW/VW

RW/Vw is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the control inputs.

The wiper terminal series resistance is typically 200Ω at

VCC = 5V.

Up/Down (U/D)

The U/D input controls the direction of the wiper movement

and whether the counter is incremented or decremented.

Increment (INC)

The INC input is negative-edge triggered. Toggling INC will

move the wiper and either increment or decrement the

counter in the direction indicated by the logic level on the

U/D input.

Chip Select (CS)

The device is selected when the CS input is LOW. The

current counter value is stored in nonvolatile memory when

CS is returned HIGH while the INC input is also HIGH. After

the store operation is complete th e X9315 will be placed in

the low power standby mode until the device is selected

once again.

Principles of Operation

There are three sections of the X9315: the inp ut control ,

counter and decode section; the nonvolatile memory; and

the resistor array . The input control section operates just like

an up/down counter . The output of this counter is decoded to

turn on a single electronic switch connecting a point on the

resistor array to the wiper output. Under the proper

conditions the contents of the counter can be stored in

nonvolatile memory and retained for future use. The resistor

array is comprised of 31 individual resistors connected in

series. At either end of the array and between each resistor

is an electronic switch that transfers the connection at that

point to the wiper.

The wiper, when at either fixed terminal, acts like its

mechanical equivalent and does not move beyond the last

position. That is, the counter does not wrap around when

clocked to either extreme.

The electronic switches on the device operate in a “ma ke

before break” mode when the wiper changes tap positions. If

the wiper is moved several positions, multiple taps are

connected to the wiper for tIW (INC to VW change). The

RTOTAL value for the device can temporarily be reduced by

a significant amount if the wiper is moved several positions.

When the device is powered-down, the last wiper posi tio n

stored will be maintained in the nonvolatile memory. When

power is restored, the contents of the memory are recalled

and the wiper is set to the value last sto r ed.

Instructions and Programming

The INC, U/D and CS inp uts control the movement of the

wiper along the resistor array. With CS set LOW the device

is selected and enabled to respond to the U/D and INC

inputs. HIGH to LOW transitions on INC will increment or

decrement (depending on the state of the U/D input) a five

bit counter . The output of this counter is decoded to select

one of thirty two wiper positions along the resistive array.

The value of the counter is stored in no nvolatile memory

whenever CS transitions HIGH while the INC input is also

HIGH.

The system may select the X9315, move the wiper and

deselect the device without having to store the latest wiper

position in nonvolatile memory. After the wiper movement is

performed as described above and once the new position is

reached, the system must keep INC LOW while taking CS

HIGH. The new wiper position will be maintained until

Pin Names

SYMBOL DESCRIPTION

RH/VHHigh terminal

RW/VWWiper terminal

RL/VLLow terminal

VSS Ground

VCC Supply voltage

U/D Up/Down control input

INC Increment control input

CS Chip Select control input

VCC

INC

U/D

RH/VH

VSS

X9315 RL/VL

RW/VW

X9315

5FN8179.2

December 21, 2009

changed by the system or until a power-up/down cycle

recalled the previously stored data.

This procedure allows the system to always power-up to a

preset value stored in nonvolatile memory; then during

system operation minor adjustments could be made. The

adjustments might be based on user preference, system

parameter changes due to temperature drift, etc...

The state of U/D may be changed while CS remains LOW.

This allows the host system to enable the device and then

move the wiper up and down until the proper trim is attained.

Power-up and Down Requirements

There are no restrictions on the power-up or power-down

conditions of VCC and the voltages applied to the

potentiometer pins provided that VCC is always more

positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL,

VW. The VCC ramp rate spec is always in effect.

Mode Selection

CS INC U/D MODE

L H Wiper up

L L Wiper down

H X Store wiper position to nonvolatile

memory

H X X Standby

L X No store, return to standby

L H Wiper Up (not recommended)

L L Wiper Down (not recommended)

X9315

6FN8179.2

December 21, 2009

Absolute Maximum Ratings Thermal Information

Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on CS, INC, U/D, VH, VL and

VCC with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

ΔV = |VH–VL| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V

IW (10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5mA

Thermal Resistance (Typica l, Notes 3, 4) θJA (°C/W) θJC (°C/W)

8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . 105 68

8 Ld MSOP. . . . . . . . . . . . . . . . . . . . . . 154 58

8 Ld PDIP. . . . . . . . . . . . . . . . . . . . . . . 85 57

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +8 5°C

Supply Voltage (VCC) (Note 8) Limits

X9315. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%

X9315-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Max Wiper Current, IW. . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.75mA

Max Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. For θJC, the “case temp” location is taken at the package top center.

Potentiometer Characteristics (Over recommended operating conditions unless otherwise stated.)

SYMBOL PARAMETER TEST CONDITIONS/NOTES

LIMITS

MIN

(Note 9) TYP

(Note 8) MAX

(Note 9) UNIT

End to end resistance tolerance -20 +20 %

VVH VH terminal voltage 0 VCC V

VVL VL terminal voltage 0 VCC V

RWWiper resistance IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 5V 200 400 Ω

RWWiper resistance IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 2.7V 400 1000 Ω

Noise Ref: 1kHz -120 dBV

Resolution 3%

Absolute linearity (Note 5) Vw(n)(actual) - Vw(n)(expected) ±1 MI

(Note 7)

Relative linearity (Note 6) Vw(n + 1) - [Vw(n) + MI]±0.2MI

(Note 7)

RTOTAL temperature coefficient ±300 ppm/°C

Ratiometric temperature coefficient ±20 ppm/°C

CH/CL/CWPotentiometer capacitances See circuit #3 on page 7 10/10/25 pF

NOTES:

5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (Vw(n)(actual) - Vw(n)(expected)) = ±1 Ml Maximum.

6. Relative linearity is a measure of the error in step size between taps = RW(n+1) - [Rw(n) + Ml] = ±0.2 Ml.

7. 1 Ml = Minimum Increment = RTOT/31.

8. Typical values are for TA = +25°C and nominal supply voltage.

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

X9315

7FN8179.2

December 21, 2009

DC Electrical Specifications (Over recommended operating conditio ns unless otherwise specified.

SYMBOL PARAMETER TEST CONDITIONS

LIMITS

UNIT

MIN

(Note 9) TYP

(Note 8) MAX

(Note 9)

VCC Supply Voltage X9315 4.5 5.5 V

X9315-2.7 2.7 5.5 V

ICC1 VCC active current (Increment) CS = VIL, U/D = VIL or VIH and INC = 0.4V

@ max. tCYC 80 µA

ICC2 VCC active current (Store) (EEPROM

Store) CS = VIH, U/D = VIL or VIH and INC = VIH @

max. tWR 400 µA

ISB Standby supply current CS = VCC - 0.3V , U/D and INC = VSS or VCC

- 0.3V 5µA

ILI CS, INC, U/D input leakage current VIN = VSS to VCC -10 +10 µA

VIH CS, INC, U/D input HIGH voltage VCC x 0.7 VCC + 0.5 V

VIL CS, INC, U/D input LOW voltage -0.5 VCC x 0.1 V

CIN CS, INC, U/D input capacitance VCC = 5V, VIN = VSS, T A= +25°C, f = 1MHz 10 pF

Endurance and Data Retention

PARAMETER MIN UNIT

Minimum endurance 100,000 Data changes per bit

Data retention 100 Years

Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macro Model

Test Point

VW/RW

VH/RH

VL/RL

Force

Current

Test Point

VH/RH

VW/RW

VL/RL

10pF

RHRL

RTOTAL

25pF

AC Conditions of Test

Input pulse levels 0V to 3V

Input rise and fall times 10ns

Input reference levels 1.5V

AC Electrical Specifications (Over recommended operating conditions unless otherwise specified)

SYMBOL PARAMETER

LIMITS

UNIT

MIN

(Note 9) TYP

(Note 8) MAX

(Note 9)

tCl CS to INC setup 100 ns

tlD INC HIGH to U/D change 100 ns

tDI U/D to INC setup 2.9 µs

tlL INC LOW period 1 µs

tlH INC HIGH period 1 µs

X9315

8FN8179.2

December 21, 2009

AC Timing

NOTE:

11. MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.

tlC INC Inactive to CS inactive 1 µs

tCPH CS Deselect time (NO STORE) 100 ns

tCPH CS Deselect time (STORE) 10 ms

tIW INC to Vw change 1 5 µs

tCYC INC cycle time 4 µs

tR, tF

(Note 10) INC input rise and fall time 500 µs

tPU

(Note 10) Power-up to wiper stable 5µs

tR VCC

(Note 10) VCC power-up rate 0.2 50 V/ms

tWR Store cycle 510ms

NOTE:

10. This parameter is not 100% tested.

AC Electrical Specifications (Over recommended operating conditions unless otherwise specified) (Continued)

SYMBOL PARAMETER

LIMITS

UNIT

MIN

(Note 9) TYP

(Note 8) MAX

(Note 9)

INC

U/D

tCI tIL tIH

tCYC

tID DI

tIW

MI (Note 9)

tIC tCPH

tFtR

10%

90% 90%

(Store)

X9315

9FN8179.2

December 21, 2009

Symbol Table

Performance Characteristics (Typical)

Typical Noise

WAVEFORM INPUTS OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

0 102030405060708090100

Frequency (kHz)

Noise (dB)

110 120 130 140 150 160 170 180 190 200

X9315

10 FN8179.2

December 21, 2009

Typical Rtotal vs. Temperature

Typical Total Resistance Temperature Coefficient

Typical Wiper Resistance

10000

9800

9600

9400

9200

9000

8800

8600

8400

8200

8000

Rtotal

-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75

Temperature

85 95 105 115 125 C°

-55

-350

-300

-250

-200

-150

-100

-50

-45 -35 -25 -15 -5 5 15 25 35

Temperature

PPM

45 55 65 75 85 95 105 115 125 °C

100

200

300

400

Rw (Ω)

500

600

700

800

2 4 6 8 10 12 14 16

Tap

18 20 22 24 26 28 30 32 VCC = 2.7V

X9315

11 FN8179.2

December 21, 2009

Typical Absolute% Error per Tap Position

Typical Relative% Error per Tap Position

Applications Information

Electronic digitally controlled (XDCP) potentiometers provide

three powerful application advantages; (1) the variability and

reliability of a solid-state potentiometer, (2) the flexibility of

computer-based digital controls, and (3) the retentivity of

nonvolatile memory used for the storage of mu ltiple

potentiometer settings or da ta.

40.0%

30.0%

20.0%

10.0%

0.0%

-10.0%

-20.0%

-30.0%

-40.0%

0 3 6 9 12 15

Tap

Absolute% Error

18 21 24 27 30

20.0%

15.0%

10.0%

5.0%

0.0%

-5.0%

-10.0%

-15.0%

-20.0%

03691215

Relative% Error

18 21 24 27 30

Tap

X9315

12 FN8179.2

December 21, 2009

Basic Configurations of Electronic Potentiometers

Basic Circuits

VW/RW

Three terminal potentiometer;

variable voltage divider Two terminal variable resistor;

variable current

Cascading TechniquesBuffered Reference Voltage

–

+5V

-5V

VREF VOUT

OP-07

RW/VW

+V +V

(a) (b)

VOUT = VW/RW

Noninverting Amplifier

–

VO = (1 + R2/R1)VS

LM308A

Voltage Regulator

Iadj

VO (REG) = 1.25V (1 + R2/R1) + Iadj R2

VO (REG)VIN 317

Comparator with Hysteresis

VUL = {R1/(R1 + R2)} VO(max)

VLL = {R1/(R1 + R2)} VO(min)

–

VSVO

}

LT311A

+5V

-5V

(for additional circuits see AN115)

X9315

13 FN8179.2

December 21, 2009

X9315

Mini Small Outline Plastic Packages (MSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

and are measured at Datum Plane. Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

0.25

(0.010)

4X θ

GAUGE

PLANE

SEATING

PLANE

EE1

TOP VIEW

INDEX

AREA

-C-

-B-

0.20 (0.008) ABC

SEATING

PLANE

0.20 (0.008) C

0.10 (0.004) C

-A-

-H-

SIDE VIEW

-B-

END VIEW

0.20 (0.008) CD

- H -

-A - - B -

- H -

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.010 0.014 0.25 0.36 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.026 BSC 0.65 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N8 87

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

o15o5o15o-

α0o6o0o6o-

Rev. 2 01/03

14 FN8179.2

December 21, 2009

X9315

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

Unless otherwise specified, tolerance : Decimal ± 0.05

The pin #1 identifier may be either a mold or mark feature.

Interlead flash or protrusions shall not exceed 0.25mm per side.

Dimension does not include interlead flash or protrusions.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Dimensions are in millimeters.1.

NOTES:

DETAIL "A"

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

0.25 AMC B

0.10 C

ID MARK

PIN NO.1

(0.35) x 45°

SEATING PLANE

GAUGE PLANE

0.25

(5.40)

(1.50)

4.90 ± 0.10

3.90 ± 0.10

1.27 0.43 ± 0.076

0.63 ±0.23

4° ± 4°

DETAIL "A" 0.22 ± 0.03

0.175 ± 0.075

1.45 ± 0.1

1.75 MAX

(1.27) (0.60)

6.0 ± 0.20

Reference to JEDEC MS-012.

SIDE VIEW “B”

15 FN8179.2

December 21, 2009

X9315

Plastic Dual-In-Line Packages (PDIP)

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

Rev. B 2/99

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

NOTE 5

SEATING

PLANE

PIN #1

INDEX

12 N/2

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8179.2

December 21, 2009

X9315

Small Outline Plastic Packages (SOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05