2Gb: x4, x8, x16 DDR3 SDRAM Features DDR3 SDRAM MT41J512M4 - 64 Meg x 4 x 8 Banks MT41J256M8 - 32 Meg x 8 x 8 Banks MT41J128M16 - 16 Meg x 16 x 8 Banks Options1 Features * * * * * * * * * * * * * * * * * * * * Configuration - 512 Meg x 4 - 256 Meg x 8 - 128 Meg x 16 * FBGA package (Pb-free) - x4, x8 - 78-ball (8mm x 10.5mm) Rev. H - 78-ball (9mm x 11.5mm) Rev. D - 82-ball (12.5mm x 15mm) Rev. A * FBGA package (Pb-free) - x16 - 96-ball (9mm x 14mm) Rev. D * Timing - cycle time - 1.07ns @ CL = 13 (DDR3-1866) - 1.25ns @ CL = 11 (DDR3-1600) - 1.5ns @ CL = 10 (DDR3-1333) - 1.5ns @ CL = 9 (DDR3-1333) - 1.87ns @ CL = 8 (DDR3-1066) - 1.87ns @ CL = 7 (DDR3-1066) * Operating temperature - Commercial (0C TC +95C) - Industrial (-40C TC +95C) * Revision VDD = VDDQ = +1.5V 0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals CAS READ latency (CL): 5, 6, 7, 8, 9, 10, or 11 POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2 CAS WRITE latency (CWL): 5, 6, 7, 8, based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 0C to +95C - 64ms, 8192 cycle refresh at 0C to +85C - 32ms, 8192 cycle refresh at +85C to +95C Clock frequency range of 300-800 MHz Self refresh temperature (SRT) Write leveling Multipurpose register Output driver calibration Note: Marking 512M4 256M8 128M16 DA HX JE HA -107 -125 -15 -15E -187 -187E None IT :A/:D/:H 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -1071, 2 1866 13-13-13 13.91 13.91 13.91 -1251, 2 1600 11-11-11 13.75 13.75 13.75 -153 1333 10-10-10 15 15 15 -15E1 1333 9-9-9 13.5 13.5 13.5 -187 1066 8-8-8 15 15 15 -187E 1066 7-7-7 13.1 13.1 13.1 Notes: tRCD (ns) tRP (ns) CL (ns) 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1066, CL = 8 (-187). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x4, x8, x16 DDR3 SDRAM Features Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K 32K (A[14:0]) 32K (A[14:0]) 16K (A[13:0]) Row addressing Bank addressing Column addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Figure 1: DDR3 Part Numbers Example Part Number: MT41J256M8JE-15:D Configuration Package Speed Revision { MT41J : :D Revision Temperature Configuration 512 Meg x 4 512M4 Commercial 256 Meg x 8 256M8 Industrial temperature 128 Meg x 16 128M16 -107 Package 82-ball 12.5mm x 15mm FBGA JE -125 IT Speed Grade tCK = 1.07ns, CL = 13 tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 10 78-ball 9mm x 11.5mm FBGA HX -15 78-ball 8mm x 10.5mm FBGA DA -15E 96-ball 9mm x 14mm FBGA HA -187 tCK = 1.5ns, CL = 9 tCK = 1.87ns, CL = 8 -187E tCK = 1.87ns, CL = 7 Note: None 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron's Web site: http://www.micron.com. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Industrial Temperature .............................................................................................................................. 12 General Notes ............................................................................................................................................ 12 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ...................................................................................................................................... 25 Electrical Specifications .................................................................................................................................. 29 Absolute Ratings ........................................................................................................................................ 29 Input/Output Capacitance ......................................................................................................................... 30 Thermal Characteristics .................................................................................................................................. 31 Electrical Specifications - IDD Specifications and Conditions Definitions .......................................................... 32 Electrical Characteristics - IDD Specifications .................................................................................................. 43 Electrical Specifications - DC and AC .............................................................................................................. 48 DC Operating Conditions ........................................................................................................................... 48 Input Operating Conditions ........................................................................................................................ 48 AC Overshoot/Undershoot Specification ..................................................................................................... 51 Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 54 Slew Rate Definitions for Differential Input Signals ...................................................................................... 56 ODT Characteristics ....................................................................................................................................... 57 ODT Resistors ............................................................................................................................................ 57 ODT Sensitivity .......................................................................................................................................... 59 ODT Timing Definitions ............................................................................................................................. 59 Output Driver Impedance ............................................................................................................................... 63 34 Ohm Output Driver Impedance .............................................................................................................. 64 34 Ohm Driver ............................................................................................................................................ 65 34 Ohm Output Driver Sensitivity ................................................................................................................ 66 Alternative 40 Ohm Driver .......................................................................................................................... 67 40 Ohm Output Driver Sensitivity ................................................................................................................ 67 Output Characteristics and Operating Conditions ........................................................................................... 69 Reference Output Load ............................................................................................................................... 71 Slew Rate Definitions for Single-Ended Output Signals ................................................................................ 72 Slew Rate Definitions for Differential Output Signals ................................................................................... 73 Speed Bin Tables ............................................................................................................................................ 74 Electrical Characteristics and AC Operating Conditions ................................................................................... 78 Command and Address Setup, Hold, and Derating .......................................................................................... 97 Data Setup, Hold, and Derating ..................................................................................................................... 105 Commands - Truth Tables ............................................................................................................................. 112 Commands ................................................................................................................................................... 115 DESELECT ................................................................................................................................................ 115 NO OPERATION ........................................................................................................................................ 115 ZQ CALIBRATION LONG ........................................................................................................................... 115 ZQ CALIBRATION SHORT ......................................................................................................................... 115 ACTIVATE ................................................................................................................................................. 115 READ ........................................................................................................................................................ 115 WRITE ...................................................................................................................................................... 116 PRECHARGE ............................................................................................................................................. 116 REFRESH .................................................................................................................................................. 117 SELF REFRESH .......................................................................................................................................... 118 DLL Disable Mode ..................................................................................................................................... 119 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - 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K 04/10 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change ...................................................................................................................... 123 Write Leveling ............................................................................................................................................... 125 Write Leveling Procedure ........................................................................................................................... 127 Write Leveling Mode Exit Procedure ........................................................................................................... 129 Initialization ................................................................................................................................................. 130 Mode Registers .............................................................................................................................................. 132 Mode Register 0 (MR0) .................................................................................................................................. 133 Burst Length ............................................................................................................................................. 133 Burst Type ................................................................................................................................................ 134 DLL RESET ................................................................................................................................................ 135 Write Recovery .......................................................................................................................................... 135 Precharge Power-Down (Precharge PD) ..................................................................................................... 136 CAS Latency (CL) ....................................................................................................................................... 136 Mode Register 1 (MR1) .................................................................................................................................. 137 DLL Enable/DLL Disable ........................................................................................................................... 137 Output Drive Strength ............................................................................................................................... 138 OUTPUT ENABLE/DISABLE ...................................................................................................................... 138 TDQS Enable ............................................................................................................................................. 138 On-Die Termination .................................................................................................................................. 139 WRITE LEVELING ..................................................................................................................................... 139 POSTED CAS ADDITIVE Latency ................................................................................................................ 139 Mode Register 2 (MR2) .................................................................................................................................. 141 CAS Write Latency (CWL) ........................................................................................................................... 141 AUTO SELF REFRESH (ASR) ...................................................................................................................... 142 SELF REFRESH TEMPERATURE (SRT) ....................................................................................................... 142 SRT vs. ASR ............................................................................................................................................... 143 DYNAMIC ODT ......................................................................................................................................... 143 Mode Register 3 (MR3) .................................................................................................................................. 144 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 144 MPR Functional Description ...................................................................................................................... 145 MPR Register Address Definitions and Bursting Order ................................................................................ 146 MPR Read Predefined Pattern .................................................................................................................... 151 MODE REGISTER SET (MRS) Command ........................................................................................................ 151 ZQ CALIBRATION Operation ......................................................................................................................... 152 ACTIVATE Operation ..................................................................................................................................... 153 READ Operation ............................................................................................................................................ 155 WRITE Operation .......................................................................................................................................... 166 DQ Input Timing ....................................................................................................................................... 174 PRECHARGE Operation ................................................................................................................................. 176 SELF REFRESH Operation ............................................................................................................................. 176 Extended Temperature Usage ........................................................................................................................ 178 Power-Down Mode ....................................................................................................................................... 179 RESET Operation ........................................................................................................................................... 187 On-Die Termination (ODT) ........................................................................................................................... 189 Functional Representation of ODT ............................................................................................................. 189 Nominal ODT ........................................................................................................................................... 189 Dynamic ODT ............................................................................................................................................... 191 Functional Description .............................................................................................................................. 191 Synchronous ODT Mode ............................................................................................................................... 196 ODT Latency and Posted ODT ................................................................................................................... 196 Timing Parameters .................................................................................................................................... 196 ODT Off During READs .............................................................................................................................. 199 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode .............................................................................................................................. 201 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) ................................................. 203 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ....................................................... 205 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ..................................................... 207 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM List of Tables Table 1: Key Timing Parameters ...................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions .............................................................................................. 19 Table 4: 82-Ball FBGA (x4, x8) ........................................................................................................................ 21 Table 5: 96-Ball FBGA - x16 Ball Descriptions ................................................................................................. 23 Table 6: Absolute Maximum Ratings .............................................................................................................. 29 Table 7: Input/Output Capacitance ............................................................................................................... 30 Table 8: Thermal Characteristics .................................................................................................................... 31 Table 9: Timing Parameters Used for IDD Measurements - Clock Units ........................................................... 32 Table 10: IDD0 Measurement Loop ................................................................................................................. 33 Table 11: IDD1 Measurement Loop ................................................................................................................. 34 Table 12: IDD Measurement Conditions for Power-Down Currents .................................................................. 35 Table 13: IDD2N and IDD3N Measurement Loop ................................................................................................ 36 Table 14: IDD2NT Measurement Loop .............................................................................................................. 36 Table 15: IDD4R Measurement Loop ................................................................................................................ 37 Table 16: IDD4W Measurement Loop ............................................................................................................... 38 Table 17: IDD5B Measurement Loop ................................................................................................................ 39 Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 40 Table 19: IDD7 Measurement Loop ................................................................................................................. 41 Table 20: IDD Maximum Limits - Die Rev A ..................................................................................................... 43 Table 21: IDD Maximum Limits - Die Rev D .................................................................................................... 45 Table 22: IDD Maximum Limits - Die Rev H .................................................................................................... 47 Table 23: DC Electrical Characteristics and Operating Conditions ................................................................... 48 Table 24: DC Electrical Characteristics and Input Conditions .......................................................................... 48 Table 25: Input Switching Conditions ............................................................................................................ 49 Table 26: Control and Address Pins ................................................................................................................ 51 Table 27: Clock, Data, Strobe, and Mask Pins ................................................................................................. 51 Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 52 Table 29: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# .............................................. 53 Table 30: Single-Ended Input Slew Rate Definition ......................................................................................... 54 Table 31: Differential Input Slew Rate Definition ............................................................................................ 56 Table 32: On-Die Termination DC Electrical Characteristics ........................................................................... 57 Table 33: RTT Effective Impedances ................................................................................................................ 58 Table 34: ODT Sensitivity Definition .............................................................................................................. 59 Table 35: ODT Temperature and Voltage Sensitivity ....................................................................................... 59 Table 36: ODT Timing Definitions ................................................................................................................. 60 Table 37: Reference Settings for ODT Timing Measurements .......................................................................... 60 Table 38: 34 Ohm Driver Impedance Characteristics ...................................................................................... 64 Table 39: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ...................................................... 65 Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V ................................................................ 65 Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V ............................................................ 65 Table 42: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V ............................................................ 66 Table 43: 34 Ohm Output Driver Sensitivity Definition ................................................................................... 66 Table 44: 34 Ohm Output Driver Voltage and Temperature Sensitivity ............................................................ 66 Table 45: 40 Ohm Driver Impedance Characteristics ...................................................................................... 67 Table 46: 40 Ohm Output Driver Sensitivity Definition ................................................................................... 67 Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity ............................................................ 68 Table 48: Single-Ended Output Driver Characteristics .................................................................................... 69 Table 49: Differential Output Driver Characteristics ....................................................................................... 70 Table 50: Single-Ended Output Slew Rate Definition ...................................................................................... 72 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - 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K 04/10 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: Table 86: Table 87: Table 88: Table 89: Table 90: Differential Output Slew Rate Definition ......................................................................................... 73 DDR3-1066 Speed Bins ................................................................................................................... 74 DDR3-1333 Speed Bins ................................................................................................................... 75 DDR3-1600 Speed Bins ................................................................................................................... 76 DDR3-1866 Speed Bins ................................................................................................................... 77 Electrical Characteristics and AC Operating Conditions ................................................................... 78 Electrical Characteristics and AC Operating Conditions for Speed Extensions ................................... 87 Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based ....................... 97 Derating Values for tIS/tIH - AC175/DC100-Based ........................................................................... 98 Derating Values for tIS/tIH - AC150/DC100-Based ........................................................................... 98 Derating Values for tIS/tIH - AC135/DC100-Based ........................................................................... 99 Derating Values for tIS/tIH - AC125/DC100-Based ........................................................................... 99 Minimum Required Time tVAC Above VIH(AC) for Valid Transition ................................................... 100 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) - AC/DC-Based .................................. 105 Derating Values for tDS/tDH - AC175/DC100-Based ....................................................................... 106 Derating Values for tDS/tDH - AC150/DC100-Based ....................................................................... 106 Derating Values for tDS/tDH - AC135/DC100-Based ....................................................................... 107 Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid Transition ............................................. 107 Truth Table - Command ................................................................................................................ 112 Truth Table - CKE ......................................................................................................................... 114 READ Command Summary ............................................................................................................ 116 WRITE Command Summary .......................................................................................................... 116 READ Electrical Characteristics, DLL Disable Mode ........................................................................ 122 Write Leveling Matrix ..................................................................................................................... 126 Burst Order ................................................................................................................................... 135 MPR Functional Description of MR3 Bits ........................................................................................ 145 MPR Readouts and Burst Order Bit Mapping .................................................................................. 146 Self Refresh Temperature and Auto Self Refresh Description ........................................................... 178 Self Refresh Mode Summary .......................................................................................................... 178 Command to Power-Down Entry Parameters ................................................................................. 179 Power-Down Modes ...................................................................................................................... 180 Truth Table - ODT (Nominal) ........................................................................................................ 190 ODT Parameter ............................................................................................................................. 190 Dynamic ODT Specific Parameters ................................................................................................. 191 Mode Registers for RTT,nom ............................................................................................................. 192 Mode Registers for RTT(WR) ............................................................................................................. 192 Timing Diagrams for Dynamic ODT ............................................................................................... 192 Synchronous ODT Parameters ....................................................................................................... 197 Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 202 ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period .................................. 204 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - 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K 04/10 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM List of Figures Figure 1: DDR3 Part Numbers ......................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14 Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15 Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15 Figure 6: 78-Ball FBGA - x4, x8 (Top View) ...................................................................................................... 16 Figure 7: 82-Ball FBGA - x4, x8 (Top View) ...................................................................................................... 17 Figure 8: 96-Ball FBGA - x16 (Top View) ......................................................................................................... 18 Figure 9: 78-Ball FBGA - x4, x8; "DA" ............................................................................................................. 25 Figure 10: 78-Ball FBGA - x4, x8; "HX" ............................................................................................................ 26 Figure 11: 82-Ball FBGA - x4, x8; "JE" ............................................................................................................. 27 Figure 12: 96-Ball FBGA - x16; "HA" ............................................................................................................... 28 Figure 13: Thermal Measurement Point ......................................................................................................... 31 Figure 14: Input Signal .................................................................................................................................. 50 Figure 15: Overshoot ..................................................................................................................................... 51 Figure 16: Undershoot .................................................................................................................................. 51 Figure 17: VIX for Differential Signals .............................................................................................................. 52 Figure 18: Single-Ended Requirements for Differential Signals ........................................................................ 53 Figure 19: Definition of Differential AC-Swing and tDVAC ............................................................................... 53 Figure 20: Nominal Slew Rate Definition for Single-Ended Input Signals ......................................................... 55 Figure 21: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 56 Figure 22: ODT Levels and I-V Characteristics ................................................................................................ 57 Figure 23: ODT Timing Reference Load .......................................................................................................... 60 Figure 24: tAON and tAOF Definitions ............................................................................................................ 61 Figure 25: tAONPD and tAOFPD Definitions ................................................................................................... 61 Figure 26: tADC Definition ............................................................................................................................. 62 Figure 27: Output Driver ............................................................................................................................... 63 Figure 28: DQ Output Signal .......................................................................................................................... 70 Figure 29: Differential Output Signal .............................................................................................................. 71 Figure 30: Reference Output Load for AC Timing and Output Slew Rate .......................................................... 71 Figure 31: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 72 Figure 32: Nominal Differential Output Slew Rate Definition for DQS, DQS# ................................................... 73 Figure 33: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) ............................................. 101 Figure 34: Nominal Slew Rate for tIH (Command and Address - Clock) .......................................................... 102 Figure 35: Tangent Line for tIS (Command and Address - Clock) .................................................................... 103 Figure 36: Tangent Line for tIH (Command and Address - Clock) ................................................................... 104 Figure 37: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) ........................................................................ 108 Figure 38: Nominal Slew Rate for tDH (DQ - Strobe) ...................................................................................... 109 Figure 39: Tangent Line for tDS (DQ - Strobe) ............................................................................................... 110 Figure 40: Tangent Line for tDH (DQ - Strobe) ............................................................................................... 111 Figure 41: Refresh Mode ............................................................................................................................... 118 Figure 42: DLL Enable Mode to DLL Disable Mode ........................................................................................ 120 Figure 43: DLL Disable Mode to DLL Enable Mode ........................................................................................ 121 Figure 44: DLL Disable tDQSCK Timing ........................................................................................................ 122 Figure 45: Change Frequency During Precharge Power-Down ....................................................................... 124 Figure 46: Write Leveling Concept ................................................................................................................ 125 Figure 47: Write Leveling Sequence ............................................................................................................... 128 Figure 48: Exit Write Leveling ....................................................................................................................... 129 Figure 49: Initialization Sequence ................................................................................................................. 131 Figure 50: MRS to MRS Command Timing (tMRD) ......................................................................................... 132 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - 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K 04/10 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 51: MRS to nonMRS Command Timing (tMOD) .................................................................................. 133 Figure 52: Mode Register 0 (MR0) Definitions ................................................................................................ 134 Figure 53: READ Latency .............................................................................................................................. 136 Figure 54: Mode Register 1 (MR1) Definition ................................................................................................. 137 Figure 55: READ Latency (AL = 5, CL = 6) ....................................................................................................... 140 Figure 56: Mode Register 2 (MR2) Definition ................................................................................................. 141 Figure 57: CAS Write Latency ........................................................................................................................ 142 Figure 58: Mode Register 3 (MR3) Definition ................................................................................................. 144 Figure 59: Multipurpose Register (MPR) Block Diagram ................................................................................. 145 Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 147 Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout ......................... 148 Figure 62: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble ................................... 149 Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble ................................... 150 Figure 64: ZQ Calibration Timing (ZQCL and ZQCS) ...................................................................................... 152 Figure 65: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 153 Figure 66: Example: tFAW ............................................................................................................................. 154 Figure 67: READ Latency .............................................................................................................................. 155 Figure 68: Consecutive READ Bursts (BL8) .................................................................................................... 157 Figure 69: Consecutive READ Bursts (BC4) .................................................................................................... 157 Figure 70: Nonconsecutive READ Bursts ....................................................................................................... 158 Figure 71: READ (BL8) to WRITE (BL8) .......................................................................................................... 158 Figure 72: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 159 Figure 73: READ to PRECHARGE (BL8) ......................................................................................................... 159 Figure 74: READ to PRECHARGE (BC4) ......................................................................................................... 160 Figure 75: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 160 Figure 76: READ with Auto Precharge (AL = 4, CL = 6) .................................................................................... 160 Figure 77: Data Output Timing - tDQSQ and Data Valid Window ................................................................... 162 Figure 78: Data Strobe Timing - READs ......................................................................................................... 163 Figure 79: Method for Calculating tLZ and tHZ .............................................................................................. 164 Figure 80: tRPRE Timing ............................................................................................................................... 164 Figure 81: tRPST Timing ............................................................................................................................... 165 Figure 82: tWPRE Timing .............................................................................................................................. 167 Figure 83: tWPST Timing .............................................................................................................................. 167 Figure 84: WRITE Burst ................................................................................................................................ 168 Figure 85: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 169 Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF ............................................................ 169 Figure 87: Nonconsecutive WRITE to WRITE ................................................................................................. 170 Figure 88: WRITE (BL8) to READ (BL8) .......................................................................................................... 170 Figure 89: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 171 Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 172 Figure 91: WRITE (BL8) to PRECHARGE ........................................................................................................ 173 Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 173 Figure 93: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 174 Figure 94: Data Input Timing ........................................................................................................................ 175 Figure 95: Self Refresh Entry/Exit Timing ...................................................................................................... 177 Figure 96: Active Power-Down Entry and Exit ................................................................................................ 181 Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................ 182 Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ............................................................... 182 Figure 99: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................ 183 Figure 100: Power-Down Entry After WRITE .................................................................................................. 183 Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 184 Figure 102: REFRESH to Power-Down Entry .................................................................................................. 184 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - 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K 04/10 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: Figure 120: Figure 121: ACTIVATE to Power-Down Entry ................................................................................................ 185 PRECHARGE to Power-Down Entry ............................................................................................. 185 MRS Command to Power-Down Entry ........................................................................................ 186 Power-Down Exit to Refresh to Power-Down Entry ...................................................................... 186 RESET Sequence ........................................................................................................................ 188 On-Die Termination ................................................................................................................... 189 Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 193 Dynamic ODT: Without WRITE Command .................................................................................. 193 Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ........... 194 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 ......................... 195 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 ......................... 195 Synchronous ODT ...................................................................................................................... 197 Synchronous ODT (BC4) ............................................................................................................. 198 ODT During READs .................................................................................................................... 200 Asynchronous ODT Timing with Fast ODT Transition .................................................................. 202 Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ........... 204 Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit .............. 206 Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping .................... 208 Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 209 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram CKE L Power applied Reset procedure Power on MRS, MPR, write leveling Initialization SRE ZQCL From any state RESET ZQ calibration Self refresh MRS SRX REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP Writing READ READ AP READ WRITE WRITE AP Reading READ AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Precharging Reading Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 11 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Functional Description Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Industrial Temperature The industrial temperature (IT) device requires that the case temperature not exceed - 40C or +95C. JEDEC specifications require the refresh rate to double when TC exceeds +85C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when TC is < 0C or > +95C. General Notes * The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). * Throughout this data sheet, various figures and text refer to DQs as "DQ." DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. * The terms "DQS" and "CK" found throughout this data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Functional Description * Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. * Any specific requirement takes precedence over a general statement. * Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. * Row addressing is denoted as A[n:0]. For example,1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]; 2Gb: n = 13 [x16] and 2Gb: n = 14 [x4, x8]; . 4Gb: n = 14 [x16] and 4Gb: n = 15 [x4, x8]. * A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: - - - - Connect UDQS to ground via 1K* resistor. Connect UDQS# to VDD via 1K* resistor. Connect UDM to VDD via 1K* resistor. Connect DQ 8-15 individually to either VSS, VDD, or VREF via 1K resistors,* or float DQ 8-15. *If ODT is used, 1K resistor should be changed to 4X that of the selected ODT. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# ZQCL, ZQCS CKE VSSQ To pullup/pulldown networks Control logic A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 18 15 Rowaddress MUX 15 15 Bank 0 rowaddress 32,768 latch and decoder Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 RTT,nom CK,CK# DLL Bank 0 memory array (32,768 x 256 x 32) 32 READ FIFO and data MUX 4 (1 . . . 4) DQ[3:0] READ drivers VDDQ/2 32 8,192 BC4 BC4 OTF I/O gating DM mask logic 3 18 Address register 3 Bank control logic (1, 2) 32 Data interface 4 Data WRITE drivers and input logic 8 DQS, DQS# VDDQ/2 RTT,nom sw1 RTT(WR) sw2 DM 3 Columns 0, 1, and 2 CK,CK# PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN RTT(WR) sw2 sw1 Column decoder Columnaddress counter/ latch RTT,nom DM 256 (x32) 11 DQ[3:0] DQS, DQS# Sense amplifiers A[14:0] BA[2:0] RTT(WR) sw2 sw1 14 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams Figure 4: 256 Meg x 8 Functional Block Diagram ODT control ODT ZQ RZQ Control logic CKE VSSQ To ODT/output drivers ZQ CAL RESET# A12 ZQCL, ZQCS CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 15 Rowaddress MUX 18 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank control logic 3 (1 . . . 8) 8 DQ[7:0] DQS, DQS# VDDQ/2 BC4 BC4 OTF RTT,nom sw1 RTT(WR) sw2 (1, 2) (128 x64) 64 8 Data interface Data Column decoder Columnaddress counter/ latch 10 TDQS# DQ[7:0] Read drivers I/O gating DM mask logic 3 Address register sw2 DQ8 READ FIFO and data MUX 64 8,192 18 CK, CK# DLL 64 Sense amplifiers A[14:0] BA[2:0] RTT(WR) RTT,nom sw1 Bank 0 Memory array (32,768 x 128 x 64) Bank 0 rowaddress 32,768 latch and decoder 15 Columns 0, 1, and 2 Write drivers and input logic VDDQ/2 RTT,nom sw1 RTT(WR) sw2 7 3 DQS/DQS# DM/TDQS (shared pin) Columns 0, 1, and 2 CK, CK# Column 2 (select upper or lower nibble for BC4) Figure 5: 128 Meg x 16 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# Control logic CKE VSSQ To ODT/output drivers ZQCL, ZQCS A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 17 13 Rowaddress MUX 14 14 Bank 0 rowaddress latch and decoder 16,384 RTT,nom Column 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 CK, CK# DLL (1 . . . 16) Bank 0 memory array (16,384 x 128 x 128) 128 READ FIFO and data MUX 16 DQ[15:0] READ drivers LDQS, LDQS#, UDQS, UDQS# A[13:0] BA[2:0] 17 Address register 3 BC4 128 16,384 Data interface 16 Data WRITE drivers and input logic 7 3 UDQS, UDQS# VDDQ/2 128 RTT,nom sw1 RTT(WR) sw2 (1, 2) LDM/UDM Columns 0, 1, and 2 CK, CK# PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN sw2 LDQS, LDQS# Column decoder Columnaddress counter/ latch RTT(WR) (1 . . . 4) (128 x128) 10 RTT,nom sw1 BC4 OTF I/O gating DM mask logic Bank control logic DQ[15:0] VDDQ/2 Sense amplifiers 3 RTT(WR) sw2 sw1 15 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA - x4, x8 (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. Ball descriptions listed in Table 3 (page 19) are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 3). 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 7: 82-Ball FBGA - x4, x8 (Top View) 1 2 3 4 8 9 10 11 NC VSS VDD NC NF, NF/TDQS# VSS VDD NC VSS VSSQ DQ0 DM,DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ VSSQ NF, DQ6 DQS# VDD VSS VSSQ 5 6 7 A B C D E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N NC Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN NC 1. Ball descriptions listed in Table 4 (page 21) are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 4). 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Figure 8: 96-Ball FBGA - x16 (Top View) A B 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 NC A8 VSS C D E F G H J K L M N P R T Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. Ball descriptions listed in Table 5 (page 23) are listed as "x4, x8" if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only--selectable between NF or TDQS# via MRS (symbols are defined in Table 5). 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/ BC#, A13, A14 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 112). BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA - x4, x8 Ball Descriptions (Continued) Symbol Type DQ[3:0] I/O Description Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. VDD Supply Power supply: 1.5V 0.075V. VDDQ Supply DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF - No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 4: 82-Ball FBGA (x4, x8) Symbol Type Description A0, A1, A2, A3 A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/ BC#, A13, A14 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-thefly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 112). BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 4: 82-Ball FBGA (x4, x8) (Continued) Symbol Type DQ[3:0] I/O Description Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. VDD Supply Power supply: 1.5V 0.075V. VDDQ Supply DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference NC - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF - No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 5: 96-Ball FBGA - x16 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/ BC#, A13 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 112). BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/ TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VDD and DC LOW 0.2 x VDDQ. RESET# assertion and desertion are asynchronous. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions Table 5: 96-Ball FBGA - x16 Ball Descriptions (Continued) Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. VDD Supply Power supply: 1.5V 0.075V. VDDQ Supply DQ power supply: 1.5V 0.075V. Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240 resistor (RZQ), which is tied to VSSQ. NC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN - No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Package Dimensions Figure 9: 78-Ball FBGA - x4, x8; "DA" 0.8 0.05 0.155 Seating Plane 0.12 A 1.8 CTR Nonconductive overmold A 78X O0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow 9 8 7 on O0.35 SMD ball pads. Ball A1 ID 3 2 1 A B C D E F G H J K L M N 9.6 CTR 0.8 TYP Ball A1 ID 10.5 0.1 0.8 TYP 1.2 MAX 6.4 CTR 0.25 MIN 8 0.1 Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. All dimensions are in millimeters. 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 10: 78-Ball FBGA - x4, x8; "HX" 0.155 Seating plane 1.8 CTR Nonconductive overmold 78X O0.45 Dimensions apply to solder balls post-reflow on O0.35 SMD ball pads. A 0.12 A Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H 11.5 0.1 9.6 CTR J K L M N 0.8 TYP 0.8 TYP 1.1 0.1 6.4 CTR 0.25 MIN 9 0.1 Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. All dimensions are in millimeters. 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 11: 82-Ball FBGA - x4, x8; "JE" Seating plane 0.12 A A 82X O0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on O0.33 NSMD ball pads. 0.75 0.1 Ball A1 ID 11 10 9 8 4 3 2 Ball A1 ID 1 A B C D 0.8 TYP E F 15 0.15 G 9.6 CTR H J K L M N 0.8 TYP 1.2 MAX 0.25 MIN 8 CTR 12.5 0.15 Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. All dimensions are in millimeters. 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions Figure 12: 96-Ball FBGA - x16; "HA" 0.8 0.1 Seating plane 0.12 A A 96X O0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow on O0.35 SMD ball pads. Ball A1 ID 9 8 7 3 2 Ball A1 ID 1 A B C D E F G H 12 CTR J 14 0.15 K L M N P R 0.8 TYP T 0.8 TYP 1.2 MAX 6.4 CTR 0.25 MIN 9 0.15 Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. All dimensions are in millimeters. 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 6: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDD supply voltage relative to VSS -0.4 1.975 V 1 VDDQ VDD supply voltage relative to VSSQ -0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS -0.4 1.975 V TC Operating case temperature 0 95 C TSTG Storage temperature -55 150 C Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 2, 3 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 x VDDQ. When VDD and VDDQ are less than 500mV, VREF may be 300mV. 2. MAX operating case temperature. TC is measured in the center of the package. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications Input/Output Capacitance Table 7: Input/Output Capacitance Note 1 applies to the entire table DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Capacitance Parameters Symbol Min Max Min Max Min Max Min Max Min Max Units Notes CK and CK# CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pF C: CK to CK# CDCK 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pF Single-end I/O: DQ, DM CIO 1.5 3.0 1.5 3.0 1.5 2.5 1.5 2.3 1.4 2.2 pF 2 Differential I/O: DQS, DQS#, TDQS, TDQS# CIO 1.5 3.0 1.5 3.0 1.5 2.5 1.5 2.3 1.4 2.2 pF 3 CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pF 3 CDIO -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 4 CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.3 pF 5 C: DQS to DQS#, TDQS, TDQS# C: DQ to DQS Inputs (CTRL, CMD, ADDR) C: CTRL to CK CDI_CTRL -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pF 6 CDI_CMD_ADDR -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.5 0.3 pF 7 ZQ pin capacitance CZO - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 pF Reset pin capacitance CRE - 3.0 - 3.0 - 3.0 - 3.0 - 3.0 pF C: CMD_ADDR to CK Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. VDD = +1.5V 0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25C. VOUT(DC) = 0.5 x VDDQ, VOUT (peak-to-peak) = 0.1V. 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 3. Includes TDQS, TDQS#. Cddqs is for DQS vs. DQS# and TDQS vs. TDQS# separately. 4. CDIO = CIO (DQ) - 0.5 x (CIO [DQS] + CIO [DQS#]). 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n: 0], BA[2:0]. 6. CDI_CTRL = CI (CTRL) - 0.5 x (CCK [CK] + CCK [CK#]). 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 x (CCK [CK] + CCK [CK#]). 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Thermal Characteristics Thermal Characteristics Table 8: Thermal Characteristics Parameter/Condition Operating case temperature Junction-to-case (TOP) Value Units Symbol Notes 0 to +85 C TC 1, 2, 3 0 to +95 C TC 1, 2, 3, 4 78-ball "HX" 3.9 C/W JC 5 78-ball "DA" tbd 82-ball "JE" 1.6 96-ball "HA" tbd 1. MAX operating case temperature. TC is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds +85C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9s interval refresh rate. The use of SRT or ASR (if available) must be enabled. 5. The thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. Notes: Figure 13: Thermal Measurement Point (L/2) Tc test point L (W/2) W PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Electrical Specifications - IDD Specifications and Conditions Definitions Within the following IDD measurement tables, the following definitions and conditions are used, unless stated otherwise: * * * * * * * * * * * * * * * * LOW: VIN VIL(AC)max; HIGH: VIN VIH(AC)min Midlevel: Inputs are VREF = VDD/2 RON set to RZQ/7 (34) RTT,nom set to RZQ/6 (40) RTT(WR) set to RZQ/2 (120) Qoff is enabled in MR1 ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR)) TDQS is disabled in MR1 External DQ/DQS/DM load resister is 25 to VDDQ/2 Burst lengths are BL8 fixed AL equals 0 (except in IDD7) IDD specifications are tested after the device is properly initialized Input slew rate is specified by AC parametric test conditions Optional ASR is disabled Read burst type uses nibble sequential (MR0 [3] 0) Loop patterns must be executed at least once before current measurements begin Table 9: Timing Parameters Used for IDD Measurements - Clock Units DDR3-800 IDD Parameter tCK DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 -25E -25 -187E -187 -15E -15 -125E -125 -107 5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 13-13-13 Units 1.07 ns (MIN) IDD 2.5 1.875 1.5 1.25 CL IDD 5 6 7 8 9 10 10 11 13 CK tRCD (MIN) 5 6 7 8 9 10 10 11 13 CK (MIN) IDD 20 21 27 28 33 34 38 39 45 CK 15 15 20 20 24 24 28 28 32 CK IDD tRC tRAS (MIN) IDD tRP (MIN) tFAW 5 6 7 8 9 10 10 11 13 CK x4, x8 16 16 20 20 20 20 24 24 26 CK x16 20 20 27 27 30 30 32 32 33 CK tRRD x4, x8 4 4 4 4 4 4 5 5 5 CK IDD x16 4 4 6 6 5 5 6 6 6 CK tRFC 1Gb 44 44 59 59 74 74 88 88 103 CK 2Gb 64 64 86 86 107 107 128 128 150 CK 4Gb 120 120 160 160 200 200 240 240 281 CK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Sub-loop CKE CK, CK# Table 10: IDD0 Measurement Loop 0 ACT 0 0 1 1 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 0 0 0 0 0 0 0 0 0 0 - 3 D# 1 1 1 1 0 0 0 0 0 0 0 - 4 D# 1 1 1 1 0 0 0 0 0 0 0 - nRAS PRE Repeat cycles 1 through 4 until nRAS - 1, truncate if needed Static HIGH Toggling 0 0 0 1 0 0 0 0 0 0 0 0 - Repeat cycles 1 through 4 until nRC - 1, truncate if needed nRC ACT 0 0 1 1 0 0 0 0 0 F 0 - nRC + 1 D 1 0 0 0 0 0 0 0 0 F 0 - nRC + 2 D 1 0 0 0 0 0 0 0 0 F 0 - nRC + 3 D# 1 1 1 1 0 0 0 0 0 F 0 - nRC + 4 D# 1 1 1 1 0 0 0 0 0 F 0 - Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1, truncate if needed nRC + nRAS PRE 0 0 1 0 0 0 0 0 0 F 0 - Repeat cycles nRC + 1 through nRC + 4 until 2 x RC - 1, truncate if needed 1 2 x nRC Repeat sub-loop 0, use BA[2:0] = 1 2 4 x nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 x nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 x nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 x nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 x nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 x nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. Only selected bank (single) active. 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2 Sub-loop CKE CK, CK# Table 11: IDD1 Measurement Loop 0 ACT 0 0 1 1 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 0 0 0 0 0 0 0 0 0 0 - 3 D# 1 1 1 1 0 0 0 0 0 0 0 - 4 D# 1 1 1 1 0 0 0 0 0 0 0 - nRCD RD Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 1 0 0 0 0 0 0 0 00000000 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed Static HIGH Toggling 0 0 0 1 0 0 0 0 0 0 0 - nRAS PRE 0 nRC ACT 0 0 1 1 0 0 0 0 0 F 0 - nRC + 1 D 1 0 0 0 0 0 0 0 0 F 0 - nRC + 2 D 1 0 0 0 0 0 0 0 0 F 0 - nRC + 3 D# 1 1 1 1 0 0 0 0 0 F 0 - nRC + 4 D# 1 1 1 1 0 0 0 0 0 F 0 - Repeat cycles 1 through 4 until nRC - 1, truncate if needed Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed nRC + nRCD RD 0 nRC + nRAS PRE 1 0 1 0 0 0 0 0 F 0 00110011 Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 0 0 1 0 0 0 0 0 0 F 0 - Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed 1 2 x nRC Repeat sub-loop 0, use BA[2:0] = 1 2 4 x nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 x nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 x nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 x nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 x nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 x nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. 2. 3. 4. DQ, DQS, DQS# are midlevel unless driven as required by the RD command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. Only selected bank (single) active. 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Table 12: IDD Measurement Conditions for Power-Down Currents Name IDD2P0 Precharge Power-Down Current (Slow Exit)1 IDD2P1 Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD3P Active Power-Down Current n/a n/a n/a n/a Timing pattern CKE External clock tCK LOW LOW HIGH LOW Toggling Toggling Toggling Toggling tCK (MIN) IDD tCK(MIN) IDD tCK(MIN) IDD tCK (MIN) IDD tRC n/a n/a n/a n/a tRAS n/a n/a n/a n/a tRCD n/a n/a n/a n/a tRRD n/a n/a n/a n/a tRC n/a n/a n/a n/a CL n/a n/a n/a n/a AL n/a n/a n/a n/a CS# HIGH HIGH HIGH HIGH Command inputs LOW LOW LOW LOW Row/column addr LOW LOW LOW LOW Bank addresses LOW LOW LOW LOW DM LOW LOW LOW LOW Midlevel Midlevel Midlevel Midlevel Data I/O Output buffer DQ, DQS Enabled Enabled Enabled Enabled Enabled, off Enabled, off Enabled, off Enabled, off Burst length 8 8 8 8 Active banks None None None All ODT2 Idle banks All All All None Special notes n/a n/a n/a n/a Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. "Enabled, off" means the MR bits are enabled, but the signal is LOW. 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Sub-loop CKE CK, CK# Table 13: IDD2N and IDD3N Measurement Loop 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D# 1 1 1 1 0 0 0 0 0 F 0 - 3 D# 1 1 1 1 0 0 0 0 0 F 0 - Static HIGH Toggling 0 1 4-7 Repeat sub-loop 0, use BA[2:0] = 1 2 8-11 Repeat sub-loop 0, use BA[2:0] = 2 3 12-15 Repeat sub-loop 0, use BA[2:0] = 3 4 16-19 Repeat sub-loop 0, use BA[2:0] = 4 5 20-23 Repeat sub-loop 0, use BA[2:0] = 5 6 24-27 Repeat sub-loop 0, use BA[2:0] = 6 7 28-31 Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed during IDD2N, all banks open during IDD3N. Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Sub-loop CKE CK, CK# Table 14: IDD2NT Measurement Loop 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D# 1 1 1 1 0 0 0 0 0 F 0 - 3 D# 1 1 1 1 0 0 0 0 0 F 0 - Static HIGH Toggling 0 1 4-7 Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0 2 8-11 Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1 3 12-15 Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1 4 16-19 Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0 5 20-23 Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0 6 24-27 Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1 7 28-31 Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed. 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Sub-loop CKE CK, CK# Table 15: IDD4R Measurement Loop 0 RD 0 1 0 1 0 0 0 0 0 0 0 00000000 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D# 1 1 1 1 0 0 0 0 0 0 0 - 3 D# 1 1 1 1 0 0 0 0 0 0 0 - 4 RD 0 1 0 1 0 0 0 0 0 F 0 00110011 5 D 1 0 0 0 0 0 0 0 0 F 0 - 6 D# 1 1 1 1 0 0 0 0 0 F 0 - 7 D# 1 1 1 1 0 0 0 0 0 F 0 - Static HIGH Toggling 0 1 8-15 Repeat sub-loop 0, use BA[2:0] = 1 2 16-23 Repeat sub-loop 0, use BA[2:0] = 2 3 24-31 Repeat sub-loop 0, use BA[2:0] = 3 4 32-39 Repeat sub-loop 0, use BA[2:0] = 4 5 40-47 Repeat sub-loop 0, use BA[2:0] = 5 6 48-55 Repeat sub-loop 0, use BA[2:0] = 6 7 56-63 Repeat sub-loop 0, use BA[2:0] = 7 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. 2. 3. 4. DQ, DQS, DQS# are midlevel when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. All banks open. 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Sub-loop CKE CK, CK# Table 16: IDD4W Measurement Loop 0 WR 0 1 0 0 1 0 0 0 0 0 0 00000000 1 D 1 0 0 0 1 0 0 0 0 0 0 - 2 D# 1 1 1 1 1 0 0 0 0 0 0 - 3 D# 1 1 1 1 1 0 0 0 0 0 0 - 4 WR 0 1 0 0 1 0 0 0 0 F 0 00110011 5 D 1 0 0 0 1 0 0 0 0 F 0 - 6 D# 1 1 1 1 1 0 0 0 0 F 0 - 7 D# 1 1 1 1 1 0 0 0 0 F 0 - Static HIGH Toggling 0 1 8-15 Repeat sub-loop 0, use BA[2:0] = 1 2 16-23 Repeat sub-loop 0, use BA[2:0] = 2 3 24-31 Repeat sub-loop 0, use BA[2:0] = 3 4 32-39 Repeat sub-loop 0, use BA[2:0] = 4 5 40-47 Repeat sub-loop 0, use BA[2:0] = 5 6 48-55 Repeat sub-loop 0, use BA[2:0] = 6 7 56-63 Repeat sub-loop 0, use BA[2:0] = 7 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. 2. 3. 4. DQ, DQS, DQS# are midlevel when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the WR command. All banks open. 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Sub-loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data CKE CK, CK# Table 17: IDD5B Measurement Loop 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 0 0 0 0 0 0 0 0 0 0 - 3 D# 1 1 1 1 0 0 0 0 0 F 0 - 4 D# 1 1 1 1 0 0 0 0 0 F 0 - Static HIGH Toggling 1a 1b 5-8 Repeat sub-loop 1a, use BA[2:0] = 1 1c 9-12 Repeat sub-loop 1a, use BA[2:0] = 2 1d 13-16 Repeat sub-loop 1a, use BA[2:0] = 3 1e 17-20 Repeat sub-loop 1a, use BA[2:0] = 4 1f 21-24 Repeat sub-loop 1a, use BA[2:0] = 5 1g 25-28 Repeat sub-loop 1a, use BA[2:0] = 6 1h 29-32 Repeat sub-loop 1a, use BA[2:0] = 7 2 33-nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1, truncate if needed Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test IDD6: Self Refresh Current Normal Temperature Range TC = 0C to +85C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0C to +95C IDD8: Reset2 LOW LOW Midlevel CKE External clock Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel tCK n/a n/a n/a tRC n/a n/a n/a tRAS n/a n/a n/a tRCD n/a n/a n/a tRRD n/a n/a n/a tRC n/a n/a n/a CL n/a n/a n/a AL n/a n/a n/a CS# Midlevel Midlevel Midlevel Command inputs Midlevel Midlevel Midlevel Row/column addresses Midlevel Midlevel Midlevel Bank addresses Midlevel Midlevel Midlevel Data I/O Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Midlevel Enabled, midlevel Enabled, midlevel Midlevel Burst length n/a n/a n/a Active banks n/a n/a None Idle banks n/a n/a All SRT disabled (normal) enabled (extended) n/a ASR disabled disabled n/a ODT1 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. "Enabled, midlevel" means the MR command is enabled, but the signal is midlevel. 2. During a cold boot RESET (initialization), current reading is valid once power is stable and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current reading is valid after RESET has been LOW for 200ns + tRFC. 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 0 Cycle Number Sub-loop CKE CK, CK# Table 19: IDD7 Measurement Loop 0 ACT 0 0 1 1 0 0 0 0 0 0 0 - 1 RDA 0 1 0 1 0 0 0 1 0 0 0 00000000 2 D 1 0 0 0 0 0 0 0 0 0 0 - nRRD ACT 0 0 1 1 0 1 0 0 0 F 0 - nRRD + 1 RDA 0 1 0 1 0 1 0 1 0 F 0 00110011 nRRD + 2 D 1 0 0 0 0 1 0 0 0 F 0 - 0 - 3 1 nRRD + 3 Repeat cycle nRRD + 2 until 2 x nRRD - 1 2 2 x nRRD Repeat sub-loop 0, use BA[2:0] = 2 3 3 x nRRD Repeat sub-loop 1, use BA[2:0] = 3 4 x nRRD Static HIGH 4 Toggling Repeat cycle 2 until nRRD - 1 D 1 0 0 0 0 3 0 0 0 F 4 x nRRD + 1 Repeat cycle 4 x nRRD until nFAW - 1, if needed 5 nFAW Repeat sub-loop 0, use BA[2:0] = 4 6 nFAW + nRRD Repeat sub-loop 1, use BA[2:0] = 5 7 nFAW + 2 x nRRD Repeat sub-loop 0, use BA[2:0] = 6 8 nFAW + 3 x nRRD 9 nFAW + 4 x nRRD Repeat sub-loop 1, use BA[2:0] = 7 D 1 nFAW + 4 x nRRD + 1 10 0 0 0 7 0 0 0 F - 0 Repeat cycle nFAW + 4 x nRRD until 2 x nFAW - 1, if needed 2 x nFAW ACT 0 0 1 1 0 0 0 0 0 F 0 - 2 x nFAW + 1 RDA 0 1 0 1 0 0 0 1 0 F 0 00110011 2 x nFAW + 2 D 1 0 0 0 0 0 0 0 0 F 0 - 2 x nFAW + 3 11 0 Repeat cycle 2 x nFAW + 2 until 2 x nFAW + nRRD - 1 2 x nFAW + nRRD ACT 0 0 1 1 0 1 0 0 0 0 0 - 2 x nFAW + nRRD + 1 RDA 0 1 0 1 0 1 0 1 0 0 0 00000000 2 x nFAW + nRRD + 2 D 1 0 0 0 0 1 0 0 0 0 0 - 2 x nFAW + nRRD + 3 Repeat cycle 2 x nFAW + nRRD + 2 until 2 x nFAW + 2 x nRRD - 1 12 2 x nFAW + 2 x nRRD Repeat sub-loop 10, use BA[2:0] = 2 13 2 x nFAW + 3 x nRRD 14 2 x nFAW + 4 x nRRD Repeat sub-loop 11, use BA[2:0] = 3 D 1 0 0 0 0 3 0 0 0 0 0 2 x nFAW + 4 x nRRD + 1 Repeat cycle 2 x nFAW + 4 x nRRD until 3 x nFAW - 1, if needed 3 x nFAW Repeat sub-loop 10, use BA[2:0] = 4 15 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 41 - Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - IDD Specifications and Conditions Definitions Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. 2. 3. 4. D 1 0 0 0 0 7 0 0 0 0 Data3 3 x nFAW + 4 x nRRD 3 x nFAW + 4 x nRRD + 1 A[2:0] 19 A[6:3] Repeat sub-loop 11, use BA[2:0] = 7 A[9:7] 3 x nFAW + 3 x nRRD A[10] 18 A[15:11] Repeat sub-loop 10, use BA[2:0] = 6 BA[2:0] 3 x nFAW + 2 x nRRD ODT 17 WE# Repeat sub-loop 11, use BA[2:0] = 5 CAS# 3 x nFAW + nRRD RAS# 16 CS# Cycle Number Command Sub-loop CKE Static HIGH Toggling CK, CK# Table 19: IDD7 Measurement Loop (Continued) 0 - Repeat cycle 3 x nFAW + 4 x nRRD until 4 x nFAW - 1, if needed DQ, DQS, DQS# are midlevel unless driven as required by the RD command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. AL = CL-1. 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications Electrical Characteristics - IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. Table 20: IDD Maximum Limits - Die Rev A Speed Bin IDD Width DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Notes IDD0 x4 75 90 100 n/a mA 1, 2 x8 100 120 130 n/a mA 1, 2 x16 n/a n/a n/a n/a mA 1, 2 x4 100 115 130 n/a mA 1, 2 x8 115 135 155 n/a mA 1, 2 x16 n/a n/a n/a n/a mA 1, 2 IDD2P0(SLOW) All 12 12 12 n/a mA 1, 2 IDD2P1(FAST) All 30 35 40 n/a mA 1, 2 IDD2Q All 55 65 75 n/a mA 1, 2 IDD2N All 60 70 80 n/a mA 1, 2 IDD2NT x4, x8 75 90 100 n/a mA 1, 2 x16 85 105 115 n/a mA 1, 2 IDD3P All 50 55 65 n/a mA 1, 2 IDD3N x4, x8 70 80 95 n/a mA 1, 2 IDD1 x16 n/a n/a n/a n/a mA 1, 2 x4 175 200 230 n/a mA 1, 2 x8 195 225 255 n/a mA 1, 2 x16 n/a n/a n/a n/a mA 1, 2 x4 225 255 285 n/a mA 1, 2 x8 260 295 330 n/a mA 1, 2 x16 n/a n/a n/a n/a mA 1, 2 IDD5B All 275 290 305 n/a mA 1, 2 IDD6 All 10 10 10 n/a mA 1, 2, 3 IDD6ET All 14 14 14 n/a mA 2, 4 IDD7 x4 320 345 415 n/a mA 1, 2 x8 400 430 460 n/a mA 1, 2 IDD4R IDD4W IDD8 x16 n/a n/a n/a n/a mA 1, 2 All IDD2P0 + 2mA IDD2P0 + 2mA IDD2P0 + 2mA n/a mA 1, 2 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. 2. 3. 4. 5. TC = +85C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = +85C. TC = +85C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0C TC +85C: 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications 5a. When TC < 0C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%. 5b. When TC > +85C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2Px must be derated by 30%; and IDD6 must be derated by 80%. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications Table 21: IDD Maximum Limits - Die Rev D Speed Bin IDD Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Notes IDD0 x4 75 85 95 105 mA 1, 2 x8 75 85 95 105 mA 1, 2 x16 90 100 110 120 mA 1, 2 x4 95 100 105 110 mA 1, 2 IDD1 x8 95 100 105 110 mA 1, 2 x16 125 130 135 140 mA 1, 2 IDD2P0(SLOW) All 12 12 12 12 mA 1, 2 IDD2P1(FAST) x4, x8 25 30 35 40 mA 1, 2 x16 30 35 40 45 IDD2Q All 30 35 40 45 mA 1, 2 IDD2N All 32 37 42 47 mA 1, 2 IDD2NT x4, x8 40 45 50 55 mA 1, 2 x16 45 50 55 60 mA 1, 2 IDD3P x4, x8 30 35 40 45 mA 1, 2 x16 35 40 45 50 mA 1, 2 IDD3N All 35 40 45 50 mA 1, 2 IDD4R x4 125 145 165 185 mA 1, 2 x8 140 160 180 200 mA 1, 2 x16 200 245 270 295 mA 1, 2 x4 135 155 170 190 mA 1, 2 IDD4W 1, 2 x8 145 165 185 205 mA 1, 2 x16 210 255 280 315 mA 1, 2 IDD5B All 190 200 215 220 mA 1, 2 IDD6 All 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 mA 2, 4 IDD7 x4 335 385 435 485 mA 1, 2 x8 335 385 435 485 mA 1, 2 x16 375 425 475 525 mA 1, 2 All IDD2P + mA IDD2P + mA IDD2P + mA IDD2P + mA mA 1, 2 IDD8 Notes: 1. 2. 3. 4. 5. TC = +85C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = +85C. TC = +85C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0C TC +85C: 5a. When TC < 0C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications 5b. When TC > +85C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2Px must be derated by 30%; and IDD6 must be derated by 80%. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics - IDD Specifications Table 22: IDD Maximum Limits - Die Rev H Speed Bin IDD Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Notes IDD0 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 IDD2P0(SLOW) All tbd tbd tbd tbd mA 1, 2 IDD2P1(FAST) All tbd tbd tbd tbd mA 1, 2 IDD2Q All tbd tbd tbd tbd mA 1, 2 IDD2N All tbd tbd tbd tbd mA 1, 2 IDD2NT All tbd tbd tbd tbd mA 1, 2 IDD3P All tbd tbd tbd tbd mA 1, 2 IDD3N All tbd tbd tbd tbd mA 1, 2 IDD4R x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 IDD5B All tbd tbd tbd tbd mA 1, 2 IDD6 All tbd tbd tbd tbd mA 1, 2, 3 IDD6ET All tbd tbd tbd tbd mA 2, 4 IDD7 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 All tbd tbd tbd tbd mA 1, 2 IDD1 IDD4W IDD8 Notes: 1. 2. 3. 4. 5. TC = +85C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = +85C. TC = +85C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0C TC +85C: 5a. When TC < 0C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7%. 5b. When TC > +85C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2Px must be derated by 30%; and IDD6 must be derated by 80%. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Electrical Specifications - DC and AC DC Operating Conditions Table 23: DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage VDD 1.425 1.5 1.575 V 1, 2 I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2 II -2 - 2 A IVREF -1 - 1 A Input leakage current Any input 0V VIN VDD, VREF pin 0V VIN 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Notes: 4 1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ. 2. VDD and VDDQ may include AC noise of 50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. VREF (see Table 24). 4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. Input Operating Conditions Table 24: DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Symbol Min Nom Max Units VIL VSS n/a See Table 25 V Notes VIH See Table 25 n/a VDD V Input reference voltage command/address bus VREFCA(DC) 0.49 x VDD 0.5 x VDD 0.51 x VDD V 1, 2 I/O reference voltage DQ bus VREFDQ(DC) 0.49 x VDD 0.5 x VDD 0.51 x VDD V 2, 3 I/O reference voltage DQ bus in SELF REFRESH VREFDQ(sr) VSS 0.5 x VDD VDD V 4 VTT - 0.5 x VDDQ - V 5 Command/address termination voltage (system level, not direct DRAM input) Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. VREFCA(DC) is expected to be approximately 0.5 x VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed 1% x VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed 2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 x VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed 1% x VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed 2% of VREFDQ(DC). 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC 4. VREFDQ(DC) may transition to VREFDQ(sr) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent. Table 25: Input Switching Conditions Parameter/Condition Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Command and Address Input high AC voltage: Logic 1 @ 175mV VIH(AC175)min +175 +175 - mV Input high AC voltage: Logic 1 @ 150mV VIH(AC150)min +150 +150 - mV Input high AC voltage: Logic 1 @ 135 mV VIH(AC135)min - - +135 mV Input high AC voltage: Logic 1 @ 125 mV VIH(AC125)min - - +125 mV Input high DC voltage: Logic 1 @ 100 mV VIH(DC100)min +100 +100 +100 mV Input low DC voltage: Logic 0 @ -100mV VIL(DC100)max -100 -100 -100 mV Input low AC voltage: Logic 0 @ -125mV VIL(AC125)max - - -125 mV Input low AC voltage: Logic 0 @ -135mV VIL(AC130)max - - -135 mV Input low AC voltage: Logic 0 @ -150mV VIL(AC150)max -150 -150 - mV Input low AC voltage: Logic 0 @ -175mV VIL(AC175)max -175 -175 - mV Input high AC voltage: Logic 1 VIH(AC175)min +175 - - mV Input high AC voltage: Logic 1 VIH(AC150)min +150 +150 - mV Input high AC voltage: Logic 1 VIH(AC135)min - - +135 mV Input high DC voltage: Logic 1 VIH(DC100)min +100 +100 +100 mV Input low DC voltage: Logic 0 VIL(DC100)max -100 -100 -100 mV Input low AC voltage: Logic 0 VIL(AC135)max - - -135 mV Input low AC voltage: Logic 0 VIL(AC150)max -150 -150 - mV Input low AC voltage: Logic 0 VIL(AC175)max -175 - - mV DQ and DM Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 14: Input Signal VIL and VIH levels with ringback 1.90V Minimum VIL and VIH levels 0.925V 0.850V VIH(AC) VIH(DC) 0.575V VDDQ 0.925V VIH(AC) 0.850V VIH(DC) 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 1.50V VIL(DC) VIL(AC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.650V VIL(DC) 0.575V VIL(AC) 0.0V VSS VSS - 0.4V narrow pulse width -0.40V Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN VDDQ + 0.4V narrow pulse width 1. Numbers in diagrams reflect nominal values. 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC AC Overshoot/Undershoot Specification Table 26: Control and Address Pins Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Maximum peak amplitude allowed for overshoot area (see Figure 15) 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 16) 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD (see Figure 15) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns Maximum undershoot area below VSS (see Figure 16) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Maximum peak amplitude allowed for overshoot area (see Figure 15) 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 16) 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD/VDDQ (see Figure 15) 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns Maximum undershoot area below VSS/VSSQ (see Figure 16) 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns Table 27: Clock, Data, Strobe, and Mask Pins Parameter Figure 15: Overshoot Volts (V) Maximum amplitude Overshoot area VDD/VDDQ Time (ns) Figure 16: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Units Notes Differential input voltage logic high - slew VIH,diff(AC)SLEW +200 n/a mV 4 Differential input voltage logic low - slew VIL,diff(AC)SLEW n/a -200 mV 4 Differential input voltage logic high VIH,diff(AC) 2 x (VIH(AC) - VREF) VDD/VDDQ mV 5 Differential input voltage logic low VIL,diff(AC) VSS/VSSQ 2 x (VREF - VIL(AC)) mV 6 Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# VIX VREF(DC) - 150 VREF(DC) + 150 mV 7, 4 Differential input crossing voltage relative to VDD/2 for CK, CK# VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 7, 8, 4 VSEH VDDQ/2 + 175 VDDQ mV 5 VDD/2 + 175 VDD mV 5 VSSQ VDDQ/2 - 175 mV 6 VSS VDD/2 - 175 mV 6 Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes VSEL Single-ended low level for CK, CK# Notes: 1. 2. 3. 4. 5. 6. 7. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2 V/ns Defines slew rate reference points, relative to input crossing voltages. Maximum limit is relative to single-ended signals; overshoot specifications are applicable. Minimum limit is relative to single-ended signals; undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 x VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 8. The VIX extended range (175mV) is allowed only for the clock; this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. 9. VIX must provide 25mV (single-ended) of the voltages separation. Figure 17: VIX for Differential Signals VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# X VIX VIX VDD/2, VDDQ/2 X X VDD/2, VDDQ/2 VIX X CK, DQS CK, DQS VSS, VSSQ PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN VIX VSS, VSSQ 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 18: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH,min VDD/2 or VDDQ/2 VSEH CK or DQS VSEL,max VSEL VSS or VSSQ Figure 19: Definition of Differential AC-Swing and tDVAC tDVAC VIH,diff(AC)min VIH,diff,min VIH,diff(DC)min CK - CK# DQS - DQS# 0.0 VIL,diff(DC)max VIL,diff,max VIL,diff(AC)max tDVAC half cycle Table 29: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS DQS# tDVAC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN (ps) at |VIH,diff(AC) to VIL,diff(AC)| Slew Rate (V/ns) 350mV 300mV >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Table 29: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS DQS# (Continued) tDVAC Note: (ps) at |VIH,diff(AC) to VIL,diff(AC)| Slew Rate (V/ns) 350mV 300mV 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 1. Below VIL(AC) Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF and the first crossing of VIL(AC)max. Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF (see Figure 20 (page 55)). Table 30: Single-Ended Input Slew Rate Definition Input Slew Rates (Linear Signals) Measured Input Edge From To Calculation Setup Rising VREF VIH(AC)min VIH(AC)min - VREF TRS Falling VREF VIL(AC)max VREF - VIL(AC)max TFS Hold Rising VIL(DC)max VREF VREF - VIL(DC)max TFH Falling VIH(DC)min VREF VIH(DC)min - VREF TRSH PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Figure 20: Nominal Slew Rate Definition for Single-Ended Input Signals TRS Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREFDQ or VREFCA VIL(DC)max VIL(AC)max TFS TRH Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC)min VIH(DC)min VREFDQ or VREFCA VIL(DC)max VIL(AC)max TFH PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications - DC and AC Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 31 and Figure 21. The nominal slew rate for a rising signal is defined as the slew rate between VIL,diff,max and VIH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between VIH,diff,min and VIL,diff,max. Table 31: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Measured Input Edge From To Calculation CK and DQS reference Rising VIL,diff,max VIH,diff,min VIH,diff,min - VIL,diff,max TR,diff Falling VIH,diff,min VIL,diff,max VIH,diff,min - VIL,diff,max TF,diff Figure 21: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# Differential input voltage (DQS, DQS#; CK, CK#) TRdiff VIH,diff,min 0 VIL,diff,max TFdiff PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics ODT Characteristics ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values and a functional representation are listed in Table 32 and Table 33 (page 58). The individual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows: * RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off * RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off Figure 22: ODT Levels and I-V Characteristics Chip in termination mode ODT VDDQ IPU To other circuitry such as RCV, . . . IOUT = IPD - IPU RTT(PU) DQ IOUT RTT(PD) VOUT IPD VSSQ Table 32: On-Die Termination DC Electrical Characteristics Parameter/Condition Symbol RTT effective impedance RTT(EFF) Deviation of VM with respect to VDDQ/2 Notes: Min Nom Max Units See Table 33 (page 58) VM -5 +5 Notes 1, 2 % 1, 2, 3 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity (page 59) if either the temperature or voltage changes after calibration. 2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: VIH(AC) - VIL(AC) RTT = ------------------------------------------|I(VIH(AC)) - I(VIL(AC))| 3. Measure voltage (VM) at the tested pin with no load: ( ) 2 x VM VM = ----------------- 1 x 100 Vddq 4. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between -40C and 0C (TC). ODT Resistors Table 33 (page 58) provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what RTT is targeted to provide: * RTT 120 is made up of RTT120(PD240) and RTT120(PU240) * RTT 60 is made up of RTT60(PD120) and RTT60(PU120) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics * RTT 40 is made up of RTT40(PD80) and RTT40(PU80) * RTT 30 is made up of RTT30(PD60) and RTT30(PU60) * RTT 20 is made up of RTT20(PD40) and RTT20(PU40) Table 33: RTT Effective Impedances MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 0, 1, 0 120 RTT120(PD240) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/1 0.5 x VDDQ 0.9 1.0 1.1 RZQ/1 0.8 x VDDQ 0.9 1.0 1.4 RZQ/1 0.2 x VDDQ 0.9 1.0 1.4 RZQ/1 0.5 x VDDQ 0.9 1.0 1.1 RZQ/1 0.8 x VDDQ 0.6 1.0 1.1 RZQ/1 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0.2 x VDDQ 0.6 1.0 1.1 RZQ/2 0.5 x VDDQ 0.9 1.0 1.1 RZQ/2 0.8 x VDDQ 0.9 1.0 1.4 RZQ/2 0.2 x VDDQ 0.9 1.0 1.4 RZQ/2 0.5 x VDDQ 0.9 1.0 1.1 RZQ/2 RTT120(PU240) 120 0, 0, 1 60 RTT60(PD120) RTT60(PU120) 60 0, 1, 1 40 RTT40(PD80) RTT40(PU80) 40 1, 0, 1 30 RTT30(PD60) RTT30(PU60) 30 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 0.8 x VDDQ 0.6 1.0 1.1 RZQ/2 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0.2 x VDDQ 0.6 1.0 1.1 RZQ/3 0.5 x VDDQ 0.9 1.0 1.1 RZQ/3 0.8 x VDDQ 0.9 1.0 1.4 RZQ/3 0.2 x VDDQ 0.9 1.0 1.4 RZQ/3 0.5 x VDDQ 0.9 1.0 1.1 RZQ/3 0.8 x VDDQ 0.6 1.0 1.1 RZQ/3 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 0.2 x VDDQ 0.6 1.0 1.1 RZQ/4 0.5 x VDDQ 0.9 1.0 1.1 RZQ/4 0.8 x VDDQ 0.9 1.0 1.4 RZQ/4 0.2 x VDDQ 0.9 1.0 1.4 RZQ/4 0.5 x VDDQ 0.9 1.0 1.1 RZQ/4 0.8 x VDDQ 0.6 1.0 1.1 RZQ/4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Table 33: RTT Effective Impedances (Continued) MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 1, 0, 0 20 RTT20(PD40) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/6 0.5 x VDDQ 0.9 1.0 1.1 RZQ/6 0.8 x VDDQ 0.9 1.0 1.4 RZQ/6 0.2 x VDDQ 0.9 1.0 1.4 RZQ/6 0.5 x VDDQ 0.9 1.0 1.1 RZQ/6 0.8 x VDDQ 0.6 1.0 1.1 RZQ/6 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 RTT20(PU40) 20 1. Values assume an RZQ of 240 (1%). Note: ODT Sensitivity If either the temperature or voltage changes after I/O calibration, then the tolerance limits listed in Table 32 (page 57) and Table 33 can be expected to widen according to Table 34 and Table 35 (page 59). Table 34: ODT Sensitivity Definition Symbol Min Max Units RTT 0.9 - dRTTdT x |DT| - dRTTdV x |DV| 1.6 + dRTTdT x |DT| + dRTTdV x |DV| RZQ/(2, 4, 6, 8, 12) Note: 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. Table 35: ODT Temperature and Voltage Sensitivity Note: Change Min Max Units dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. ODT Timing Definitions ODT loading differs from that used in AC timing measurements. The reference load for ODT timings is shown in Figure 23. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off asynchronously, and another defines when ODT turns on or off dynamically. Table 36 outlines and provides definition and measurement references settings for each parameter (see Table 37 (page 60)). ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance begins to turn off. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Figure 23: ODT Timing Reference Load DUT CK, CK# VREF VDDQ/2 RTT = 25 DQ, DM DQS, DQS# TDQS, TDQS# ZQ VTT = VSSQ Timing reference point RZQ = 240 VSSQ Table 36: ODT Timing Definitions Symbol Begin Point Definition End Point Definition Figure tAON Rising edge of CK - CK# defined by the end point of ODTL on Extrapolated point at VSSQ Figure 24 (page 61) tAOF Rising edge of CK - CK# defined by the end point of ODTL off Extrapolated point at VRTT,nom Figure 24 (page 61) tAONPD Rising edge of CK - CK# with ODT first being registered HIGH Extrapolated point at VSSQ Figure 25 (page 61) tAOFPD Rising edge of CK - CK# with ODT first being registered LOW Extrapolated point at VRTT,nom Figure 25 (page 61) tADC Rising edge of CK - CK# defined by the end point of ODTLcnw, ODTLcwn4, or ODTLcwn8 Extrapolated points at VRTT(WR) and VRTT,nom Figure 26 (page 62) Table 37: Reference Settings for ODT Timing Measurements Measured Parameter RTT,nom Setting RTT(WR) Setting VSW1 VSW2 tAON RZQ/4 (60) n/a 50mV 100mV RZQ/12 (20) n/a 100mV 200mV RZQ/4 (60) n/a 50mV 100mV RZQ/12 (20) n/a 100mV 200mV RZQ/4 (60) n/a 50mV 100mV RZQ/12 (20) n/a 100mV 200mV RZQ/4 (60) n/a 50mV 100mV RZQ/12 (20) n/a 100mV 200mV RZQ/12 (20) RZQ/2 (120) 200mV 300mV tAOF tAONPD tAOFPD tADC Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. Assume an RZQ of 240 (1%) and that proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Figure 24: tAON and tAOF Definitions tAON tAOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VDDQ/2 CK# CK# tAON tAOF End point: Extrapolated point at VRTT,nom TSW2 TSW1 TSW1 DQ, DM DQS, DQS# TDQS, TDQS# VSW2 TSW1 VSW2 VSW1 VSW1 VSSQ VRTT,nom VSSQ End point: Extrapolated point at VSSQ Figure 25: tAONPD and tAOFPD Definitions tAONPD tAOFPD Begin point: Rising edge of CK - CK# with ODT first registered high Begin point: Rising edge of CK - CK# with ODT first registered low CK CK VDDQ/2 CK# CK# tAONPD tAOFPD End point: Extrapolated point at VRTT,nom TSW2 TSW2 TSW1 DQ, DM DQS, DQS# TDQS, TDQS# VSW2 VSSQ VRTT,nom TSW1 VSW2 VSW1 VSW1 VSSQ End point: Extrapolated point at VSSQ PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics Figure 26: tADC Definition Begin point: Rising edge of CK - CK# defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK# defined by the end point of ODTLcwn 4 or ODTLcwn 8 CK VDDQ/2 CK# tADC VRTT,nom DQ, DM DQS, DQS# TDQS, TDQS# End point: Extrapolated point at VRTT,nom tADC VRTT,nom TSW21 TSW11 VSW2 VSW1 TSW22 TSW12 VRTT(WR) End point: Extrapolated point at VRTT(WR) VSSQ PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Output Driver Impedance The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver impedance Ron is defined by the value of the external reference resistor RZQ as follows: * RON,x = RZQ/y (with RZQ = 240 1%; x = 34 or 40 with y = 7 or 6, respectively) The individual pull-up and pull-down resistors (RON(PU) and RON(PD)) are defined as follows: * RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off * RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off Figure 27: Output Driver Chip in drive mode Output driver VDDQ IPU To other circuitry such as RCV, . . . RON(PU) DQ IOUT RON(PD) VOUT IPD VSSQ PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance 34 Ohm Output Driver Impedance The 34 driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34 driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with nominal RZQ = 240 1%) and is actually 34.3 1%. Table 38: 34 Ohm Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units 0,1 34.3 RON34(PD) 0.2/VDDQ 0.6 1.0 1.1 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.9 1.0 1.4 RZQ/7 0.2/VDDQ 0.9 1.0 1.4 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.6 1.0 1.1 RZQ/7 0.5/VDDQ -10% n/a 10 % RON34(PU) Pull-up/pull-down mismatch (MMPUPD) Notes: Notes 2 1. Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to 34 Ohm Output Driver Sensitivity (page 66) if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 x VDDQ: RonPU - RonPD MMPUPD = x 100 RonNOM 3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between -40C and 0C (TC). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance 34 Ohm Driver The 34 driver's current range has been calculated and summarized in Table 40 (page 65) VDD = 1.5V, Table 41 (page 65) for VDD = 1.57V, and Table 42 (page 66) for VDD = 1.42V. The individual pull-up and pull-down resistors (RON34(PD) and RON34(PU)) are defined as follows: * RON34(PD) = (VOUT)/|IOUT|; RON34(PU) is turned off * RON34(PU) = (VDDQ - VOUT)/|IOUT|; RON34(PD) is turned off Table 39: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Units RZQ = 240 1% 237.6 240 242.4 RZQ/7 = (240 1%)/7 33.9 34.3 34.6 MR1[5,1] RON Resistor VOUT Min Nom Max Units 0, 1 34.3 RON34(PD) 0.2 x VDDQ 20.4 34.3 38.1 0.5 x VDDQ 30.5 34.3 38.1 0.8 x VDDQ 30.5 34.3 48.5 0.2 x VDDQ 30.5 34.3 48.5 0.5 x VDDQ 30.5 34.3 38.1 0.8 x VDDQ 20.4 34.3 38.1 RON34(PU) Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34(PD) IOL @ 0.2 x VDDQ 14.7 8.8 7.9 mA IOL @ 0.5 x VDDQ 24.6 21.9 19.7 mA IOL @ 0.8 x VDDQ 39.3 35.0 24.8 mA IOH @ 0.2 x VDDQ 39.3 35.0 24.8 mA IOH @ 0.5 x VDDQ 24.6 21.9 19.7 mA IOH @ 0.8 x VDDQ 14.7 8.8 7.9 mA RON34(PU) Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34(PD) IOL @ 0.2 x VDDQ 15.5 9.2 8.3 mA IOL @ 0.5 x VDDQ 25.8 23 20.7 mA RON34(PU) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN IOL @ 0.8 x VDDQ 41.2 36.8 26 mA IOH @ 0.2 x VDDQ 41.2 36.8 26 mA IOH @ 0.5 x VDDQ 25.8 23 20.7 mA IOH @ 0.8 x VDDQ 15.5 9.2 8.3 mA 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Table 42: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V MR1[5,1] RON Resistor VOUT Max Nom Min Units 0, 1 34.3 RON34(PD) IOL @ 0.2 x VDDQ 14.0 8.3 7.5 mA IOL @ 0.5 x VDDQ 23.3 20.8 18.7 mA IOL @ 0.8 x VDDQ 37.3 33.3 23.5 mA IOH @ 0.2 x VDDQ 37.3 33.3 23.5 mA IOH @ 0.5 x VDDQ 23.3 20.8 18.7 mA IOH @ 0.8 x VDDQ 14.0 8.3 7.5 mA RON34(PU) 34 Ohm Output Driver Sensitivity If either the temperature or the voltage changes after ZQ calibration, then the tolerance limits listed in Table 38 (page 64) can be expected to widen according to Table 43 and Table 44 (page 66). Table 43: 34 Ohm Output Driver Sensitivity Definition Symbol Min Max Units RON(PD) @ 0.2 x VDDQ 0.6 - dRONdTL x |T| - dRONdVL x |V| 1.1 + dRONdTL x |T| + dRONdVL x |V| RZQ/6 RON(PD) @ 0.5 x VDDQ 0.9 - dRONdTM x |T| - dRONdVM x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| RZQ/6 RON(PD) @ 0.8 x VDDQ 0.9 - dRONdTH x |T| - dRONdVH x |V| 1.4 + dRONdTH x |T| + dRONdVH x |V| RZQ/6 RON(PU) @ 0.2 x VDDQ 0.9 - dRONdTL x |T| - dRONdVL x |V| 1.4 + dRONdTL x |T| + dRONdVL x |V| RZQ/7 RON(PU) @ 0.5 x VDDQ 0.9 - dRONdTM x |T| - dRONdVM x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| RZQ/7 RON(PU) @ 0.8 x VDDQ 0.6 - dRONdTH x |T| - dRONdVH x |V| 1.1 + dRONdTH x |T| + dRONdVH x |V| RZQ/7 Note: 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. Table 44: 34 Ohm Output Driver Voltage and Temperature Sensitivity PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Change Min Max Units dRONdTM 0 1.5 %/C dRONdVM 0 0.13 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 0.13 %/mV dRONdTH 0 1.5 %/C dRONdVH 0 0.13 %/mV 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Alternative 40 Ohm Driver Table 45: 40 Ohm Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Units 0,0 40 RON40(PD) 0.2 x VDDQ 0.6 1.0 1.1 RZQ/6 0.5 x VDDQ 0.9 1.0 1.1 RZQ/6 0.8 x VDDQ 0.9 1.0 1.4 RZQ/6 RON40(PU) Pull-up/pull-down mismatch (MMPUPD) Notes: 0.2 x VDDQ 0.9 1.0 1.4 RZQ/6 0.5 x VDDQ 0.9 1.0 1.1 RZQ/6 0.8 x VDDQ 0.6 1.0 1.1 RZQ/6 0.5 x VDDQ -10% n/a 10 % 1. Tolerance limits assume RZQ of 240 (1%) and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to 40 Ohm Output Driver Sensitivity (page 67) if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 x VDDQ: RonPU - RonPD MMPUPD = x 100 RonNOM 3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between -40C and 0C (TC). 40 Ohm Output Driver Sensitivity If either the temperature or the voltage changes after I/O calibration, then the tolerance limits listed in Table 45 can be expected to widen according to Table 46 and Table 47 (page 68). Table 46: 40 Ohm Output Driver Sensitivity Definition Symbol Min Max Units RON(PD) @ 0.2 x VDDQ 0.6 - dRONdTL x |T| - dRONdVL x |V| 1.1 + dRONdTL x |T| + dRONdVL x |V| RZQ/6 RON(PD) @ 0.5 x VDDQ 0.9 - dRONdTM x |T| - dRONdVM x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| RZQ/6 RON(PD) @ 0.8 x VDDQ 0.9 - dRONdTH x |T| - dRONdVH x |V| 1.4 + dRONdTH x |T| + dRONdVH x |V| RZQ/6 RON(PU) @ 0.2 x VDDQ 0.9 - dRONdTL x |T| - dRONdVL x |V| 1.4 + dRONdTL x |T| + dRONdVL x |V| RZQ/7 RON(PU) @ 0.5 x VDDQ 0.9 - dRONdTM x |T| - dRONdVM x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| RZQ/7 RON(PU) @ 0.8 x VDDQ 0.6 - dRONdTH x |T| - dRONdVH x |V| 1.1 + dRONdTH x |T| + dRONdVH x |V| RZQ/7 Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. T = T - T(@ calibration), V = VDDQ - VDDQ(@ calibration), and VDD = VDDQ. 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Change Min Max Unit dRONdTM 0 1.5 %/C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/C dRONdVH 0 0.15 %/mV 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized below, while the differential output driver is summarized in Table 48 while the differential output driver is summarized in Table 49 (page 70). Table 48: Single-Ended Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Symbol Min Max Units Notes IOZ -5 +5 A 1 Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.1 x VDDQ and VOH(AC) = VREF + 0.1 x VDDQ SRQse 2.5 6 V/ns 1, 2, 3, 4 Single-ended DC high-level output voltage VOH(DC) 0.8 x VDDQ V 1, 2, 5 Single-ended DC mid-point level output voltage VOM(DC) 0.5 x VDDQ V 1, 2, 5 Single-ended DC low-level output voltage VOL(DC) 0.2 x VDDQ V 1, 2, 5 Single-ended AC high-level output voltage VOH(AC) VTT + 0.1 x VDDQ V 1, 2, 3, 6 Single-ended AC low-level output voltage VOL(AC) VTT - 0.1 x VDDQ V 1, 2, 3, 6 % 1, 7 Output leakage current: DQ are disabled; 0V VOUT VDDQ; ODT is disabled; ODT is HIGH Delta Ron between pull-up and pull-down for DQ/DQS MMPUPD Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN -10 +10 Output to VTT (VDDQ/2) via 25 resistor Test load for AC timing and output slew rates 3 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). 2. VTT = VDDQ/2. 3. See Figure 30 (page 71) for the test load configuration. 4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or all switching the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns. 5. See Table 38 (page 64) for IV curve linearity. Do not use AC test load. 6. See Table 50 (page 72) for output slew rate. 7. See Table 38 (page 64) for additional information. 8. See Figure 28 (page 70) for an example of a single-ended output signal. 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Table 49: Differential Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Symbol Min Max Units Notes Output leakage current: DQ are disabled; 0V VOUT VDDQ; ODT is disabled; ODT is HIGH IOZ -5 +5 A 1 Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = -0.2 x VDDQ and VOH,diff(AC) = +0.2 x VDDQ SRQdiff 5 12 V/ns 1 Output differential cross-point voltage VOX(AC) VREF - 150 VREF + 150 mV 1, 2, 3 Differential high-level output voltage VOH,diff(AC) +0.2 x VDDQ V 1, 4 Differential low-level output voltage VOL,diff(AC) -0.2 x VDDQ V 1, 4 % 1, 5 Delta Ron between pull-up and pull-down for DQ/DQS MMPUPD Notes: -10 +10 Output to VTT (VDDQ/2) via 25 resistor Test load for AC timing and output slew rates 3 1. RZQ of 240 (1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). 2. VREF = VDDQ/2; slew rate @ 5 V/ns, interpolate for faster slew rate. 3. See Figure 30 (page 71) for the test load configuration. 4. See Table 51 (page 73) for the output slew rate. 5. See Table 38 (page 64) for additional information. 6. See Figure 29 (page 71) for an example of a differential output signal. Figure 28: DQ Output Signal MAX output VOH(AC) VOL(AC) MIN output PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Figure 29: Differential Output Signal MAX output VOH X X VOX(AC)max X VOX(AC)min X VOL MIN output Reference Output Load Figure 30 represents the effective reference load of 25 used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate measurements. It is not intended to be a precise representation of a particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Figure 30: Reference Output Load for AC Timing and Output Slew Rate DUT VREF DQ DQS DQS# ZQ VDDQ/2 RTT = 25 VTT = VDDQ/2 Timing reference point RZQ = 240 VSS PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 48 (page 69). With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals. Table 50: Single-Ended Output Slew Rate Definition Single-Ended Output Slew Rates (Linear Signals) Measured Output Edge From To Calculation DQ Rising VOL(AC) VOH(AC) VOH(AC) - VOL(AC) TRSE Falling VOH(AC) VOL(AC) VOH(AC) - VOL(AC) TFSE Figure 31: Nominal Slew Rate Definition for Single-Ended Output Signals TRSE VOH(AC) VTT VOL(AC) TFSE PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 49 (page 70). With the reference load for timing measurements, the output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for differential signals. Table 51: Differential Output Slew Rate Definition Differential Output Slew Rates (Linear Signals) Measured Output Edge From To Calculation DQS, DQS# Rising VOL,diff(AC) VOH,diff(AC) VOH,diff(AC) - VOL,diff(AC) TRdiff Falling VOH,diff(AC) VOL,diff(AC) VOH,diff(AC) - VOL,diff(AC) TFdiff Figure 32: Nominal Differential Output Slew Rate Definition for DQS, DQS# TRdiff VOH,diff(AC) 0 VOL,diff(AC) TFdiff PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Speed Bin Tables Table 52: DDR3-1066 Speed Bins DDR3-1066 Speed Bin -187E -187 CL-tRCD-tRP 7-7-7 8-8-8 Parameter Symbol Min Max Min Max Units tRCD 13.125 - 15 - ns PRECHARGE command period tRP 13.125 - 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50.625 - 52.5 - ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 x tREFI 37.5 9 x tREFI ns 1 3.0 3.3 3.0 3.3 ns 2 ns 3 ns 2 ACTIVATE to internal READ or WRITE delay time CL = 5 CL = 6 CL = 7 CL = 8 CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved Reserved ns 3 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) Reserved ns 2, 3 CWL = 5 tCK (AVG) Reserved ns 3 CWL = 6 tCK (AVG) ns 2 Reserved 2.5 <2.5 Reserved 1.875 Supported CWL settings Notes: 3.3 1.875 Supported CL settings PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Notes <2.5 Reserved 2.5 3.3 1.875 <2.5 5, 6, 7, 8 5, 6, 8 CK 5, 6 5, 6 CK 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 53: DDR3-1333 Speed Bins DDR3-1333 Speed Bin -15E1 -152 CL-tRCD-tRP 9-9-9 10-10-10 Parameter Symbol Min Max Min Max Units tRCD 13.5 - 15 - ns PRECHARGE command period tRP 13.5 - 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 49.5 - 51 - ns ACTIVATE-to-PRECHARGE command period tRAS 36 9 x tREFI 36 9 x tREFI ns 3 3.0 3.3 3.0 3.3 ns 4 ns 5 ns 4 ACTIVATE to internal READ or WRITE delay time CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CWL = 5 tCK (AVG) CWL = 6, 7 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved Reserved ns 5 CWL = 7 tCK (AVG) Reserved Reserved ns 5 CWL = 5 tCK (AVG) Reserved Reserved ns 5 CWL = 6 tCK (AVG) Reserved ns 4, 5 CWL = 7 tCK (AVG) Reserved Reserved ns 5 CWL = 5 tCK (AVG) Reserved Reserved ns 5 CWL = 6 tCK (AVG) ns 4 CWL = 7 tCK (AVG) 5 CWL = 5, 6 tCK (AVG) CWL = 7 tCK (AVG) CWL = 5, 6 tCK (AVG) CWL = 7 tCK (AVG) Reserved 2.5 <2.5 1.875 <2.5 Reserved 2.5 3.3 1.875 <2.5 Reserved Reserved ns Reserved Reserved ns 5 Reserved ns 4, 5 Reserved ns 5 ns 4 1.5 <1.875 Reserved 1.5 Supported CWL settings Notes: 3.3 1.875 Supported CL settings PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Notes <1.875 1.5 <1.875 5, 6, 7, 8, 9, 10 5, 6, 8, 10 CK 5, 6, 7 5, 6, 7 CK 1. 2. 3. 4. The -15E speed grade is backward compatible with 1066, CL = 7 (-187E). The -15 speed grade is backward compatible with 1066, CL = 8 (-187). tREFI depends on T OPER. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 5. Reserved settings are not allowed. 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 54: DDR3-1600 Speed Bins -1251 DDR3-1600 Speed Bin CL-tRCD-tRP 11-11-11 Parameter Symbol Min Max Units tRCD 13.75 - ns PRECHARGE command period tRP 13.75 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.75 - ns ACTIVATE-to-PRECHARGE command period tRAS 35 9 x tREFI ns 2 3.0 3.3 ns 3 ns 4 ns 3 ACTIVATE to internal READ or WRITE delay time CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CL = 11 CWL = 5 tCK (AVG) CWL = 6, 7, 8 tCK (AVG) CWL = 5 tCK (AVG) CWL = 6 tCK (AVG) Reserved ns 4 CWL = 7, 8 tCK (AVG) Reserved ns 4 CWL = 5 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) Reserved ns 4 CWL = 5 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) Reserved ns 4 CWL = 5, 6 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CWL = 5, 6 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CWL = 5, 6, 7 tCK (AVG) Reserved CWL = 8 tCK (AVG) Supported CL settings Supported CWL settings Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Notes Reserved 2.5 3.3 1.875 1.875 1.5 <2.5 <2.5 <1.875 1.5 <1.875 ns 4 <1.5 ns 3 5, 6, 7, 8, 9, 10, 11 CK 5, 6, 7, 8 CK 1.25 1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E). 2. tREFI depends on TOPER. 3. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 4. Reserved settings are not allowed. 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables Table 55: DDR3-1866 Speed Bins -1071 DDR3-1866 Speed Bin CL-tRCD-tRP 13-13-13 Parameter Symbol Min Max Internal READ command to first data tAA 13.91 20 ACTIVATE to internal READ or WRITE delay time tRCD 13.91 - ns PRECHARGE command period tRP 13.91 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.91 - ns ACTIVATE-to-PRECHARGE command period tRAS 34 9 x tREFI ns 2 3.0 3.0 ns 3 ns 4 CL = 5 CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CL = 11 CL = 12 CL = 13 tCK (AVG) CWL = 6, 7, 8, 9 tCK (AVG) CWL = 5 tCK (AVG) ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) ns 3 CWL = 5, 8, 9 tCK (AVG) ns 4 CWL = 6 tCK (AVG) ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) ns 3 CWL = 5, 6, 9 tCK (AVG) ns 4 CWL = 7 tCK (AVG) ns 3 CWL = 8 tCK (AVG) Reserved ns 3 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) ns 3 CWL = 9 tCK (AVG) Reserved ns 3 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) Reserved ns 3 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) ns 3 Supported CWL settings PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Notes CWL = 5 Supported CL settings Notes: Units Reserved 2.5 3.3 1.875 <2.5 Reserved 1.875 1.5 <2.5 <1.875 Reserved 1.5 <1.875 1.25 1.07 <1.5 <1.25 5, 6, 7, 8, 9, 10, 11, 13 CK 5, 6, 7, 8, 9 CK 1. The -107 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E). 2. tREFI depends on TOPER. 3. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 4. Reserved settings are not allowed. 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Electrical Characteristics and AC Operating Conditions Table 56: Electrical Characteristics and AC Operating Conditions Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol Min DDR3-1066 Max Min DDR3-1333 DDR3-1600 Max Min Max Min Max Units Notes Clock Timing Clock period average: DLL disable mode TC = 0C to 85C tCKdll_dis TC = >85C to 95C 8 7800 8 7800 8 7800 8 7800 ns 9, 42 8 3900 8 3900 8 3900 8 3900 ns 42 ns 10, 11 High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12 Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 CK 12 -100 100 -90 90 -80 80 -70 70 ps 13 -90 90 -80 80 -70 70 -60 60 ps 13 Clock period jitter DLL locked DLL locking (AVG) tJITper tJITper, lck Clock absolute period tCK(ABS) Clock absolute high pulse width tCH (ABS) See Speed Bin Tables (page 74) for MIN = tCK (AVG) MIN + - 0.43 tJITper MIN; MAX = - 0.43 tCK tCK range allowed (AVG) MAX + - 0.43 tJITper MAX - 0.43 ps tCK 14 (AVG) 78 Clock absolute low pulse width Cycle-to-cycle jitter DLL locked Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. DLL locking tCL (ABS) tJITcc tJITcc, - 0.43 200 180 160 140 ps 16 ps 16 -132 132 -118 118 -103 103 ps 17 3 cycles tERR -175 175 -157 157 -140 140 -122 122 ps 17 4 cycles tERR -194 194 -175 175 -155 155 -136 136 ps 17 5 cycles tERR -209 209 -188 188 -168 168 -147 147 ps 17 6 cycles tERR -222 222 -200 200 -177 177 -155 155 ps 17 7 cycles tERR -232 232 -209 209 -186 186 -163 163 ps 17 8 cycles tERR -241 241 -217 217 -193 193 -169 169 ps 17 9 cycles tERR 9per -249 249 -224 224 -200 200 -175 175 ps 17 10 cycles tERR 10per -257 257 -231 231 -205 205 -180 180 ps 17 11 cycles tERR -263 263 -237 237 -210 210 -184 184 ps 17 12 cycles tERR -269 269 -242 242 -215 215 -188 188 ps 17 ps 17 5per 6per 7per 8per 11per 12per tERR Nper tERRnper tERRnper MIN = (1 + 0.68ln[n]) x 120 15 147 4per 140 tCK (AVG) -147 3per 160 - 0.43 tERR 2per 180 - 0.43 Cumulative error across 2 cycles n = 13, 14 . . . 49, 50 cycles lck - 0.43 tJITper MIN MAX = (1 + 0.68ln[n]) x tJITper MAX 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Clock period average: DLL enable mode tCK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol Min Max tDS 75 - AC175 250 tDS 125 AC150 tDS AC135 DDR3-1066 Min DDR3-1333 DDR3-1600 Max Min Max Min Max Units Notes 25 - - - - - ps 18, 19 - 200 - - - - - ps 19, 20 - 75 - 30 - 10 - ps 18, 19 275 - 250 - 180 - 160 - ps 19, 20 - - - - - - - - ps 18, 19 - - - - - - - - ps 19, 20 tDH 150 - 100 - 65 - 45 - ps 18, 19 DC100 250 - 200 - 165 - 145 - ps 19, 20 Minimum data pulse width tDIPW 600 - 490 - 400 - 360 - ps 41 DQS, DQS# to DQ skew, per access tDQSQ 150 - 125 - 100 ps - tCK DQ Input Timing Data setup time to DQS, DQS# Base (specification) Data setup time to DQS, DQS# Base (specification) Data setup time to DQS, DQS# VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns DQ Output Timing 79 DQ output hold time from DQS, DQS# tQH - 0.38 200 - - 0.38 - 0.38 - 0.38 21 (AVG) Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. DQ Low-Z time from CK, CK# tLZ (DQ) -800 400 -600 300 -500 250 -450 225 ps 22, 23 DQ High-Z time from CK, CK# tHZ (DQ) - 400 - 300 - 250 - 225 ps 22, 23 25 DQ Strobe Input Timing DQS, DQS# rising to CK, CK# rising tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 CK DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 - 0.2 - 0.2 - 0.18 - CK 25 DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 - 0.2 - 0.2 - 0.18 - CK 25 DQS, DQS# differential WRITE preamble tWPRE 0.9 - 0.9 - 0.9 - 0.9 - CK DQS, DQS# differential WRITE postamble tWPST 0.3 - 0.3 - 0.3 - 0.3 - CK DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK -400 400 -300 300 -255 255 -225 225 ps 23 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK 1 10 1 10 1 10 1 10 ns 26 DLL_DIS DQS, DQS# differential output high time tQSH 0.38 - 0.38 - 0.40 - 0.40 - CK 21 DQS, DQS# differential output low time tQSL 0.38 - 0.38 - 0.40 - 0.40 - CK 21 -800 400 -600 300 -500 250 -450 225 ps 22, 23 DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Data hold time from DQS, DQS# VREF @ 1 V/ns PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol DQS, DQS# High-Z time (RL + BL/2) tHZ Min (DQS) DQS, DQS# differential READ preamble tRPRE DQS, DQS# differential READ postamble tRPST DDR3-1066 Max Min Max DDR3-1333 Min DDR3-1600 Max Min Max Units Notes - 400 - 300 - 250 - 225 ps 22, 23 0.9 Note 24 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23, 24 0.3 Note 27 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23, 27 512 - 512 - CK 28 Command and Address Timing 512 - 512 - tIS 200 - 125 - 65 - 45 - ps 29, 30 AC175 375 - 300 - 240 - 220 - ps 20, 30 tIS 350 - 275 - 190 - 170 - ps 29, 30 AC150 500 - 425 - 340 - 320 - ps 20, 30 tIH 275 - 200 - 140 - 120 - ps 29, 30 DC100 375 - 300 - 240 - 220 - ps 20, 30 Minimum CTRL, CMD, ADDR pulse width tIPW 900 - 780 - 620 - 560 - ps 41 ACTIVATE to internal READ or WRITE delay tRCD tRCD ns 31 tRP CTRL, CMD, ADDR setup to CK,CK# CTRL, CMD, ADDR setup to CK,CK# Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns CTRL, CMD, ADDR hold Base (specification) from CK,CK# VREF @ 1 V/ns 80 PRECHARGE command period See Speed Bin Tables (page 74) for tRP ns 31 tRAS See Speed Bin Tables (page 74) for tRAS ns 31, 32 tRC See Speed Bin Tables (page 74) for tRC ns 31 ACTIVATE-to-ACTIVATE 1KB page size minimum command period 2KB page size tRRD MIN = greater of MIN = greater of MIN = greater of MIN = greater of 4CK or 10ns 4CK or 7.5ns 4CK or 6ns 4CK or 6ns CK 31 CK 31 Four ACTIVATE windows tFAW ACTIVATE-to-PRECHARGE command period Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. ACTIVATE-to-ACTIVATE command period 1KB page size See Speed Bin Tables (page 74) for MIN = greater of 4CK or 10ns 2KB page size MIN = greater of 4CK or 7.5ns 40 - 37.5 - 30 - 30 - ns 31 50 - 50 - 45 - 40 - ns 31 tWR MIN = 15ns; MAX = n/a ns 31, 32, 33 tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK Write recovery time Delay from start of internal WRITE transaction to internal READ command MIN = WR + tRP/tCK (AVG); MAX = n/a CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions tDLLK DLL locking time PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol Min Max DDR3-1066 Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR ZQCL command: Long calibration time tZQinit 512 - 512 - 512 - 512 - CK tZQoper 256 - 256 - 256 - 256 - CK ZQCS command: Short calibration time tZQcs 64 - 64 - 64 - 64 - CK Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK tVddpr MIN = n/a; MAX = 200 ms MIN = 1CK; MAX = n/a CK Calibration Timing POWER-UP and RESET operation Normal operation Begin power supply ramp to power supplies stable 81 RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOz MIN = n/a; MAX = 20 ns 35 Refresh Timing Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. tRFC - 1Gb MIN = 110; MAX = 70,200 ns tRFC - 2Gb MIN = 160; MAX = 70,200 ns - 4Gb MIN = 300; MAX = 70,200 ns 64 (1X) ms 36 32 (2X) ms 36 7.8 (64ms/8192) s 36 3.9 (32ms/8192) s 36 tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK Minimum CKE low pulse width for self refresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or powerdown entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK REFRESH-to-ACTIVATE or REFRESH command period tRFC Maximum refresh period Maximum average periodic refresh TC +85C - TC > +85C TC +85C tREFI TC > +85C Self Refresh Timing Exit self refresh to commands not requiring a locked DLL 28 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Initialization and Reset Timing PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol Valid clocks before self refresh exit, power-down exit, or reset exit tCKSRX Min DDR3-1066 Max Min DDR3-1333 Max Min DDR3-1600 Max Min Max MIN = greater of 5CK or 10ns; MAX = n/a Units Notes CK Power-Down Timing tCKE CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing (MIN) tCPDED tPD Greater of 3CK or 7.5ns Greater of 3CK or 5.625ns Greater of 3CK or 5.625ns Greater of 3CK or 5ns MIN = 1; MAX = n/a MIN = tCKE (MIN); MAX = 60ms CK CK CK WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX Begin power-down period prior to CKE registered HIGH tANPD + tXPDLL CK 82 Power-Down Entry Minimum Timing Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 1 CK REFRESH command to power-down entry tREFPDEN MIN = 1 CK MRS command to power-down entry tMRSPDEN tMOD CK MIN = (MIN) READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK WRITE command to power-down entry BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK tWRAPDEN MIN = WL + 4 + WR + 1 CK tWRAPDEN MIN = WL + 2 + WR + 1 CK WRITE with auto BL8 (OTF, MRS) precharge command to BC4OTF power-down entry BC4MRS 37 Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL Precharge power-down with DLL off to commands requiring a locked DLL tXP tXPDLL MIN = greater of 3CK or 7.5ns; MAX = n/a MIN = greater of 3CK or 6ns; MAX = n/a MIN = greater of 10CK or 24ns; MAX = n/a CK CK 28 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions tANPD PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1-8 apply to the entire table DDR3-800 Parameter Symbol RTT synchronous turn-on delay ODTL on RTT synchronous turn-off delay ODTL off Min Max DDR3-1066 Min Max DDR3-1333 Min Max DDR3-1600 Min Max Units Notes ODT Timing CWL + AL - 2CK CK CWL + AL - 2CK 38 CK 40 RTT turn-on from ODTL on reference tAON -400 400 -300 300 -250 250 -225 225 ps 23, 38 RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 39, 40 MIN = 2; MAX = 8.5 ns 38 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 2; MAX = 8.5 ns 40 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing 83 RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK RTT(WR)-to-RTT,nom change skew - BC4 ODTLcnw4 4CK + ODTL off CK RTT(WR)-to-RTT,nom change skew - BL8 ODTLcnw8 6CK + ODTL off CK Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 CK 40 - 40 - 40 - CK Write Leveling Timing tWLMRD 40 - tWLDQSEN 25 - 25 - 25 - 25 - CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 325 - 245 - 195 - 165 - ps Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 325 - 245 - 195 - 165 - ps Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns First DQS, DQS# rising edge DQS, DQS# delay 39 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD 2Gb: x4, x8, x16 DDR3 SDRAM Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Parameters are applicable with 0C TC +95C and VDD/VDDQ = +1.5V 0.075V. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/ DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/ ns for differential inputs in the range between VIL(AC) and VIH(AC). All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine the correct number of clocks (Table 56 (page 78) uses CK or tCK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VDDQ/ 2 for single-ended signals and the crossing point for differential signals (see Figure 30 (page 71)). When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. The clock's tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60 kHz with an additional 1% of tCK(AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. The clock's tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. The cumulative jitter error (tERRnper), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK (MIN), tLZ (DQS) MIN, tLZ (DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ (DQS) MAX, tLZ(DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCKdll_dis parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. t 29. IS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows: * For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL * For BC4 (OTF): Rising clock edge four clock cycles after WL * For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in HighZ. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 36. The refresh period is 64ms when TC is less than or equal to 85C. This equates to an average refresh rate of 7.8125s. However, nine REFRESH commands should be asserted at least once every 70.3s. When TC is greater than +85C, the refresh period is 32ms. Although JEDEC specifies tREFI as a MAX, Micron allows REFRESH commands to be burst provided that the maximum refresh period is not violated. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 22 (page 57). 39. Half-clock output parameters must be derated by the actual tERR10PER and tJITdty when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR PER (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are 10 required to be derated by subtracting both tERR10PER (MAX) and tJITdty (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turnoff time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 23 (page 60). This output load is used for ODT timings (see Figure 30 (page 71)). 41. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Electrical Characteristics and AC Operating Conditions Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Min Max Units Notes 8 7800 ns 9, 42 8 3900 ns 42 ns 10, 11 Clock Timing Clock period average: DLL disable mode TC = 0C to 85C tCKdll_dis TC = >85C to 95C High pulse width average tCH (AVG) 0.47 0.53 CK 12 Low pulse width average tCL (AVG) 0.47 0.53 CK 12 -60 60 ps 13 -50 50 ps 13 Clock period jitter DLL locked DLL locking (AVG) tJITper tJITper, lck tCK(ABS) Clock absolute period See Speed Bin Tables (page 74) for tCK range allowed MIN = tCK (AVG) MIN + tJITp- ps 87 er MIN; MAX = tCK (AVG) MAX + tJITper MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Clock absolute high pulse width tCH (ABS) 0.43 - tCK (AVG) 14 Clock absolute low pulse width tCL (ABS) 0.43 - tCK (AVG) 15 120 ps 16 100 ps 16 Cycle-to-cycle jitter DLL locked DLL locking tJITcc tJITcc, lck 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Clock period average: DLL enable mode tCK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Cumulative error across tERR 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 10 cycles 11 cycles 12 cycles n = 13, 14 . . . 49, 50 cycles Max Units Notes -88 88 ps 17 -105 105 ps 17 -117 117 ps 17 -126 126 ps 17 -133 133 ps 17 -139 139 ps 17 -145 145 ps 17 -150 150 ps 17 -154 154 ps 17 -158 158 ps 17 -161 161 ps 17 ps 17 tERRnper 88 MIN = (1 + 0.68ln[n]) x tJITper MIN tERRnper MAX = (1 + 0.68ln[n]) x tJITper MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. DQ Input Timing Data setup time to DQS, DQS# Base (specification) VREF @ 1 V/ns Data setup time to DQS, DQS# Base (specification) VREF @ 1 V/ns Data setup time to DQS, DQS# Base (specification) VREF @ 1 V/ns Data hold time from DQS, DQS# Base (specification) VREF @ 1 V/ns Minimum data pulse width tDS - - ps 18, 19 AC175 - - ps 19, 20 tDS - - ps 18, 19 AC150 - - ps 19, 20 tDS 0 - ps 18, 19 AC135 135 - ps 19, 20 tDH 20 - ps 18, 19 DC100 120 - ps 19, 20 tDIPW 320 - ps 41 - 85 DQ Output Timing DQS, DQS# to DQ skew, per access tDQSQ tQH ps tCK 0.38 - DQ Low-Z time from CK, CK# tLZ (DQ) -390 195 ps 22, 23 DQ High-Z time from CK, CK# tHZ (DQ) - 195 ps 22, 23 DQ output hold time from DQS, DQS# (AVG) 21 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions 9 cycles 2per tERR 3per tERR 4per tERR 5per tERR 6per tERR 7per tERR 8per tERR 9per tERR 10per tERR 11per tERR 12per tERR Nper Min PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Min Max Units Notes 25 DQ Strobe Input Timing tDQSS -0.27 0.27 CK DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 CK DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 CK DQS, DQS# falling setup to CK, CK# rising tDSS 0.18 - CK 25 DQS, DQS# falling hold from CK, CK# rising tDSH 0.18 - CK 25 DQS, DQS# differential WRITE preamble tWPRE 0.9 - CK DQS, DQS# differential WRITE postamble tWPST 0.3 - CK DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK -195 195 ps 23 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK 1 10 ns 26 DLL_DIS 89 DQS, DQS# differential output high time tQSH 0.40 - CK 21 DQS, DQS# differential output low time tQSL 0.40 - CK 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) -390 195 ps 22, 23 DQS, DQS# High-Z time (RL + BL/2) tHZ (DQS) - 195 ps 22, 23 DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 CK 23, 24 DQS, DQS# differential READ postamble tRPST 0.3 Note 27 CK 23, 27 tDLLK 512 - CK 28 tIS 65 - ps 29, 30 AC175 200 - ps 20, 30 tIS 150 - ps 29, 30 AC150 275 - ps 20, 30 tIH 100 - ps 29, 30 DC100 200 - ps 20, 30 Minimum CTRL, CMD, ADDR pulse width tIPW 535 - ps 41 ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables (page 74) for tRCD ns 31 tRP See Speed Bin Tables (page 74) for tRP ns 31 Command and Address Timing DLL locking time CTRL, CMD, ADDR setup to CK,CK# CTRL, CMD, ADDR setup to CK,CK# CTRL, CMD, ADDR hold from CK,CK# Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns PRECHARGE command period 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions DQS, DQS# rising to CK, CK# rising PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Notes See Speed Bin Tables (page 74) for tRAS ns 31, 32 tRC See Speed Bin Tables (page 74) for tRC ns 31 ACTIVATE-to-ACTIVATE minimum com- 1KB page size mand 2KB page size period tRRD MIN = greater of 4CK or 5ns CK 31 MIN = greater of 4CK or 6ns CK 31 Four ACTIVATE windows tFAW ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period 1KB page size 2KB page size Min Max 25 - ns 31 35 - ns 31 tWR MIN = 15ns; MAX = n/a ns 31, 32, 33 Delay from start of internal WRITE transaction to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK tZQinit MIN = n/a MAX = max(512nCK, 640ns) CK tZQoper MIN = n/a MAX = max(256nCK, 320ns) CK tZQcs MIN = n/a MAX = max(64nCK, 80ns) CK MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Write recovery time 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Calibration Timing ZQCL command: Long calibration time POWER-UP and RESET operation Normal operation ZQCS command: Short calibration time Initialization and Reset Timing Exit reset from CKE HIGH to a valid command tXPR 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions Units tRAS PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Min Max Units tVddpr MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOz MIN = n/a; MAX = 20 ns Begin power supply ramp to power supplies stable Notes 35 Refresh Timing - 1Gb MIN = 110; MAX = 70,200 ns tRFC - 2Gb MIN = 160; MAX = 70,200 ns tRFC - 4Gb MIN = 300; MAX = 70,200 ns - 64 (1X) ms 36 32 (2X) ms 36 tREFI 7.8 (64ms/8192) s 36 3.9 (32ms/8192) s 36 tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/ a CK Minimum CKE low pulse width for self refresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or power-down entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, power-down exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK Maximum refresh period TC +85C Maximum average periodic refresh TC +85C TC > +85C TC > +85C 91 Self Refresh Timing Exit self refresh to commands not requiring a locked DLL Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Power-Down Timing CKE MIN pulse width Command pass disable delay Power-down entry to power-down exit timing Begin power-down period prior to CKE registered HIGH tCKE Greater of 3CK or 5ns CK tCPDED (MIN) MIN = 2; MAX = n/a CK tPD MIN = tCKE (MIN); MAX = 60ms CK tANPD WL - 1CK CK 28 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions tRFC REFRESH-to-ACTIVATE or REFRESH command period PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Power-down entry period: ODT either synchronous or asynchronous PDE Power-down exit period: ODT either synchronous or asynchronous PDX Min Max tANPD tRFC Greater of or REFRESH command to CKE LOW time tANPD + tXPDLL Units Notes CK CK Power-Down Entry Minimum Timing tACTPDEN MIN = 2 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 2 CK tREFPDEN MIN = 2 CK MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK WRITE command to power-down entry BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + (AVG) tWR/tCK CK tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK BL8 (OTF, MRS) BC4OTF tWRAPDEN MIN = WL + 4 + WR + 1 CK BC4MRS tWRAPDEN MIN = WL + 2 + WR + 1 CK tXP MIN = greater of 3CK or 6ns; MAX = n/a CK tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28 RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38 RTT synchronous turn-off delay ODTL off CWL + AL - 2CK 92 REFRESH command to power-down entry BC4MRS Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. WRITE with auto precharge command to power-down entry 37 Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL Precharge power-down with DLL off to commands requiring a locked DLL ODT Timing RTT turn-on from ODTL on reference tAON RTT turn-off from ODTL off reference tAOF Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD CK 40 -195 195 ps 23, 38 0.3 0.7 CK 39, 40 ns 38 MIN = 2; MAX = 8.5 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions ACTIVATE command to power-down entry PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1-8 apply to the entire table DDR3-1866 Parameter Symbol Min Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD ODT HIGH time with WRITE command and BL8 ODT HIGH time without WRITE command or with WRITE command and BC4 Max Units Notes MIN = 2; MAX = 8.5 ns 40 ODTH8 MIN = 6; MAX = n/a CK ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing ODTLcnw WL - 2CK CK RTT(WR)-to-RTT,nom change skew - BC4 ODTLcnw4 4CK + ODTL off CK RTT(WR)-to-RTT,nom change skew - BL8 ODTLcnw8 6CK + ODTL off CK tADC 0.3 0.7 CK RTT dynamic change skew Write Leveling Timing tWLMRD 40 - CK tWLDQSEN 25 - CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 140 - ps Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 140 - ps Write leveling output delay tWLO 0 7.5 ns Write leveling output error tWLOE 0 2 ns First DQS, DQS# rising edge DQS, DQS# delay 39 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions RTT,nom-to-RTT(WR) change skew 2Gb: x4, x8, x16 DDR3 SDRAM Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Parameters are applicable with 0C TC +95C and VDD/VDDQ = +1.5V 0.075V. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/ DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/ ns for differential inputs in the range between VIL(AC) and VIH(AC). All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine the correct number of clocks (Table 57 (page 87) uses CK or tCK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VDDQ/ 2 for single-ended signals and the crossing point for differential signals (see Figure 30 (page 71)). When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. The clock's tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60 kHz with an additional 1% of tCK(AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. The clock's tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. The period jitter (tJITper) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. The cycle-to-cycle jitter (tJITcc) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. The cumulative jitter error (tERRnper), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK (MIN), tLZ (DQS) MIN, tLZ (DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ (DQS) MAX, tLZ(DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCKdll_dis parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. t 29. IS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows: * For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL * For BC4 (OTF): Rising clock edge four clock cycles after WL * For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in HighZ. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 36. The refresh period is 64ms when TC is less than or equal to 85C. This equates to an average refresh rate of 7.8125s. However, nine REFRESH commands should be asserted at least once every 70.3s. When TC is greater than +85C, the refresh period is 32ms. Although JEDEC specifies tREFI as a MAX, Micron allows REFRESH commands to be burst provided that the maximum refresh period is not violated. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 22 (page 57). 39. Half-clock output parameters must be derated by the actual tERR10PER and tJITdty when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR PER (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are 10 required to be derated by subtracting both tERR10PER (MAX) and tJITdty (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turnoff time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 23 (page 60). This output load is used for ODT timings (see Figure 30 (page 71)). 41. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 58; values come from Table 56 (page 78)) to the tIS and tIH derating values (see Table 59 (page 98) and Table 60 (page 98)), respectively. Example: tIS (total setup time) = tIS (base) + tIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 60 (page 98)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/ VIL(AC) (see Figure 14 (page 50) for input signal requirements). For slew rates which fall between the values listed in Table 60 (page 98) and Table 63 (page 100), the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region," use the nominal slew rate for derating value (see Figure 33 (page 101)). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region," the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 35 (page 103)). Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region," use the nominal slew rate for derating value (see Figure 34 (page 102)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region," the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for derating value (see Figure 36 (page 104)). Table 58: Command and Address Setup and Hold Values Referenced at 1 V/ns - AC/DC-Based DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Reference tIS (base) AC175 Symbol 200 125 65 45 - ps VIH(AC)/VIL(AC) tIS (base) AC150 350 275 190 170 - ps VIH(AC)/VIL(AC) tIS (base) AC135 - - - - 65 ps VIH(AC)/VIL(AC) tIS (base) AC125 - - - - 150 ps VIH(AC)/VIL(AC) tIH (base) DC100 275 200 140 120 100 ps VIH(DC)/VIL(DC) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Table 59: Derating Values for tIS/tIH - AC175/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC175 Threshold: VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIH tIH tIS tIH tIS tIH 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Table 60: Derating Values for tIS/tIH - AC150/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIH tIH tIS tIH tIS tIH 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 4.0 V/ns PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 3.0 V/ns 2.0 V/ns 1.8 V/ns 98 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Table 61: Derating Values for tIS/tIH - AC135/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC135 Threshold: VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIH tIH tIS tIH tIS tIH 2.0 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 2 -4 2 -4 2 -4 10 4 18 12 26 20 34 30 42 46 0.8 3 -10 3 -10 3 -10 11 -2 19 6 27 14 35 24 43 40 0.7 6 -16 6 -16 6 -16 14 -8 22 0 30 8 38 18 46 34 0.6 9 -26 9 -26 9 -26 17 -18 25 -10 33 -2 41 8 49 24 0.5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.4 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Table 62: Derating Values for tIS/tIH - AC125/DC100-Based tIS, tIH Derating (ps) - AC/DC-Based AC125 Threshold: VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIH tIH tIS tIH tIS tIH 2.0 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 4 -4 4 -4 4 -4 12 4 20 12 28 20 36 30 44 46 0.8 6 -10 6 -10 6 -10 14 -2 22 6 30 14 38 24 45 40 0.7 11 -16 11 -16 11 -16 19 -8 27 0 35 8 43 18 51 34 0.6 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0.4 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4.0 V/ns PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 3.0 V/ns 2.0 V/ns 1.8 V/ns 99 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Table 63: Minimum Required Time tVAC Above VIH(AC) for Valid Transition Below VIL(AC) Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps) >2.0 75 175 175 200 2.0 57 170 160 190 1.5 50 167 150 180 1.0 38 163 140 170 0.9 34 162 130 160 0.8 29 161 120 150 0.7 22 159 110 n/a 0.6 13 155 105 n/a 0.5 0 150 n/a n/a <0.5 0 150 n/a n/a PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Figure 33: Nominal Slew Rate and tVAC for tIS (Command and Address - Clock) tIS tIS tIH tIH CK CK# DQS# DQS VDDQ tVAC VIH(AC)min VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(DC)max tVAC VSS TF Setup slew rate falling signal = Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN TR VREF(DC) - VIL(AC)max TF Setup slew rate = rising signal VIH(AC)min - VREF(DC) TR 1. Both the clock and the strobe are drawn on different time scales. 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Figure 34: Nominal Slew Rate for tIH (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC)max VIL(AC)max VSS TF TR Hold slew rate rising signal = Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN VREF(DC) - VIL(DC)max TR Hold slew rate falling signal = VIH(DC)min - VREF(DC) TF 1. Both the clock and the strobe are drawn on different time scales. 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Figure 35: Tangent Line for tIS (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ tVAC Nominal line VIH(AC)min VREF to AC region VIH(DC)min Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(DC)max Nominal line tVAC VSS TR Setup slew rate rising signal = TF Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Tangent line (VIH(DC)min - VREF(DC)) TR Tangent line (VREF(DC) - VIL(AC)max) Setup slew rate falling signal = TF 1. Both the clock and the strobe are drawn on different time scales. 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating Figure 36: Tangent Line for tIH (Command and Address - Clock) tIS tIH tIS tIH CK CK# DQS# DQS VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangen t line VREF(DC) DC to VREF region Tangen t line Nominal line VIL( DC)max VIL( AC)max VSS TR Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN TR Hold slew rate rising signal = Tangent line (VREF(DC) - VIL(DC)max) Hold slew rate falling signal = Tangent line (VIH(DC)min - VREF(DC)) TR TF 1. Both the clock and the strobe are drawn on different time scales. 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 64 (page 105); values come from Table 56 (page 78)) to the tDS and tDH derating values (see Table 65 (page 106)), respectively. Example: tDS (total setup time) = tDS (base) + tDS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 68 (page 107)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH/ VIL(AC). For slew rates which fall between the values listed in Table 66 (page 106), the derating values may obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded "VREF(DC)-to-AC region," use the nominal slew rate for derating value (see Figure 37 (page 108)). If the actual signal is later than the nominal slew rate line anywhere between the shaded "VREF(DC)-to-AC region," the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 39 (page 110)). Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded "DC-to-VREF(DC) region," use the nominal slew rate for derating value (see Figure 38 (page 109)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded "DC-to-VREF(DC) region," the slew rate of a tangent line to the actual signal from the "DC-to-VREF(DC) region" is used for derating value (see Figure 40 (page 111)). Table 64: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) - AC/DC-Based Symbol DDR3-800 DDR3-1600 DDR3-1866 Units Reference tDS (base) AC175 75 25 - - - ps VIH(AC)/VIL(AC) tDS (base) AC150 125 75 30 10 - ps VIH(AC)/VIL(AC) tDS (base) AC135 - - - - 0 ps VIH(AC)/VIL(AC) 150 100 65 45 20 ps VIH(DC)/VIL(DC) tDH (base) DC100 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN DDR3-1066 DDR3-1333 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Table 65: Derating Values for tDS/tDH - AC175/DC100-Based Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns DQ Slew Rate V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 88 50 88 50 88 50 1.5 59 34 59 34 59 34 67 42 1.0 0 0 0.9 0 0 0 0 8 8 16 16 -2 -4 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 26 24 -3 -8 5 0 13 8 21 18 29 34 -1 -10 7 -2 15 8 23 24 -11 -16 -2 -6 5 10 -30 -26 -22 -10 0.8 0.7 0.6 0.5 0.4 Table 66: Derating Values for tDS/tDH - AC150/DC100-Based Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns DQ Slew Rate V/ns tDS tDH tDS tDH tDS tDH 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 1.0 0 0 0 0 0 0 -4 0.9 0.8 0.7 1.8 V/ns tDS tDH 34 58 42 0 8 0 -4 0 -10 tDH 8 16 16 8 4 16 8 -2 16 8 -8 0.6 0.5 0.4 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1.6 V/ns tDS 106 1.4 V/ns tDS tDH 12 24 20 6 24 16 0 15 -10 1.2 V/ns tDS tDH 14 32 24 24 8 32 23 -2 31 14 -16 1.0 V/ns tDS tDH 18 40 34 8 39 24 22 -6 30 10 7 -26 15 -10 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Table 67: Derating Values for tDS/tDH - AC135/DC100-Based Shaded cells indicate slew rate combinations not supported tDS, tDH Derating (ps) - AC/DC-Based DQS, DQS# Differential Slew Rate DQ Slew Rate V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 68 50 68 50 68 50 1.5 45 34 45 34 45 34 1.0 0 0 0 0 0 2 -4 2 0.9 53 42 0 8 8 16 16 -4 10 4 18 12 0.8 0.7 0.6 0.5 0.4 Table 68: Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid Transition tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps) Slew Rate (V/ns) Min Min Min >2.0 75 175 187 2.0 57 170 165 1.5 50 167 121 1.0 38 163 50 0.9 34 162 20 0.8 29 161 n/a 0.7 22 159 n/a 0.6 13 155 n/a 0.5 0 150 n/a <0.5 0 150 n/a PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Figure 37: Nominal Slew Rate and tVAC for tDS (DQ - Strobe) CK CK# DQS# DQS tDH tDS tDS tDH VDDQ tVAC VIH(AC)MIN VREF to AC region VIH(DC)min Nominal slew rate VREF(DC) Nominal slew rate VIL(DC)max VREF to AC region VIL(AC)max tVAC VSS TF Setup slew rate = falling signal Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN TR VREF(DC) - VIL(AC)max TF Setup slew rate = rising signal VIH(AC)min - VREF(DC) TR 1. Both the clock and the strobe are drawn on different time scales. 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Figure 38: Nominal Slew Rate for tDH (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC)min VIH(DC)min Nominal slew rate DC to VREF region VREF(DC) Nominal slew rate DC to VREF region VIL(DC)max VIL(AC)max VSS TR Hold slew rate = rising signal Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN VREF(DC) - VIL(DC)max TR TF Hold slew rate = falling signal VIL(DC)min - VREF(DC) TF 1. Both the clock and the strobe are drawn on different time scales. 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Figure 39: Tangent Line for tDS (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ Nominal line tVAC VIH(AC)min VIH(DC)min VREF to AC region Tangent line VREF(DC) Tangent line VIL(DC)max VREF to AC region VIL(AC)max Nominal line tVAC VSS TF TR Setup slew rate rising signal = Tangent line (VIH(AC)min - VREF(DC)) Setup slew rate falling signal = Tangent line (VREF(DC) - VIL(AC)max) TR TF Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. Both the clock and the strobe are drawn on different time scales. 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating Figure 40: Tangent Line for tDH (DQ - Strobe) CK CK# DQS# DQS tDS tDH tDS tDH VDDQ VIH(AC)min Nominal line VIH(DC)min DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC)max VIL(AC)max VSS TR Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN TF Hold slew rate rising signal = Tangent line (VREF(DC) - VIL(DC)max) Hold slew rate falling signal = Tangent line (VIH(DC)min - VREF(DC)) TR TF 1. Both the clock and the strobe are drawn on different time scales. 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands - Truth Tables Commands - Truth Tables Table 69: Truth Table - Command Notes 1-5 apply to the entire table CKE Symbol Prev. Cycle MODE REGISTER SET MRS H H L L L L BA REFRESH REF H H L L L H V V V V V Self refresh entry SRE H L L L L H V V V V V 6 Self refresh exit SRX L H H V V V V V V V V 6, 7 L H H H V V L V V H V Function Single-bank PRECHARGE Next BA Cycle CS# RAS# CAS# WE# [2:0] An A12 A10 A[11, 9:0] Notes OP code PRE H H L L H L BA PRECHARGE all banks PREA H H L L H L V Bank ACTIVATE ACT H H L L H H BA WRITE BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8 BC4OTF WRS4 H H L H L L BA RFU L L CA 8 BL8OTF WRS8 H H L H L L BA RFU H L CA 8 BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8 BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8 BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8 BC4OTF RDS4 H H L H L H BA RFU L L CA 8 BL8OTF RDS8 H H L H L H BA RFU H L CA 8 BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8 BL8OTF L H L H BA RFU H H CA 8 H H H V V V V V 9 WRITE with auto precharge READ READ with auto precharge Row address (RA) RDAPS8 H H NO OPERATION NOP H H Device DESELECTED DES H H H X X X X X X X X 10 Power-down entry PDE H L L H H H V V V V V 6 Power-down exit PDX L H V V V V V 6, 11 12 H V V V L H H H H V V V ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-dependent. 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands - Truth Tables 2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT does not affect the states described in this table. 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. "V" means "H" or "L" (a defined logic level), and "X" means "Don't Care." 6. See Table 70 (page 114) for additional information on CKE transition. 7. Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. 12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initialization) or ZQoper (ZQCL command after initialization). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands - Truth Tables Table 70: Truth Table - CKE Notes 1-2 apply to the entire table; see Table 69 (page 112) for additional command details CKE Current State3 Previous Cycle4 Present Cycle4 Command5 (n - 1) (n) (RAS#, CAS#, WE#, CS#) Action5 L L "Don't Care" Maintain power-down L H DES or NOP Power-down exit L L "Don't Care" Maintain self refresh L H DES or NOP Self refresh exit Bank(s) active H L DES or NOP Active power-down entry Reading H L DES or NOP Power-down entry Writing H L DES or NOP Power-down entry Precharging H L DES or NOP Power-down entry Refreshing H L DES or NOP Precharge power-down entry All banks idle H L DES or NOP Precharge power-down entry H L REFRESH Self refresh Power-down Self refresh Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Notes 6 1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH. 3. Current state = The state of the DRAM immediately prior to clock edge n. 4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge. 5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 69 (page 112)). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed. 6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied. 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands Commands DESELECT The DESELT (DES) command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION LONG The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibration during a power-up initialization and reset sequence (see Figure 49 (page 131)). This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values. The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQoper to be satisfied. ZQ CALIBRATION SHORT The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in Table 43 (page 66) and Table 44 (page 66). ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected (see Burst Order table for additional information). The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. Table 71: READ Command Summary CKE Function READ READ with auto precharge Symbol Prev. Cycle Next BA Cycle CS# RAS# CAS# WE# [3:0] An A12 A10 A[11, 9:0] BL8MRS, BC4MRS RD H L H L H BA RFU V L CA BC4OTF RDS4 H L H L H BA RFU L L CA BL8OTF RDS8 H L H L H BA RFU H L CA BL8MRS, BC4MRS RDAP H L H L H BA RFU V H CA BC4OTF RDAPS4 H L H L H BA RFU L H CA BL8OTF RDAPS8 H L H L H BA RFU H H CA WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not auto precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. Table 72: WRITE Command Summary CKE Function WRITE WRITE with auto precharge Symbol Prev. Cycle Next BA Cycle CS# RAS# CAS# WE# [3:0] An A12 A10 A[11, 9:0] BL8MRS, BC4MRS WR H L H L L BA RFU V L CA BC4OTF WRS4 H L H L L BA RFU L L CA BL8OTF WRS8 H L H L L BA RFU H L CA BL8MRS, BC4MRS WRAP H L H L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA BL8OTF WRAPS8 H L H L L BA RFU H H CA PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto prePDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands charge. A READ or WRITE command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as "Don't Care." After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#-beforeRAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8s (maximum when TC +85C or 3.9s; maximum when TC +95C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. Self refresh may be entered with up to eight REFRESH commands being posted. After exiting self refresh (when entered with posted REFRESH commands) additional posting of REFRESH commands is allowed to the extent the maximum number of cumulative posted REFRESH commands (both pre and post self refresh) does not exceed eight REFRESH commands. The posting limit of eight REFRESH commands is a JEDEC specification; however, as long as all the required number of REFRESH commands are issued within the refresh period (64ms), exceeding the eight posted REFRESH commands is allowed. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 41: Refresh Mode T0 T2 T1 CK# CK tCK T3 tCH T4 Ta1 Valid5 NOP1 PRE Tb0 Tb1 Valid5 Valid5 NOP5 NOP5 Tb2 tCL CKE Command Ta0 NOP1 NOP1 REF NOP5 REF2 Address ACT RA All banks A10 RA One bank Bank(s)3 BA[2:0] BA DQS, DQS#4 DQ4 DM4 tRP tRFC (MIN) tRFC2 Indicates A Break in Time Scale Notes: Don't Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see Power-Down Mode (page 179)). 2. The second REFRESH is not required but depicts two back-to-back REFRESH commands. 3. "Don't Care" if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks). 4. For operations shown, DM, DQ, and DQS signals are all "Don't Care"/High-Z. 5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC (MIN) is satisfied. SELF REFRESH SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in self refresh mode, the DRAM retains data without external clocking. Self refresh mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous operating range (see Input Clock Frequency Change (page 123)). All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in self refresh mode under certain conditions: * * * * PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN VSS < VREFDQ < VDD is maintained VREFDQ is valid and stable prior to CKE going back HIGH The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid All other self refresh mode exit timing requirements are met 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands DLL Disable Mode If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: * The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6). * DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK), but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the read data up with the controller time domain when the DLL is disabled. * In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature is not supported during DLL disable mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT,nom MR1[9, 6, 2] and RTT(WR) MR2[10, 9] to 0 while in the DLL disable mode. Specific steps must be followed to switch between the DLL enable and DLL disable modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX and tCK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during self refresh mode. Thus, the required procedure for switching from the DLL enable mode to the DLL disable mode is to change frequency during self refresh: 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT,nom and RTT(WR) are High-Z), set MR1[0] to 1 to disable the DLL. 2. Enter self refresh mode after tMOD has been satisfied. 3. After tCKSRE is satisfied, change the frequency to the desired clock rate. 4. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with appropriate values. 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timings met. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 42: DLL Enable Mode to DLL Disable Mode T0 CK# CK T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Valid1 CKE Command Tf0 MRS2 SRE3 NOP tCKSRE tMOD 6 SRX4 NOP 7 tCKSRX8 NOP tXS MRS5 NOP Valid1 tMOD tCKESR ODT9 Valid1 Indicates A Break in Time Scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Don't Care Any valid command. Disable DLL by setting MR1[0] to 1. Enter SELF REFRESH. Exit SELF REFRESH. Update the mode registers with the DLL disable parameters setting. Starting with the idle state, RTT is in the High-Z state. Change frequency. Clock must be stable tCKSRX. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 43 (page 121)). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT,nom and RTT(WR) are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to 0 to enable the DLL. Wait tMRD, then set MR0[8] to 1 to enable DLL RESET. 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 43: DLL Disable Mode to DLL Enable Mode T0 CK# CK Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 CKE Th0 Valid tDLLK Command SRE1 NOP SRX2 NOP tCKSRE 7 tCKSRX9 8 MRS3 tXS MRS4 tMRD MRS5 Valid6 tMRD ODTL off + 1 x tCK tCKESR ODT10 Indicates A Break in Time Scale Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Don't Care Enter SELF REFRESH. Exit SELF REFRESH. Wait tXS, then set MR1[0] to 0 to enable DLL. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). Wait tMOD, any valid command. Starting with the idle state. Change frequency. Clock must be stable at least tCKSRX. Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is specified by the parameter tCKdll_dis. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command. WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Commands Figure 44: DLL Disable tDQSCK Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid CK# CK RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on RL (DLL disable) = AL + (CL - 1) = 5 DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 tDQSCK (dll _dis ) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+4 DI b+5 DI b+6 tDQSCK (dll _dis ) MAX DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+7 Transitioning Data Don't Care Table 73: READ Electrical Characteristics, DLL Disable Mode Parameter Symbol Access window of DQS from CK, CK# PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 122 tDQSCK (dll_dis) Min Max Units 1 10 ns Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change Input Clock Frequency Change When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the self refresh mode condition, when the DDR3 SDRAM has been successfully placed into self refresh mode and tCKSRE has been satisfied, the state of the clock becomes a "Don't Care." When the clock becomes a "Don't Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met. The precharge power-down mode condition is when the DDR3 SDRAM is in precharge power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or RTT,nom and RTT(WR) must be disabled via MR1 and MR2. This ensures RTT,nom and RTT(WR) are in an off state prior to entering precharge power-down mode, and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade (tCK [AVG] MIN to tCK [AVG] MAX). During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change Figure 45: Change Frequency During Precharge Power-Down New clock frequency Previous clock frequency T0 T1 T2 Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK tCH tCH b tCL tCK tIS tCL b tCH b tCK b tCL b tCK b tCKE tIH CKE tIS tCPDED Command tCH b tCKSRX tCKSRE tIH tCL b tCK b NOP NOP NOP NOP NOP Address MRS NOP Valid DLL RESET tAOFPD/tAOF tXP Valid tIH tIS ODT DQS, DQS# High-Z DQ High-Z DM tDLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes. 2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termination (ODT) (page 189) for exact requirements). 3. If the RTT,nom feature was enabled in the mode register prior to entering precharge powerdown mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If the RTT,nom feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling Write Leveling For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal DRAM operation, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are required. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by deskewing the trace length mismatch. A conceptual timing of this procedure is shown. Figure 46: Write Leveling Concept T0 T1 T2 T3 T5 T4 T6 T7 CK# Source CK Differential DQS CK# Tn T0 T1 T2 T3 T4 T5 T6 T4 T5 T6 CK Destination Differential DQS 0 DQ Destination CK# Tn T0 T1 0 T2 T3 CK Push DQS to capture 0-1 transition Differential DQS DQ 1 1 Don't Care PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK's status. The prime DQ for a x4 or x8 configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a x16 enable each byte lane to be leveled independently. The write leveling mode register interacts with other mode registers to correctly configure the write leveling functionality. Besides using MR1[7] to disable/enable write leveling, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst length, and so forth need to be selected as well. This interaction is shown in Table 74. It should also be noted that when the outputs are enabled during write leveling mode, the DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write leveling mode, only the DQS strobe terminations are activated and deactivated via the ODT ball. The DQ remain disabled and are not affected by the ODT ball. Table 74: Write Leveling Matrix Note 1 applies to the entire table MR1[7] MR1[12] MR1[3, 6, 9] Write Leveling Output Buffers RTT,nom Value Disabled Enabled (1) DRAM RTT,nom DRAM ODT Ball DQS DQ See normal operations Disabled (1) Write leveling not enabled 0 DQS not receiving: not terminated Prime DQ High-Z: not terminated Other DQ High-Z: not terminated 1 Low Off 20, 30, 40, 60, or 120 High On DQS not receiving: terminated by RTT Prime DQ High-Z: not terminated Other DQ High-Z: not terminated 2 n/a Low Off DQS receiving: not terminated Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated 3 40, 60, or 120 High On DQS receiving: terminated by RTT Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated 4 Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Case Notes n/a Enabled (0) Off DRAM State 2 3 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a dual-rank module and on the rank not being levelized or on any rank of a module not being levelized on a multislotted system. Case 2 may be used when DRAM are on any rank of a module not being levelized on a multislotted system. Case 3 is generally not used. Case 4 is generally used when DRAM are on the rank that is being leveled. 2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe, and all RTT,nom values are allowed. This simulates a normal standby state to DQS. 3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and only some RTT,nom values are allowed. This simulates a normal write state to DQS. 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling Write Leveling Procedure A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a 1, assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a 1 in the other ranks. The memory controller may assert ODT after a tMOD delay as the DRAM will be ready to process the ODT transition. ODT should be turned on prior to DQS being driven LOW by at least ODTL on delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay requirement. The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQS toggle or multiple DQS toggles to sample CK for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during write leveling mode. The DQS must be able to distinguish the CK's rising edge within tWLS and tWLH. The prime DQ will output the CK's status asynchronously from the associated DQS rising edge CK capture within tWLO. The remaining DQ that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQ going LOW). As previously noted, DQS is an input and not an output during this process. Figure 47 (page 128) depicts the basic timing parameters for the overall write leveling procedure. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement its DQS delay setting. After the memory controller performs enough DQS toggles to detect the CK's 0-to-1 transition, the memory controller should lock the DQS delay setting for that DRAM. After locking the DQS setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling Figure 47: Write Leveling Sequence tWLH CK# CK Command MRS1 NOP2 NOP NOP NOP T1 tWLS NOP NOP NOP T2 NOP NOP NOP NOP tMOD ODT tWLDQSEN tDQSL3 tDQSH3 tDQSL3 tDQSH3 Differential DQS4 tWLMRD tWLO tWLO Prime DQ5 tWLO tWLOE Early remaining DQ tWLO Late remaining DQ Indicates a Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Undefined Driving Mode Don't Care 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. 4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure. 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling Write Leveling Mode Exit Procedure After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. Figure 48 (page 129) depicts a general procedure in exiting write leveling mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the DRAM. Some MRS commands may be issued after tMRD (at Td1). Figure 48: Exit Write Leveling CK# CK Command T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 NOP NOP NOP NOP NOP NOP NOP MRS NOP tMRD Valid NOP Valid Address MR1 tIS Valid Valid tMOD ODT ODTL off RTT,nom RTT DQS, RTT DQS# tAOF (MAX) DQS, DQS# RTT(DQ) tWLO + tWLOE DQ CK = 1 Indicates a break in time scale Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN tAOF (MIN) Undefined Driving Mode Transitioning Don't Care 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Initialization Initialization The following sequence is required for power up and initialization, as shown in Figure 49 (page 131): 1. Apply power. RESET# is recommended to be below 0.2 x VDDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT, may be undefined. During power-up, either of the following conditions may exist and must be met: 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN * Condition A: - VDD and VDDQ are driven from a single-power converter output and are ramped with a maximum delta voltage between them of V 300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side, and must be greater than or equal to VSSQ and VSS on the other side. - Both VDD and VDDQ power supplies ramp to VDD,min and VDDQ,min within tV DDPR = 200ms. - VREFDQ tracks VDD x 0.5, VREFCA tracks VDD x 0.5. - VTT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup. * Condition B: - VDD may be applied before or at the same time as VDDQ. - VDDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA. - No slope reversals are allowed in the power supply ramp for this condition. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least 200s to begin the initialization process. ODT will remain in the High-Z state while RESET# is LOW and until CKE is registered HIGH. CKE must be LOW 10ns prior to RESET# transitioning HIGH. After RESET# transitions HIGH, wait 500s (minus one clock) with CKE LOW. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). Issue an MRS command to MR3 with the applicable settings. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to normal operation, tZQinit must be satisfied. When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for normal operation. 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Initialization Figure 49: Initialization Sequence T (MAX) = 200ms VDD VDDQ VTT See power-up conditions in the initialization sequence text, set up 1 VREF Power-up ramp tVTD Stable and valid clock T0 T1 tCK Tc0 Tb0 Ta0 Td0 CK# CK tCKSRX tCL tCL tIOz = 20ns RESET# tIS T (MIN) = 10ns CKE Valid ODT Valid tIS Command NOP MRS MRS MRS MRS Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Valid ZQCL DM BA[2:0] Valid Valid A10 = H Valid DQS DQ RTT T = 200s (MIN) T = 500s (MIN) MR2 All voltage supplies valid and stable tMRD tMRD tMRD tXPR MR3 MR1 with DLL enable tMOD MR0 with DLL reset tZQinit ZQ calibration tDLLK DRAM ready for external commands Normal operation Indicates A Break in Time Scale PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 131 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Registers Mode Registers Mode registers (MR0-MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the mode register set (MRS) command during initialization, and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or until the device loses power. Contents of a mode register can be altered by reexecuting the MRS command. If the user chooses to modify only a subset of the mode register's variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands. Figure 50: MRS to MRS Command Timing (tMRD) CK# T0 T1 T2 Ta0 Ta1 Ta2 MRS1 NOP NOP NOP NOP MRS2 CK Command tMRD Address Valid Valid CKE3 Indicates A Break in Time Scale Notes: Don't Care 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must be satisfied, and no data bursts can be in progress. 2. tMRD specifies the MRS to MRS command minimum cycle time. 3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see PowerDown Mode (page 179)). 4. For a CAS latency change, tXPDLL timing must be met before any nonMRS command. The controller must also wait tMOD before initiating any nonMRS commands (excluding NOP and DES). The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) Figure 51: MRS to nonMRS Command Timing (tMOD) T0 T1 T2 Ta0 Ta1 Ta2 MRS NOP NOP NOP NOP non MRS CK# CK Command tMOD Address Valid Valid Valid CKE Old setting New setting Updating setting Indicates A Break in Time Scale Notes: Don't Care 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). 2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be issued. 3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMOD (MIN) is satisfied at Ta2. 4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time power-down may occur (see Power-Down Mode (page 179)). Mode Register 0 (MR0) The base register, MR0, is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in Figure 52 (page 134). Burst Length Burst length is defined by MR0[1: 0]. Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed), or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst length is set to 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Figure 52: Mode Register 0 (MR0) Definitions M16 M15 BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 17 16 15 14 13 12 11 10 01 0 0 01 01 PD WR Mode register 0 (MR0) 9 8 7 6 5 4 3 2 DLL 01 CAS# latency BT CL 1 0 BL M1 M0 Mode Register 0 0 Mode register 0 (MR0) 0 1 Mode register 1 (MR1) M12 Precharge PD 1 0 Mode register 2 (MR2) 0 DLL off (slow exit) 0 1 1 Mode register 3 (MR3) 1 DLL on (fast exit) 1 Note: 0 Fixed BL8 0 1 4 or 8 (on-the-fly via A12) No 1 0 Fixed BC4 (chop) Yes 1 1 Reserved M8 DLL Reset M11 M10 M9 Write Recovery Burst Length 0 M3 READ Burst Type 0 0 0 Reserved M6 M5 M4 M2 CAS Latency 0 0 0 0 Reserved 0 Sequential (nibble) 0 0 1 5 0 0 1 0 5 1 Interleaved 0 1 0 6 0 1 0 0 6 0 1 1 7 0 1 1 0 7 1 0 0 8 1 0 0 0 8 1 0 1 10 1 0 1 0 9 1 1 0 12 1 1 0 0 10 1 1 1 14 1 1 1 0 11 0 0 0 1 12 0 0 1 1 13 1. MR0[17, 14, 13, 7] are reserved for future use and must be programmed to 0. Burst Type Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3] (see Figure 52 (page 134)). The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) Table 75: Burst Order Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes 4 chop READ 000 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2 001 1, 2, 3, 0, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 1, 2 010 2, 3, 0, 1, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 1, 2 011 3, 0, 1, 2, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 1, 2 100 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 1, 2 101 5, 6, 7, 4, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 1, 2 110 6, 7, 4, 5, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 1, 2 WRITE 8 READ WRITE Notes: 111 7, 4, 5, 6, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 1, 2 0VV 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 3, 4 1VV 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X 1, 3, 4 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1 VVV 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. 2. Z = Data and strobe output drivers are in tri-state. 3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins. 4. X = "Don't Care." DLL RESET DLL RESET is defined by MR0[8] (see Figure 52 (page 134)). Programming MR0[8] to 1 activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of 0 after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] (see Figure 52 (page 134)). Write recovery values of 5, 6, 7, 8, 10, 12, or 14 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) tWR (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]). Precharge Power-Down (Precharge PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, tXP must be satisfied when exiting (see Power-Down Mode (page 179)). CAS Latency (CL) The CL is defined by MR0[6:4], as shown in Figure 52 (page 134). CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, or 13. DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. on page through Table 53 (page 75) indicate the CLs supported at various operating frequencies. Figure 53: READ Latency T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal tDQSCK and nominal tDSDQ. 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) Mode Register 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 54 (page 137). The MR1 register is programmed via the MRS command and retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation. Figure 54: Mode Register 1 (MR1) Definition BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 17 16 1 0 M16 M15 15 14 13 12 1 0 1 0 11 10 9 8 7 6 5 1 1 1 0 Q Off TDQS 0 RTT 0 WL RTT ODS 4 3 2 1 0 AL RTT ODS DLL Mode register 1 (MR1) Mode Register 0 0 Mode register set 0 (MR0) M12 Q Off M11 TDQS 0 1 Mode register set 1 (MR1) 0 Enabled 0 Disabled 1 0 Mode register set 2 (MR2) 1 Disabled 1 Enabled 1 1 Mode register set 3 (MR3) 2 M9 M6 M2 M0 DLL Enable 0 Enable (normal) 1 Disable M5 M1 Output Drive Strength 3 M7 Write Levelization RTT,nom (ODT) RTT,nom (ODT) Non-Writes Writes 0 Disable (normal) 1 Enable 0 0 0 RTT,nom disabled RTT,nom disabled 0 0 1 RZQ/4 (60 [NOM]) RZQ/4 (60 [NOM]) 0 0 RZQ/6 (40 [NOM]) 0 1 RZQ/7 (34 [NOM]) 1 0 Reserved 1 1 Reserved 0 1 0 RZQ/2 (120 [NOM]) RZQ/2 (120 [NOM]) 0 1 1 Notes: RZQ/6 (40 [NOM]) RZQ/6 (40 [NOM]) M4 M3 Additive Latency (AL) 1 0 0 RZQ/12 (20 [NOM]) n/a 0 0 Disabled (AL = 0) 1 0 1 RZQ/8 (30 [NOM]) n/a 0 1 AL = CL - 1 1 1 0 Reserved Reserved 1 0 AL = CL - 2 1 1 1 Reserved Reserved 1 1 Reserved 1. MR1[17, 14, 13, 10, 8] are reserved for future use and must be programmed to 0. 2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available for use. 3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values are available for use. DLL Enable/DLL Disable The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 54 (page 137). The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disabled when entering SELF REFRESH operation and is automatically reenabled and reset upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until it is reenabled and reset. The DRAM is not tested to check--nor does Micron warrant compliance with--normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined: * ODT is not allowed to be used * The output data is no longer edge-aligned to the clock * CL and CWL can only be six clocks When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see DLL Disable Mode (page 119)). Disabling the DLL also implies the need to change the clock frequency (see Input Clock Frequency Change (page 123)). Output Drive Strength The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34 [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the ZQ ball and VSSQ. The value of the resistor must be 240 1%. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifications are met during an update. To meet the 34 specification, the output drive strength must be set to 34 during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset procedure. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 54 (page 137). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used during Idd characterization of the READ current and during tDQSS margining (write leveling) only. TDQS Enable Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that provides termination resistance (RTT) and may be useful in some system configurations. TDQS is not supported in x4 or x16 configurations. When enabled via the mode register (MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#. In contrast to the RDQS function of DDR2 SDRAM, DDR3's TDQS provides the termination resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided by TDQS; thus, Ron does not apply to TDQS and TDQS#. The TDQS and DM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) functions share the same ball. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. On-Die Termination ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure 54 (page 137)). The RTT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240. Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain off during a READ burst.RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Additionally, write accesses with dynamic ODT enabled (RTT(WR)) temporarily replacesRTT,nom with RTT(WR). The actual effective termination, RTT(EFF), may be different from the RTT targeted due to nonlinearity of the termination. For RTT(EFF) values and calculations (see On-Die Termination (ODT) (page 189)). The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when RTT is turned on (ODTL on) and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2]. Timings for ODT are detailed in On-Die Termination (ODT) (page 189). WRITE LEVELING The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 54 (page 137). Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems which use fly-by topology-based modules. Write leveling timing and detailed operation information is provided in Write Leveling (page 125). POSTED CAS ADDITIVE Latency POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL, as shown in Figure 55 (page 140). MR1[4, 3] enable the user to program the DDR3 SDRAM with AL = 0, CL - 1, or CL - 2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is ACTIVATE to READ or WRITE + AL tRCD (MIN) must be satisfied. Assuming tRCD PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 141)). Examples of READ and WRITE latencies are shown in Figure 55 (page 140) and Figure 56 (page 141). Figure 55: READ Latency (AL = 5, CL = 6) BC4 CK# T0 T1 ACTIVE n READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK Command tRCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates A Break in Time Scale PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 140 Transitioning Data Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) Mode Register 2 (MR2) The mode register 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (RTT(WR)). These functions are controlled via the bits shown in Figure 56. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Figure 56: Mode Register 2 (MR2) Definition BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 17 16 15 14 13 12 11 10 9 8 7 6 2 1 1 1 1 1 1 1 0 0 0 0 0 RTT(WR) 0 SRT ASR 5 M16 M15 Mode Register 3 2 0 M5 M4 M3 1 1 0 1 0 0 1 Mode register 2 (MR2) CAS Write Latency (CWL) 5 CK (tCK 2.5ns) 0 0 Mode register set 0 (MR0) 0 Normal (0C to 85C) 0 0 0 0 1 Mode register set 1 (MR1) 1 Extended (0C to 95C) 0 0 1 1 0 Mode register set 2 (MR2) 0 1 0 1 1 Mode register set 3 (MR3) 0 1 1 8 CK (1.5ns > tCK 1.25ns) 1 0 0 9 CK (1.25ns > tCK 1.07ns) 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M10 M9 Notes: M7 Self Refresh Temperature 4 CWL 0 Address bus Dynamic ODT (RTT(WR)) 0 0 RTT(WR) disabled 0 1 RZQ/4 1 0 RZQ/2 1 1 Reserved M6 0 Auto Self Refresh (Optional) Disabled: Manual 6 CK (2.5ns > tCK 1.875ns) 7 CK (1.875ns > tCK 1.5ns) 1 Enabled: Automatic 1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 2. On die revision A, ASR is not available; MR2[6] must be programmed to a "0," and if operating self refresh mode above 85C, use SRT, MR2[7]. CAS Write Latency (CWL) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 56). The overall WRITE latency (WL) is equal to CWL + AL (Figure 54 (page 137)). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) Figure 57: CAS Write Latency BC4 CK# T0 T1 ACTIVE n WRITE n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK Command tRCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don't Care AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled, the self refresh mode's refresh rate is assumed to be at the normal 85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a TC of +85C while in self refresh unless the user enables the SRT feature listed below when the TC is between +85C and +95C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to 2X when the case temperature exceeds +85C. This enables the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of +95C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (+85C) only, meaning if ASR is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 178)). SELF REFRESH TEMPERATURE (SRT) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode's refresh rate is assumed to be at the normal +85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a TC of +85C while in self refresh mode unless the user enables ASR. When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regardless of the case temperature. This enables the user to operate the DRAM beyond the standard +85C limit up to the optional extended temperature range of +95C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (+85C) only, meaning if SRT is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 178)). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) SRT vs. ASR If the normal case temperature limit of 85C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of +95C is needed, the user is required to provide a 2X refresh rate during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2X rate. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM's internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1X to 2X over the supported temperature range. One other disadvantage with ASR is the DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature of +85C. Although the DRAM will support data integrity when it switches from a 1X to a 2X refresh rate, it may switch at a lower temperature than +85C. Since only one mode is neccesary, SRT and ASR cannot be enabled at the same time. DYNAMIC ODT The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected. This new DDR3 SDRAM feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination on-the-fly. With dynamic ODT (RTT(WR)) enabled, the DRAM switches from normal ODT (RTT,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst and subsequently switches back to ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, the RTT,nom value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of one other. Dynamic ODT is not available during write leveling mode, regardless of the state of ODT (RTT,nom). For details on dynamic ODT operation, refer to On-Die Termination (ODT) (page 189). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) Mode Register 3 (MR3) The mode register 3 (MR3) controls additional functions and features not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 58 (page 144). The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Figure 58: Mode Register 3 (MR3) Definition BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 17 01 A4 A3 A2 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 01 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF Address bus Mode register 3 (MR3) Mode Register M2 MPR Enable 0 0 Mode register set (MR0) 0 Normal DRAM operations2 0 0 MPR READ Function Predefined pattern3 0 1 Mode register set 1 (MR1) 1 Dataflow from MPR 0 1 Reserved 1 0 Mode register set 2 (MR2) 1 0 Reserved 1 1 Mode register set 3 (MR3) 1 1 Reserved M16 M15 Notes: 16 1 A7 A6 A5 M1 M0 1. MR3[17 and 14:3] are reserved for future use and must all be programmed to 0. 2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3. Intended to be used for READ synchronization. MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 59 (page 145). If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 77 (page 146)). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/RDAP commands are not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) Figure 59: Multipurpose Register (MPR) Block Diagram Memory core MR3[2] = 0 (MPR off) Multipurpose register predefined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQS, DQS# Notes: 1. A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. Table 76: MPR Functional Description of MR3 Bits MR3[2] MR3[1:0] MPR MPR READ Function 0 "Don't Care" 1 A[1:0] (see Table 77 (page 146)) Function Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 MPR Functional Description The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16, DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining DQ driven LOW, or for all DQ to output the MPR data . The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is locked as required. MPR addressing for a valid MPR read is as follows: * A[1:0] must be set to 00 as the burst order is fixed per nibble * A2 selects the burst order: - BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7 * For burst chop 4 cases, the burst order is switched on the nibble base along with the following: - A2 = 0; burst order = 0, 1, 2, 3 - A2 = 1; burst order = 4, 5, 6, 7 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) * Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB * A[9:3] are a "Don't Care" * A10 is a "Don't Care" * A11 is a "Don't Care" * A12: Selects burst chop mode on-the-fly, if enabled within MR0 * A13 is a "Don't Care" * BA[2:0] are a "Don't Care" MPR Register Address Definitions and Bursting Order The MPR currently supports a single data format. This data format is a predefined read pattern for system calibration. The predefined pattern is always a repeating 0-1 bit pattern. Examples of the different types of predefined READ pattern bursts are shown in the following figures. Table 77: MPR Readouts and Burst Order Bit Mapping MR3[2] MR3[1:0] Function 1 00 READ predefined pattern for system calibration 1 1 1 01 RFU 10 RFU 11 RFU Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Burst Length Read A[2:0] BL8 000 Burst order: 0, 1, 2, 3, 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1 BC4 000 Burst order: 0, 1, 2, 3 Predefined pattern: 0, 1, 0, 1 BC4 100 Burst order: 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Burst Order and Data Pattern 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent. 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 PREA MRS READ1 NOP NOP NOP NOP NOP NOP NOP NOP MRS NOP NOP Valid CK# CK Command tRP tMPRR tMOD tMOD Bank address 3 Valid 3 A[1:0] 0 02 Valid A2 1 02 0 A[9:3] 00 Valid 00 0 Valid 0 A11 0 Valid 0 A12/BC# 0 Valid1 0 A[15:13] 0 Valid 0 A10/AP 1 147 RL DQS, DQS# Indicates A Break in Time Scale Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. DQ PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout CK# CK Command T0 Ta Tb PREA MRS READ1 tRP Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 READ1 NOP NOP NOP NOP NOP NOP NOP NOP NOP tCCD tMOD Tc10 MRS 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 02 12 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid Valid1 0 A[15:13] 0 Valid Valid 0 1 Valid tMOD tMPRR Bank address A10/AP Td 148 RL DQS, DQS# DQ Indicates A Break in Time Scale Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. RL PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 62: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 PREA MRS READ1 READ1 NOP NOP NOP NOP NOP NOP NOP Tc8 Tc9 MRS NOP Tc10 Td NOP Valid CK# CK Command tRF tMPRR tCCD tMOD tMOD Bank address 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 03 14 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid1 Valid1 0 A[15:13] 0 Valid Valid 0 A10/AP 1 149 RL DQS, DQS# DQ Indicates A Break in Time Scale Notes: 1. 2. 3. 4. READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. RL PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 READ1 NOP NOP NOP NOP NOP NOP NOP Tc8 Tc9 MRS NOP Tc10 Td NOP Valid CK# CK Command PREA READ1 MRS tRF tCCD tMOD tMPRR tMOD Bank address 3 Valid Valid 3 A[1:0] 0 02 02 Valid A2 1 13 04 0 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A11 0 Valid Valid 0 A12/BC# 0 Valid1 Valid1 0 A[15:13] 0 Valid Valid 0 A10/AP 1 150 RL DQS, DQS# DQ Indicates A Break in Time Scale Notes: 1. 2. 3. 4. READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. RL 2Gb: x4, x8, x16 DDR3 SDRAM MODE REGISTER SET (MRS) Command MPR Read Predefined Pattern The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using the read out predetermined read calibration pattern. The example is to perform multiple reads from the multipurpose register to do system level read timing calibration based on the predetermined and standardized pattern. The following protocol outlines the steps used to perform the read calibration: 1. Precharge all banks 2. After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subsequent reads and loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available 3. Data WRITE operations are not allowed until the MPR returns to the normal DRAM state 4. Issue a read with burst order information (all other address pins are "Don't Care"): 5. 6. 7. 8. * A[1:0] = 00 (data burst order is fixed starting at nibble) * A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) * A12 = 1 (use BL8) After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern (0, 1, 0, 1, 0, 1, 0, 1) The memory controller repeats the calibration reads until read data capture at memory controller is optimized After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = "Don't Care" to the normal DRAM state. All subsequent read and write accesses will be regular reads and writes from/to the DRAM array When tMRD and tMOD are satisfied from the last MRS, the regular DRAM commands (such as activate a memory bank for regular read or write access) are permitted MODE REGISTER SET (MRS) Command The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed: * * * * BA2 = 0, BA1 = 0, BA0 = 0 for MR0 BA2 = 0, BA1 = 0, BA0 = 1 for MR1 BA2 = 0, BA1 = 1, BA0 = 0 for MR2 BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command (see Figure 50 (page 132)). There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 50 (page 132) and Figure 51 (page 133). Violating either of these requirements will result in unspecified operation. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ZQ CALIBRATION Operation ZQ CALIBRATION Operation The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240 (1%) external resistor is connected from the DRAM's ZQ ball to VSSQ. DDR3 SDRAM need a longer time to calibrate RON and ODT at power-up initialization and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example of ZQ calibration timing is shown below. All banks must be precharged and tRP must be met before ZQCL or ZQCS commands can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS command may be issued to another DRAM) can be performed on the DRAM channel by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the ZQ ball's current consumption path to reduce power. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired. In dual-rank systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQinit, tZQoper, or tZQcs between ranks. Figure 64: ZQ Calibration Timing (ZQCL and ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL NOP NOP NOP Valid Valid ZQCS NOP NOP NOP Valid Address Valid Valid Valid A10 Valid Valid Valid CK# CK Command CKE 1 Valid Valid 1 Valid ODT 2 Valid Valid 2 Valid DQ 3 Activities 3 High-Z tZQinit or tZQoper High-Z tZQCS Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Activities Don't Care 1. CKE must be continuously registered HIGH during the calibration procedure. 2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure. 3. All devices connected to the DQ bus should be High-Z during calibration. 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ACTIVATE Operation ACTIVATE Operation Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. After a row is opened with an ACTIVATE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the DRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement that (ACTIVATE-to-READ/WRITE) + AL tRCD (MIN) (see POSTED CAS ADDITIVE Latency). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-toWRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC. A subsequent ACTIVATE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVATE commands to different banks is defined by tRRD. No more than four bank ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of banks already opened or closed. Figure 65: Example: Meeting tRRD (MIN) and tRCD (MIN) T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR Address Row BA[2:0] Bank x CK# CK Row Col Bank y Bank y tRRD tRCD Indicates A Break in Time Scale PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 153 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ACTIVATE Operation Figure 66: Example: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP ACT NOP ACT NOP NOP ACT CK Command Address BA[2:0] Row Row Row Row Row Bank a Bank b Bank c Bank d Bank ey tRRD tFAW Indicates A Break in Time Scale PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 154 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation READ Operation READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 67 shows an example of RL based on a CL setting of 8 and an AL setting of 0. Figure 67: READ Latency CK# T0 T7 T8 T9 T10 T11 T12 T12 READ NOP NOP NOP NOP NOP NOP NOP CK Command Address Bank a, Col n CL = 8, AL = 0 DQS, DQS# DO n DQ Indicates A Break in Time Scale Notes: Transitioning Data Don't Care 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The low state on DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 78 (page 163). A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 78 (page 163). Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 68 (page 157). If BC4 is enabled, tCCD must still be met which will cause a gap in the data output, as shown in Figure 69 (page 157). Nonconsecutive read data is reflected in Fig- PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation ure 70 (page 158). DDR3 SDRAM does not allow interrupting or truncating any READ burst. Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 71 (page 158) (BC4 is shown in Figure 72 (page 159)). To ensure the read data is completed before the write data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD - WL + 2tCK. A READ burst may be followed by a PRECHARGE command to the same bank provided auto precharge is not activated. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Examples for BL8 are shown in Figure 73 (page 159) and BC4 in Figure 74 (page 160). Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge, which is AL + tRTP cycles after the READ command. DRAM support a tRAS lockout feature (see Figure 76 (page 160)). If tRAS (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point at which the internal precharge happens (not at the next rising clock edge after this event). The time from READ with auto precharge to the next ACTIVATE command to the same bank is AL + (tRTP + tRP)*, where * means rounded up to the next integer. In any event, internal precharge does not start earlier than four clocks after the last 8n-bit prefetch. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 68: Consecutive READ Bursts (BL8) CK# T0 T1 READ NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 tCCD Address2 Bank, Col n Bank, Col b tRPRE tRPST DQS, DQS# DQ3 DO n RL = 5 DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 5 Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. 3. DO n (or b) = data-out from column n (or column b). 4. BL8, RL = 5 (CL = 5, AL = 0). Notes: 157 Figure 69: Consecutive READ Bursts (BC4) CK# T1 READ NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 Command1 NOP NOP READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tCCD Address2 Bank, Col n Bank, Col b tRPRE tRPST tRPST tRPRE DQS, DQS# DQ3 RL = 5 DO n DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 RL = 5 Transitioning Data Notes: Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. 3. DO n (or b) = data-out from column n (or column b). 4. BC4, RL = 5 (CL = 5, AL = 0). 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. T0 CK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 70: Nonconsecutive READ Bursts CK# T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 T7 READ NOP T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command Address Bank a, Col n NOP NOP Bank a, Col b CL = 8 CL = 8 DQS, DQS# DO n DQ DO b Transitioning Data Notes: 1. 2. 3. 4. Don't Care AL = 0, RL = 8. DO n (or b) = data-out from column n (or column b). Seven subsequent elements of data-out appear in the programmed order following DO n. Seven subsequent elements of data-out appear in the programmed order following DO b. Figure 71: READ (BL8) to WRITE (BL8) 158 CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 READ NOP NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 Address2 tWR tBL = 4 clocks Bank, Col n tWTR Bank, Col b tRPRE tRPST tWPRE tWPST DQS, DQS# DO n DQ3 RL = 5 DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI n DI n+1 DI DI n+2 n+3 DI n+4 DI n+5 DI n+6 WL = 5 Transitioning Data Notes: DI n+7 Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. READ-to-WRITE command delay = RL + tCCD + 2tCK - WL PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 72: READ (BC4) to WRITE (BC4) OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 READ NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command1 READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL Address2 Bank, Col n tWR tWTR tBL = 4 clocks Bank, Col b tRPRE tRPST tWPRE tWPST DQS, DQS# DO n DQ3 DO n+ 1 DO n+ 2 DO n+3 DI n DI n+2 DI n+ 1 DI n+ 3 RL = 5 WL = 5 Transitioning Data 1. 2. 3. 4. 159 Notes: Don't Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. DO n = data-out from column n; DI n = data-in from column b. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5). CK# T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 PRE NOP NOP NOP NOP NOP NOP NOP T13 T14 T15 T16 T17 ACT NOP NOP NOP NOP CK Command Address Bank a, Col n Bank a, (or all) Bank a, Row b tRTP tRP DQS, DQS# DQ tRAS DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Transitioning Data Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Figure 73: READ to PRECHARGE (BL8) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 74: READ to PRECHARGE (BC4) CK# T0 T1 T2 T3 T4 READ NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 PRE NOP NOP NOP NOP NOP NOP NOP T13 T14 T15 T16 T17 ACT NOP NOP NOP NOP CK Command Address Bank a, Col n Bank a, (or all) Bank a, Row b tRP tRTP DQS, DQS# DO n DQ tRAS DO n+1 DO n+2 DO n+3 Transitioning Data Don't Care Figure 75: READ to PRECHARGE (AL = 5, CL = 6) CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP T9 T10 T11 T12 T13 T14 PRE NOP NOP NOP NOP NOP T15 CK Command Address Bank a, Col n Bank a, (or all) tRTP AL = 5 ACT Bank a, Row b tRP DQS, DQS# 160 DO n DQ DO n+2 DO n+1 DO n+3 CL = 6 tRAS Don't Care Figure 76: READ with Auto Precharge (AL = 4, CL = 6) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Bank a, Col n CK# Ta0 CK NOP ACT Bank a, Row b AL = 4 tRTP (MIN) DQS, DQS# DO n DQ DO n+1 DO n+2 DO n+3 CL = 6 tRAS (MIN) tRP Indicates A Break in Time Scale Transitioning Data Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Transitioning Data 2Gb: x4, x8, x16 DDR3 SDRAM DQS to DQ output timing is shown in Figure 77 (page 162). The DQ transitions between valid data outputs must be within tDQSQ of the crossing point of DQS, DQS#. DQS must also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ preamble, the DQ balls either will be floating or terminated depending on the status of the ODT signal. Figure 78 (page 163) shows the strobe-to-clock timing during a READ. The crossing point DQS, DQS# must transition within tDQSCK of the clock crossing point. The data out has no timing relationship to clock, only to DQS, as shown in Figure 78 (page 163). Figure 78 (page 163) also shows the READ preamble and postamble. Typically, both DQS and DQS# are High-Z to save power (VDDQ). Prior to data output from the DRAM, DQS is driven LOW and DQS# is HIGH for tRPRE. This is known as the READ preamble. The READ postamble, tRPST, is one half clock from the last DQS, DQS# transition. During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the DQ will either be disabled or will continue terminating depending on the state of the ODT signal. Figure 83 (page 167) demonstrates how to measure tRPST. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 161 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 77: Data Output Timing - tDQSQ and Data Valid Window CK# T0 T1 T2 READ NOP NOP T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 RL = AL + CL Address 2 Bank, Col n tDQSQ (MAX) tDQSQ (MAX) tLZ (DQ) MIN tRPST tHZ (DQ) MAX DQS, DQS# tRPRE DQ3 (last data valid) DQ3 (first data no longer valid) tQH tQH DO DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 n DO DO DO DO DO DO DO DO n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO n All DQ collectively Data valid DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 Data valid Transitioning Data 162 Notes: NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. DO n = data-out from column n. BL8, RL = 5 (AL = 0, CL = 5). Output timings are referenced to VDDQ/2 and DLL on and locked. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 1. 2. 3. 4. 5. 6. 7. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ). Figure 79 (page 164) shows a method to calculate the point when the device is no longer driving tHZ (DQS) and tHZ (DQ) or begins driving tLZ (DQS), tLZ (DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ (DQS), tLZ (DQ), tHZ (DQS), and tHZ (DQ) are defined as single-ended. Figure 78: Data Strobe Timing - READs RL measured to this point T0 CK T1 T2 T3 T4 T5 T6 CK# tDQSCK (MIN) tLZ (DQS) MIN tDQSCK (MIN) tQSH tDQSCK (MIN) tQSH tQSL tDQSCK (MIN) tHZ (DQS) MIN tQSL DQS, DQS# early strobe tRPST tRPRE Bit 0 tLZ (DQS) MAX Bit 1 Bit 2 tDQSCK (MAX) Bit 3 Bit 4 Bit 5 tDQSCK (MAX) Bit 6 tDQSCK (MAX) Bit 7 tHZ (DQS) MAX tDQSCK (MAX) tRPST DQS, DQS# late strobe tQSH tRPRE Bit 0 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN tQSL Bit 1 tQSH Bit 2 163 tQSL Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 79: Method for Calculating tLZ and tHZ VOH - xmV VTT + 2xmV VOH - 2xmV VTT + xmV tLZ (DQS), tLZ (DQ) tHZ (DQS), tHZ (DQ) T2 T1 VOL + 2xmV VTT - xmV VOL + xmV VTT - 2xmV T1 T2 tLZ (DQS), tLZ (DQ) begin point = 2 x T1 - T2 tHZ (DQS), tHZ (DQ) end point = 2 x T1 - T2 1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK (MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK (MAX). 2. The DQS high pulse width is defined by tQSH, and the DQS low pulse width is defined by tQSL. Likewise, tLZ (DQS) MIN and tHZ (DQS) MIN are not tied to tDQSCK (MIN) (early strobe case) and tLZ (DQS) MAX and tHZ (DQS) MAX are not tied to tDQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN). Notes: Figure 80: tRPRE Timing CK VTT CK# tA tB DQS VTT Single-ended signal provided as background information tC tD VTT DQS# Single-ended signal provided as background information T1 tRPRE begins DQS - DQS# tRPRE T2 tRPRE ends Resulting differential signal relevant for tRPRE specification PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 0V 164 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 81: tRPST Timing CK VTT CK# tA DQS Single-ended signal, provided as background information VTT tB tC tD DQS# VTT Single-ended signal, provided as background information tRPST DQS - DQS# Resulting differential signal relevant for tRPST specification PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN T1 tRPST begins 165 0V T2 tRPST ends Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation WRITE Operation WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 84 (page 168) through Figure 92 (page 173), auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS following the WRITE latency (WL) clocks later and subsequent data elements will be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS, DQS#) and specified as the WRITE preamble shown in Figure 84 (page 168). The half cycle on DQS following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQS is WL clocks tDQSS. Figure 85 (page 169) through Figure 92 (page 173) show the nominal case where tDQSS = 0ns; however, Figure 84 (page 168) includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The mask occurs on the DM ball aligned to the write data. If DM is LOW, the write completes normally. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figure 85 (page 169) and Figure 86 (page 169) on Figure 86 (page 169) show concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 87 (page 170). Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figure 88 (page 170) and Figure 89 (page 171) on Figure 89 (page 171) and Figure 90 (page 172)). Data for any WRITE burst may be followed by a subsequent PRECHARGE command providing tWR has been met, as shown in Figure 91 (page 173) and Figure 92 (page 173). Both tWTR and tWR starting time may vary depending on the mode register settings (fixed BC4, BL8 versus OTF). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation Figure 82: tWPRE Timing CK VTT CK# T1 tWPRE begins DQS - DQS# 0V tWPRE T2 tWPRE ends Resulting differential signal relevant for tWPRE specification Figure 83: tWPST Timing CK VTT CK# tWPST DQS - DQS# Resulting differential signal relevant for tWPST specification PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 0V T1 tWPST begins T2 tWPST ends 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation Figure 84: WRITE Burst CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command1 WL = AL + CWL Address2 Bank, Col n tDQSS tDSH tDSH tDSH tDSH tWPRE tDQSS (MIN) tWPST DQS, DQS# tDQSH tDQSL tDQSH DI n DQ3 tDQSL DI n+1 tDQSH DI n+2 tDQSL DI n+3 tDSH tDQSH DI n+4 tDQSL DI n+5 tDSH tDQSH DI n+6 tDQSL DI n+7 tDSH tDSH tWPRE tDQSS (NOM) tWPST DQS, DQS# tDQSH tDQSL tDQSH DI n DQ3 tDQSL tDQSH tDSS tDSS DI n+1 tDQSL tDQSH tDSS DI n+2 DI n+3 tDQSL tDQSH tDSS DI n+4 DI n+5 tDQSL tDSS DI n+6 DI n+7 tDQSS tWPRE tDQSS (MAX) tWPST DQS, DQS# tDQSH tDQSL tDQSH tDSS DI n DQ3 tDQSL tDQSH tDSS DI n+1 tDQSL tDQSH tDSS DI n+2 DI n+3 tDQSL tDQSH tDSS DI n+4 DI n+5 tDQSL tDSS DI n+6 DI n+7 Transitioning Data Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. tDQSS must be met at each rising clock edge. 6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 85: Consecutive WRITE (BL8) to WRITE (BL8) CK# T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP tBL = 4 clocks NOP NOP T14 CK Command1 tCCD NOP tWR tWTR Address2 Valid Valid tWPST tWPRE DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 5 WL = 5 Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5). Notes: 169 Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF CK# T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP WRITE NOP NOP NOP NOP NOP NOP T11 T12 T13 NOP NOP NOP T14 CK tCCD NOP tWR tBL = 4 clocks tWTR Address2 Valid Valid tWPST tWPRE tWPRE tWPST DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = 5 WL = 5 Transitioning Data Notes: 1. 2. 3. 4. NOP commands are shown for ease of illustration; other commands may be valid at these times. BC4, WL = 5 (AL = 0, CWL = 5). DI n (or b) = data-in for column n (or column b). The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Command1 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 87: Nonconsecutive WRITE to WRITE CK# T0 T1 T2 T3 T4 WRITE NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command Address WRITE Valid NOP NOP NOP Valid WL = CWL + AL = 7 WL = CWL + AL = 7 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DM Transitioning Data Notes: 1. 2. 3. 4. Don't Care DI n (or b) = data-in for column n (or column b). Seven subsequent elements of data-in are applied in the programmed order following DO n. Each WRITE command may be to any bank. Shown for WL = 7 (CWL = 7, AL = 0). Figure 88: WRITE (BL8) to READ (BL8) 170 CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T11 Ta0 NOP READ CK Command1 tWTR2 Valid Valid tWPST tWPRE DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 5 Indicates A Break in Time Scale Notes: Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Address3 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 89: WRITE to READ (BC4 Mode Register Setting) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP READ CK# CK Command1 tWTR2 Address3 Valid Valid tWPRE tWPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates A Break in Time Scale 171 Notes: Transitioning Data Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF) CK# T0 T1 T2 T3 T4 T5 T6 WRITE NOP NOP NOP NOP NOP NOP T7 T8 T9 T10 NOP NOP NOP NOP T11 Tn NOP READ CK Command1 tBL = 4 clocks Address3 tWTR2 Valid Valid tWPRE tWPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 RL = 5 Indicates A Break in Time Scale Notes: Transitioning Data Don't Care 172 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 91: WRITE (BL8) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE Address Valid CK# CK Valid tWR WL = AL + CWL DQS, DQS# DI n DQ BL8 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 Indicates A Break in Time Scale Notes: Transitioning Data Don't Care 1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applied in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7). Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Ta0 Ta1 Command WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PRE Address Valid CK# CK Valid tWR WL = AL + CWL DQS, DQS# DI n DQ BC4 DI n+1 DI n+2 DI n+3 Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time (tWR) is referenced from the first rising clock edge after the last write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5. 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 93: WRITE (BC4 OTF) to PRECHARGE CK# T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Tn CK Command1 PRE tWR2 Address3 Bank, Col n Valid tWPRE tWPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates A Break In Time Scale Notes: Transitioning Data Don't Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5. DQ Input Timing Figure 84 (page 168) shows the strobe to clock timing during a WRITE. DQS, DQS# must transition within 0.25tCK of the clock transitions as limited by tDQSS. All data and data mask setup and hold timings are measured relative to the DQS, DQS# crossing, not the clock crossing. The WRITE preamble and postamble are also shown here. One clock prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble, tWPRE. Likewise, DQS must be kept LOW by the controller after the last data is written to the DRAM during the WRITE postamble, tWPST. Data setup and hold times are shown. All setup and hold times are measured from the crossing points of DQS and DQS#. These setup and hold values pertain to data input and data mask input. Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 174 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 94: Data Input Timing DQS, DQS# tWPRE DQ tDQSH tDQSL tWPST DI b DM tDS tDH Transitioning Data PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 175 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM PRECHARGE Operation PRECHARGE Operation Input A10 determines whether one bank or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] are treated as "Don't Care." After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued. SELF REFRESH Operation The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW. The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in the self refresh mode under certain conditions: * * * * VSS < VREFDQ < VDD is maintained VREFDQ is valid and stable prior to CKE going back HIGH The first WRITE operation may not occur earlier than 512 clocks after VREFDQ is valid All other self refresh mode exit timing requirements are met The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no bursts are in progress) before a self refresh entry command can be issued. ODT must also be turned off before self refresh entry by registering the ODT ball LOW prior to the self refresh entry command (see On-Die Termination (ODT) (page 189) for timing requirements). If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a "Don't Care." After the self refresh entry command is registered, CKE must be held LOW to keep the DRAM in self refresh mode. After the DRAM has entered self refresh mode, all external control signals, except CKE and RESET#, become "Don't Care." The DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters self refresh mode. The requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. First and foremost, the clock must be stable (meeting tCK specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in self refresh mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during self refresh mode (turned-off or frequency change), then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh mode, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal refresh that is already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time self refresh reentry may occur. Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, tZQoper timing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM SELF REFRESH Operation Figure 95: Self Refresh Entry/Exit Timing T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Valid Valid CK# CK tCKSRX1 tCKSRE1 tIS tIH tCPDED tIS CKE tCKESR (MIN)1 tIS ODT2 Valid ODTL RESET#2 Command SRE (REF)3 NOP NOP4 SRX (NOP) NOP5 Address Valid6 Valid7 Valid Valid tXS6, 9 tRP8 tXSDLL7, 9 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. The clock must be valid and stable meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however, tCKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a "Don't Care." 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming "Don't Care." 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. tXS is required before any commands not requiring a locked DLL. 7. tXSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, tRP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that tISXR is satisfied at Tc1. 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Extended Temperature Usage Extended Temperature Usage Micron's DDR3 SDRAM supports the optional extended temperature range of 0C to +95C, TC. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double refresh) anytime the case temperature is above +85C (and does not exceed +95C). The external refreshing requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85C or self refresh cannot be used until the case temperature is at or below +85C. Table 78 summarizes the two extended temperature options and Table 79 summarizes how the two extended temperature options relate to one another. Table 78: Self Refresh Temperature and Auto Self Refresh Description Field MR2 Bits Description Self Refresh Temperature (SRT) SRT 7 If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh: *MR2[7] = 0: Normal operating temperature range (0C to +85C) *MR2[7] = 1: Extended operating temperature range (0C to +95C) If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported *MR2[7] = 0: SRT is disabled Auto Self Refresh (ASR) ASR 6 When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values) * MR2[6] = 1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH operation * MR2[6] = 0: ASR is disabled, must use manual self refresh temperature (SRT) Table 79: Self Refresh Mode Summary MR2[6] MR2[7] (ASR) (SRT) SELF REFRESH Operation Permitted Operating Temperature Range for Self Refresh Mode 0 0 Self refresh mode is supported in the normal temperature range Normal (0C to +85C) 0 1 Self refresh mode is supported in normal and extended temper- Normal and extended (0C to +95C) ature ranges; When SRT is enabled, it increases self refresh power consumption 1 0 Self refresh mode is supported in normal and extended temper- Normal and extended (0C to +95C) ature ranges; Self refresh power consumption may be temperature-dependent 1 1 Illegal PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Power-Down Mode Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down IDD specifications are not applicable until such operations have been completed. Depending on the previous DRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 80). Timing diagrams detailing the different power-down mode entry and exits are shown in Figure 96 (page 181) through Figure 105 (page 186). Table 80: Command to Power-Down Entry Parameters DRAM Status Last Command Prior to CKE LOW1 Parameter (Min) Parameter Value Figure Idle or active ACTIVATE tACTPDEN 1tCK Figure 103 (page 185) Idle or active PRECHARGE tPRPDEN 1tCK READ or READAP tRDPDEN Active WRITE: BL8OTF, BL8MRS, BC4OTF tWRPDEN Active WRITE: BC4MRS Active Active WRITEAP: BL8OTF, BL8MRS, BC4OTF Active WRITEAP: BC4MRS tWRAPDEN Figure 104 (page 185) 1tCK Figure 99 (page 183) tWR/tCK Figure 100 (page 183) WL + 2tCK + tWR/tCK Figure 100 (page 183) RL + WL + 4tCK 4tCK + 1tCK Figure 101 (page 184) WL + 2tCK + WR + 1tCK Figure 101 (page 184) 1tCK Figure 102 (page 184) WL + 4tCK + + WR + Idle REFRESH tREFPDEN Power-down REFRESH tXPDLL Greater of 10tCK or 24ns Figure 106 (page 186) MODE REGISTER SET tMRSPDEN tMOD Figure 105 (page 186) Idle Note: 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchronous tANPD prior to CKE going LOW and remains asynchronous until tANPD + tXPDLL after CKE goes HIGH. Entering power-down disables the input and output buffers, excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when power-down is entered for the fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge powerdown mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in slow exit mode or kept on in fast exit mode. The DLL remains on when entering active power-down as well. ODT has special timing constraints when slow exit mode precharge power-down is enabled and entered. Refer to Asynchronous ODT Mode (page 201) for detailed ODT usage requirements in slow PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode exit mode precharge power-down. A summary of the two power-down modes is listed in Table 81 (page 180). While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a "Don't Care." If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for power-down duration is tPD (MAX) (9 x tREFI). The power-down states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after power-down exit latency, tXP tXPDLL, have been satisfied. A summary of the power-down modes is listed below. For specific CKE-intensive operations, for example, repeating a power-down exit to refresh to power-down entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient enough to keep the DLL properly updated. In addition to meeting tPD when the REFRESH command is used in between power-down exit and power-down entry, two other conditions must be met. First, tXP must be satisfied before issuing the REFRESH command. Second, tXPDLL must be satisfied before the next power-down may be entered. An example is shown in Figure 106 (page 186). Table 81: Power-Down Modes MR1[12] DLL State PowerDown Exit Active (any bank open) "Don't Care" On Fast tXP to any other valid command Precharged (all banks precharged) 1 On Fast tXP to any other valid command Slow tXPDLL DRAM State PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 0 Off 180 Relevant Parameters to commands that require the DLL to be locked (READ, RDAP, or ODT on) tXP to any other valid command Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 96: Active Power-Down Entry and Exit T0 T1 T2 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP Valid Ta0 CK# CK Command tCK Valid tCH tCL NOP NOP tPD tIS CKE Address tIH tIH tIS tCKE (MIN) Valid Valid tXP tCPDED Enter power-down mode Exit power-down mode Indicates A Break in Time Scale PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 181 Don't Care Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit T0 T1 T2 T4 T5 NOP NOP T3 Ta0 Ta1 NOP Valid CK# CK tCK tCH Command tCL NOP NOP tCPDED tCKE (MIN) tIH tIS CKE tIS tXP tPD Enter power-down mode Exit power-down mode Indicates A Break in Time Scale Don't Care Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit T0 T1 T2 T3 T4 Ta NOP NOP Ta1 Tb CK# CK Command tCK tCH PRE tCL NOP NOP Valid1 Valid2 tCKE (MIN) tCPDED tIS tXP tIH CKE tIS tXPDLL tPD Enter power-down mode Exit power-down mode Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL. 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 99: Power-Down Entry After READ or READ with Auto Precharge (RDAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 READ/ RDAP NOP NOP NOP NOP NOP NOP NOP NOP Ta7 Ta8 Ta10 Ta9 Ta11 Ta12 CK Command NOP tIS NOP tCPDED CKE Address Valid tPD RL = AL + CL DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DQ BC4 DI n DI n+1 DI n+3 DI n+4 DI n+ 5 DI n+6 DI n+7 DI DI n+2 n+3 tRDPDEN Power-down or self refresh entry Indicates A Break In Time Scale Transitioning Data Don't Care Figure 100: Power-Down Entry After WRITE CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tb4 CK Command NOP tIS NOP tCPDED CKE Address Valid tWR WL = AL + CWL tPD DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DI n+3 DQ BC4 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI DI n+5 n+6 DI n+7 tWRPDEN Power-down or self refresh entry1 Indicates A Break in Time Scale Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Transitioning Data Don't Care 1. CKE can go LOW 2tCK earlier if BC4MRS. 183 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 WRAP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb3 Tb4 CK Command tIS tCPDED CKE Address Valid A10 WR1 WL = AL + CWL tPD DQS, DQS# DQ BL8 DI n DI n+1 DI DI DI n+2 n+3 n+4 DQ BC4 DI n DI n+1 DI DI n+2 n+3 DI n+5 DI n+6 DI n+7 tWRAPDEN Power-down or self refresh entry2 Start internal precharge Indicates A Break in Time Scale Transitioning Data Don't Care 1. tWR is programmed through MR0[11:9] and represents tWR (MIN)ns/tCK rounded up to the next integer tCK. 2. CKE can go LOW 2tCK earlier if BC4MRS. Notes: Figure 102: REFRESH to Power-Down Entry T0 T1 T2 T3 Ta0 NOP NOP Ta1 Ta2 Tb0 CK# CK tCK Command tCH tCL REFRESH NOP tCPDED NOP Valid tCKE (MIN) tPD tIS CKE tXP (MIN) tREFPDEN tRFC (MIN)1 Indicates A Break In Time Scale Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied. 184 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 103: ACTIVATE to Power-Down Entry T0 T1 T2 T3 NOP NOP T5 T4 T6 T7 CK# CK tCK Command tCH tCL ACTIVE Address Valid tCPDED tIS tPD CKE tACTPDEN Don't Care Figure 104: PRECHARGE to Power-Down Entry T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 CK# CK tCK Command Address tCH tCL PRE All/single bank tCPDED tIS tPD CKE tPREPDEN Don't Care PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 185 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode Figure 105: MRS Command to Power-Down Entry CK# T0 CK T1 T2 tCK Command MRS Address Valid tCH Ta0 Ta1 tCL NOP Ta2 Ta3 Ta4 tCPDED NOP NOP NOP NOP tPD tMRSPDEN tIS CKE Indicates A Break in Time Scale Don't Care Figure 106: Power-Down Exit to Refresh to Power-Down Entry T0 T1 T2 T3 T4 Ta0 NOP REFRESH Ta1 Tb0 CK# CK Command tCK tCH NOP tCL NOP NOP tCPDED NOP NOP tXP1 tIH tIS CKE tIS tPD tXPDLL2 Enter power-down mode Enter power-down mode Exit power-down mode Indicates A Break in Time Scale Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. tXP must be satisfied before issuing the command. 2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. 186 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM RESET Operation RESET Operation The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (RTT) turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 187 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM RESET Operation Figure 107: RESET Sequence System RESET (warm boot) Stable and valid clock T0 T1 tCK Tc0 Tb0 Ta0 Td0 CK# CK tCL tCL T (MIN) = MAX (10ns, 5 tCK)1 T = 100ns (MIN) RESET# tIOZ = 20ns T = 10ns (MIN) tIS Valid CKE ODT Valid Valid Valid Valid ZQCL Valid tIS MRS MRS MRS MRS Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Command NOP DM BA[2:0] DQS DQ RTT Valid Valid A10 = H Valid High-Z High-Z High-Z T = 500s (MIN) MR2 All voltage supplies valid and stable tMRD tMRD tXPR MR3 DRAM ready for external commands tMRD MR1 with DLL ENABLE tMOD MR0 with DLL RESET ZQ CAL tZQinit tDLLK Normal operation Indicates a break in time scale Note: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. The minimum time required is the larger of 10ns or 5 clocks. 188 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) On-Die Termination (ODT) ODT is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration. The ODT feature is designed to improve signal integrity of the memory channel by enabling the DRAM controller to independently turn on/off the DRAM's internal termination resistance for any grouping of DRAM devices. The ODT feature is not supported during DLL disable mode (simple functional representation shown below). The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information. Figure 108: On-Die Termination ODT To other circuitry such as RCV, ... RTT VDDQ/2 Switch DQ, DQS, DQS#, DM, TDQS, TDQS# Functional Representation of ODT The value of RTT (ODT termination value) is determined by the settings of several mode register bits (see Table 85 (page 192)). The ODT ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous mode (when the DLL is off during precharge power-down or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during writes and provides OTF switching from no RTT or RTT,nom to RTT(WR). The actual effective termination, RTT(EFF), may be different from the RTT targeted due to nonlinearity of the termination. For RTT(EFF) values and calculations, see ODT Characteristics (page 57). Nominal ODT ODT (NOM) is the base termination resistance for each applicable ball, it is enabled or disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or off via the ODT ball. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 189 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) Table 82: Truth Table - ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 RTT,nom disabled, ODT off Any valid 2 000 1 RTT,nom disabled, ODT on Any valid except self refresh, read 3 000-101 0 RTT,nom enabled, ODT off Any valid 2 000-101 1 RTT,nom enabled, ODT on Any valid except self refresh, read 3 110 and 111 X RTT,nom reserved, ODT on or off Illegal 1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 191) when enabled). 2. ODT is enabled and active during most writes for proper termination, but it is not illegal to have it off during writes. 3. ODT must be disabled during reads. The RTT,nom value is restricted during writes. Dynamic ODT is applicable if enabled. Notes: Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1 (MR1) Definition. The RTT,nom termination value applies to the output pins previously mentioned. DDR3 SDRAM supports multiple RTT,nom values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240. RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access or when it is not in self refresh mode. Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is disabled. If RTT,nom is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 85 (page 192)). ODT timings are summarized in Table 83 (page 190), as well as listed in Table 56 (page 78). Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in Synchronous ODT Mode (page 196). Table 83: ODT Parameter Symbol Description Begins at Definition for All DDR3 Speed Bins Units tAON CWL + AL - 2 tCK Defined to ODTL on ODT synchronous turn on delay ODT registered HIGH RTT,on ODTL off ODT synchronous turn off delay ODT registered HIGH RTT,off tAOF CWL + AL - 2 tCK tAONPD ODT asynchronous turn on delay ODT registered HIGH RTT,on 1-9 ns tAOFPD ODT asynchronous turn off delay ODT registered HIGH RTT,off 1-9 ns ODT registered LOW 4tCK tCK ODTH4 ODT minimum HIGH time after ODT ODT registered HIGH assertion or write (BC4) or write registration with ODT HIGH ODTH8 ODT minimum HIGH time after write (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on RTT,on See Table 56 (page 78) ps tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off RTT,off 0.5tCK 0.2tCK tCK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT Dynamic ODT In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT (RTT(WR)) enabled, the DRAM switches from nominal ODT (RTT,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst and subsequently switches back to nominal ODT (RTT,nom) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below. Functional Description The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic ODT is not supported during DLL disable mode so RTT(WR) must be disabled. The dynamic ODT function is described below: * Two RTT values are available--RTT,nom and RTT(WR) - The value for RTT,nom is preselected via MR1[9, 6, 2] - The value for RTT(WR) is preselected via MR2[10, 9] * During DRAM operation without READ or WRITE commands, the termination is controlled - Nominal termination strength RTT,nom is used - Termination on/off timing is controlled via the ODT ball and latencies ODTL on and ODTL off * When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled - A latency of ODTLcnw after the WRITE command: termination strength RTT,nom switches to RTT(WR) - A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT(WR) switches back to RTT,nom - On/off termination timing is controlled via the ODT ball and determined by ODTL on, ODTL off, ODTH4, and ODTH8 - During the tADC transition window, the value of RTT is undefined ODT is constrained during writes and when dynamic ODT is enabled (see Table 84 (page 191)). ODT timings listed in Table 83 (page 190) also apply to dynamic ODT mode. Table 84: Dynamic ODT Specific Parameters Definition for All DDR3 Speed Bins Units Symbol Description Begins at Defined to ODTLcnw Change from RTT,nom to RTT(WR) Write registration RTT switched from RTT,nom to RTT(WR) WL - 2 tCK ODTLcwn4 Change from RTT(WR) to RTT,nom (BC4) Write registration RTT switched from RTT(WR) to RTT,nom 4tCK + ODTL off tCK ODTLcwn8 Change from RTT(WR) to RTT,nom (BL8) Write registration RTT switched from RTT(WR) to RTT,nom 6tCK + ODTL off tCK tADC RTT change skew ODTLcnw completed RTT transition complete 0.5tCK 0.2tCK tCK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT Table 85: Mode Registers for RTT,nom MR1 (RTT,nom) M9 M6 M2 RTT,nom (RZQ) RTT,nom (Ohms) RTT,nom Mode Restriction 0 0 0 Off Off n/a 0 0 1 RZQ/4 60 Self refresh 0 1 0 RZQ/2 120 0 1 1 RZQ/6 40 1 0 0 RZQ/12 20 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a Note: Self refresh, write 1. RZQ = 240. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. Table 86: Mode Registers for RTT(WR) MR2 (RTT(WR)) M10 M9 RTT(WR) (RZQ) RTT(WR) (Ohms) 0 0 Dynamic ODT off: WRITE does not affect RTT,nom 0 1 RZQ/4 1 0 RZQ/2 120 1 1 Reserved Reserved 60 Table 87: Timing Diagrams for Dynamic ODT Figure and Page Title Figure 109 (page 193) Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 Figure 110 (page 193) Dynamic ODT: Without WRITE Command Figure 111 (page 194) Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 Figure 112 (page 195) Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 Figure 113 (page 195) Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 109: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 CK# CK Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid ODTH4 ODTL off ODTH4 ODT ODTL on ODTLcwn 4 tADC (MIN) tAON (MIN) RTT tADC (MIN) RTT,nom RTT(WR) tAON (MAX) tAOF (MIN) tADC (MAX) tADC (MAX) RTT,nom tAOF (MAX) ODTLcnw DQS, DQS# DQ DI n WL DI n+ 1 DI n+ 2 DI n+ 3 Transitioning Notes: Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command). 193 Figure 110: Dynamic ODT: Without WRITE Command Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Address ODTH4 ODTL on ODTL off ODT tAON (MAX) RTT tAON (MIN) tAOF (MIN) RTT,nom tAOF (MAX) DQS, DQS# DQ Transitioning Notes: Don't Care 1. AL = 0, CWL = 5. RTT,nom is enabled and RTT(WR) is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. CK# CK PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 111: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 CK# T0 T1 T2 NOP WRS8 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command ODTLcnw Address Valid ODTH8 ODTLoff ODTLon ODT tADC (MAX) tAOF (MIN) RTT(WR) RTT tAON (MIN) tAOF (MAX) ODTLcwn 8 DQS, DQS# WL DI b DQ 194 DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 Transitioning Notes: Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT,nom can be either enabled or disabled, ODT can be HIGH. RTT(WR) is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. 2Gb: x4, x8, x16 DDR3 SDRAM Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 CK# CK Command T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP ODTLcnw Address Valid ODTH4 ODTL off ODT ODTL on tADC (MAX) RTT(WR) RTT tAON (MIN) tADC (MIN) RTT,nom tAOF (MIN) tADC (MAX) tAOF (MAX) ODTLcwn 4 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 WL Transitioning Notes: Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 CK# CK Command T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP ODTLcnw Address Valid ODTL off ODTH4 ODT tAOF (MIN) tADC (MAX) ODTL on RTT tAON (MIN) RttRTT(WR) _wr tAOF (MAX) ODTLcwn 4 DQS, DQS# WL DI n DQ DI n+1 DI n+2 DI n+3 Transitioning Notes: PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Don't Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT(WR) is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. 195 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT,nom or RTT(WR) is enabled. Based on the power-down definition, these modes are: * * * * * Any bank active with CKE HIGH Refresh mode with CKE HIGH Idle mode with CKE HIGH Active power-down mode (regardless of MR0[12]) Precharge power-down mode if DLL is enabled during precharge power-down by MR0[12] ODT Latency and Posted ODT In synchronous ODT mode, RTT turns on ODTL on clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTL off clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 88 (page 197)). The ODT latency is tied to the WRITE latency (WL) by ODTL on = WL - 2 and ODTL off = WL - 2. Since write latency is made up of CAS WRITE latency (CWL) and ADDITIVE latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The device's internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus ODTL on = CWL + AL - 2 and ODTL off = CWL + AL - 2. Timing Parameters Synchronous ODT mode uses the following timing parameters: ODTL on, ODTL off, ODTH4, ODTH8, tAON, and tAOF. The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTL on. The minimum RTT turn-off time (tAOF [MIN]) is the point at which the device starts to turn off ODT resistance. Maximum RTT turn off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured from ODTL off. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 115 (page 198)). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 88: Synchronous ODT Parameters Symbol Description Begins at Definition for All DDR3 Speed Bins Units tAON CWL + AL - 2 tCK Defined to ODTL on ODT synchronous turn-on delay ODT registered HIGH RTT,on ODTL off ODT synchronous turn-off delay ODT registered HIGH RTT,off tAOF CWL +AL - 2 tCK ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODT registered HIGH or write registration with ODT HIGH ODT registered LOW 4tCK tCK ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTL on completion Completion of ODTL on RTT,on See Table 56 (page 78) ps tAOF ODT turn-off relative to ODTL off completion Completion of ODTL off RTT,off 0.5tCK 0.2tCK tCK Figure 114: Synchronous ODT 197 CK# CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CKE AL = 3 CWL - 2 ODT ODTH4 (MIN) ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 tAON (MIN) tAOF (MIN) RTT,nom RTT tAON (MAX) tAOF (MAX) Transitioning Note: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT,nom is enabled. Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. AL = 3 PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 115: Synchronous ODT (BC4) CK# CK T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 T7 NOP NOP NOP NOP WRS4 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE Command ODTH4 ODTH4 (MIN) ODTH4 ODT ODTLoff = WL - 2 ODTL off = WL - 2 ODTL on = WL - 2 ODTL on = WL - 2 tAON (MIN) tAOF (MIN) tAON (MAX) tAON (MAX) tAOF (MIN) RTT,nom RTT,nom RTT tAOF (MAX) tAOF (MAX) tAON (MIN) Transitioning Notes: Don't Care 198 1. 2. 3. 4. WL = 7. RTT,nom is enabled. RTT(WR) is disabled. ODT must be held HIGH for at least ODTH4 after assertion (T1). ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Off During READs Because the device cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either RTT,nom or RTT(WR) is enabled). RTT may not be enabled until the end of the postamble, as shown in the following example. Note: ODT may be disabled earlier and enabled later than shown Figure 116 (page 200). PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 116: ODT During READs T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 Command READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Address Valid CK# CK ODTL on = CWL + AL - 2 ODTL off = CWL + AL - 2 ODT RTT,nom RTT RL = AL + CL tAOF (MIN) RTT,nom tAOF (MAX) tAON (MAX) DQS, DQS# DQ DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 Transitioning Note: Don't Care 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT,nom is enabled. RTT(WR) is a "Don't Care." 200 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode Asynchronous ODT Mode Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either RTT,nom or RTT(WR) is enabled; however, the DLL is temporarily turned off in precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchronously when the DLL is synchronizing after being reset. See Power-Down Mode (page 179) for definition and guidance over power-down details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT by analog time. The timing parameters tAONPD and tAOFPD replace ODTL on/tAON and ODTL off/tAOF, respectively, when ODT operates asynchronously. The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turnon time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached High-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 201 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 117: Asynchronous ODT Timing with Fast ODT Transition CK# CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 CKE tIH tIS tIH tIS ODT tAOFPD (MIN) tAONPD (MIN) RTT,nom RTT tAONPD (MAX) tAOFPD (MAX) Transitioning Note: Don't Care 1. AL is ignored. Table 89: Asynchronous ODT Timing Parameters for All Speed Bins 202 Symbol Description Min Max Units tAONPD Asynchronous RTT turn-on delay (power-down with DLL off) 2 8.5 ns tAOFPD Asynchronous RTT turn-off delay (power-down with DLL off) 2 8.5 ns 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM's ODT may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW, and it ends when CKE is first registered LOW. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, power-down entry will end tRFC after the REFRESH command rather than when CKE is first registered LOW. Power-down entry will then become the greater of tANPD and tRFC - REFRESH command to CKE registered LOW. ODT assertion during power-down entry results in an RTT change as early as the lesser of tAONPD (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT deassertion during power-down entry may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 90 (page 204) summarizes these parameters. If the AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTL on and ODTL off are derived from the WL and WL is equal to CWL + AL. Figure 118 (page 204) shows three different cases: * ODT_A: Synchronous behavior before tANPD * ODT_B: ODT state changes during the transition period with tAONPD (MIN) less than ODTL on x tCK + tAON (MIN) and tAONPD (MAX) greater than ODTL on x tCK + tAON (MAX) * ODT_C: ODT state changes after the transition period with asynchronous behavior PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 203 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Table 90: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Min Power-down entry transition period (power-down entry) Max Greater of: tANPD or tRFC tANPD Power-down exit transition period (power-down exit) - refresh to CKE LOW + tXPDLL ODT to RTT turn-on delay (ODTL on = WL - 2) Lesser of: tAONPD (MIN) (1ns) or ODTL on x tCK + tAON (MIN) Greater of: tAONPD (MAX) (9ns) or ODTL on x tCK + tAON (MAX) ODT to RTT turn-off delay (ODTL off = WL - 2) Lesser of: tAOFPD (MIN) (1ns) or ODTL off x tCK + tAOF (MIN) Greater of: tAOFPD (MAX) (9ns) or ODTL off x tCK + tAOF (MAX) tANPD WL - 1 (greater of ODTL off + 1 or ODTL on + 1) Figure 118: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 Ta1 Ta2 Ta3 NOP REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE 204 Command tRFC (MIN) tANPD PDE transition period DRAM RTT A synchronous tAOF (MIN) RTT,nom ODTL off tAOF (MAX) ODT B asynchronous or synchronous ODTL off + tAOFPD (MIN) tAOFPD (MAX) tAOFPD (MIN) DRAM RTT B asynchronous or synchronous RTT,nom ODTL off + tAOFPD (MAX) ODT C asynchronous tAOFPD (MIN) DRAM RTT C asynchronous RTT,nom tAOFPD (MAX) Indicates A Break In Time Scale Note: 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. Transitioning Don't Care 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. ODT A synchronous 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit) Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM's ODT may exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins tANPD prior to CKE first being registered HIGH, and it ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTL off + 1tCK or ODTL on + 1tCK. The transition period is tANPD plus tXPDLL. ODT assertion during power-down exit results in an RTT change as early as the lesser of (MIN) and ODTL on x tCK + tAON (MIN) or as late as the greater of tAONPD (MAX) and ODTL on x tCK + tAON (MAX). ODT deassertion during power-down exit may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTL off x tCK + tAOF (MIN) or as late as the greater of tAOFPD (MAX) and ODTL off x tCK + tAOF (MAX). Table 90 (page 204) summarizes these parameters. tAONPD If the AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTL on and ODTL off are derived from the WL, and WL is equal to CWL + AL. Figure 119 (page 206) shows three different cases: * ODT C: asynchronous behavior before tANPD * ODT B: ODT state changes during the transition period, with tAOFPD (MIN) less than ODTL off x tCK + tAOF (MIN) and ODTL off x tCK + tAOF (MAX) greater than tAOFPD (MAX) * ODT A: ODT state changes after the transition period with synchronous response PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 205 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 119: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 NOP NOP NOP NOP NOP Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE COMMAND tXPDLL tANPD PDX transition period ODT A asynchronous DRAM RTT A asynchronous tAOFPD (MIN) RTT,nom ODTL off + tAOF (MIN) tAOFPD (MAX) ODT B asynchronous or synchronous RTT B asynchronous or synchronous tAOFPD (MAX) tAOFPD (MIN) RTT,nom ODTL off + tAOF (MAX) ODTL off ODT C synchronous tAOF (MAX) tAOF (MIN) DRAM RTT C synchronous RTT,nom 206 Indicates A Break in Time Scale Don't Care 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. Note: Transitioning 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods will overlap. When overlap occurs, the response of the DRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period even if the entry period ends later than the exit period. If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit and power-down entry transition periods overlap. When this overlap occurs, the response of the DRAM's RTT to a change in the ODT state may be synchronous or asynchronous from the start of power-down exit transition period to the end of the powerdown entry transition period. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 207 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 120: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping CK# CK Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE PDE transition period tANPD tRFC (MIN) PDX transition period tXPDLL tANPD Short CKE low transition period (R TT change asynchronous or synchronous) 208 Indicates a break in time scale Note: Transitioning Don't Care 1. AL = 0, WL = 5, tANPD = 4. 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN Figure 121: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping CK# CK Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE tANPD tXPDLL tANPD Short CKE HIGH transition period (RTT change asynchronous or synchonous) Indicates a break in time scale Note: Transitioning Don't Care 1. AL = 0, WL = 5, tANPD = 4. 209 2Gb: x4, x8, x16 DDR3 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3 SDRAM 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. K 04/10 EN 210 Micron Technology, Inc. reserves the right to change products or specifications without notice. (c) 2006 Micron Technology, Inc. All rights reserved.