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Old Company Name in Catalogs and Other Documents
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April 1st, 2010
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Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS164
8-Bit Parallel-Out Serial-in Shift Register REJ03D0448–0200
Rev.2.00
Feb.18.2005
This 8-bit shift register features gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit
complete control over incoming d a ta as a low at either (or both) input(s) inhibits entry of the new data and resets the
first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will them
determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but
only information meeting the setup requirements will be entered. Clocking occurs on the low-to-high-level transition of
the clock input.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS164P DILP-14 pin PRDP0014AB-B
(DP-14AV) P —
HD74LS164FPEL SOP-14 pin (JEITA) PRSP0014DF-B
(FP-14DAV) FP EL (2,000 pcs/reel)
HD74LS164RPEL SOP-14 pin (JEDEC) PRSP0014DE-A
(FP-14DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
Pin Arrangement
(Top view)
GND
1
2
3
4
5
6
7
14
8
9
10
11
12
13
A
B
QA
QB
CK
QC
QDQD
VCC
QH
A
QG
QG
QF
QF
Clear
QH
QE
QE
QA
QB
B
QC
Clock
CLR
Outputs
Outputs
Serial
Inputs
HD74LS164
Rev.2.00, Feb.18.2005, page 2 of 8
Function Table
Inputs Outputs
Clear Clock A B QA Q
B……QH
L X X X L L L
H L X X QA0 Q
B0 Q
H0
H ↑ H H H QAn Q
Gn
H ↑ L X L QAn Q
Gn
H ↑ X L L QAn Q
Gn
Notes: 1. H; high level, L; low level, X; irrelevant
2. ↑; transition from low to high level
3. QA0, QB0, QH0; the level of QA, QB, or QH, respectively, before the indic ated steady-state input conditions
were established.
4. QAn, QGn; the level of QA or QG before the most-recent ↑ transition of the clock; indicates a one-bit shift.
Block Diagram
Clear
Clock
Serial
Inputs A
B
Output
Q
A
Output
Q
B
Output
Q
C
Output
Q
D
Output
QE
Output
Q
F
Output
Q
G
Output
Q
H
Clear
R
S
Q
A
Q
A
CK
Clear
R
S
Q
B
Q
B
CK
Clear
R
S
Q
C
Q
C
CK
Clear
R
S
Q
D
Q
D
CK
Clear
R
S
Q
E
Q
E
CK
Clear
R
S
Q
F
Q
F
CK
Clear
R
S
Q
G
Q
G
CK
Clear
R
S
Q
H
Q
H
CK
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Clock frequency ƒclock 0 — 25 MHz
Clock pulse width tw (CK) 20 — — ns
Clear pulse width tw (CLR) 20 — — ns
Data setup time tsu 15 — — ns
Data hold time th 5 — — ns
HD74LS164
Rev.2.00, Feb.18.2005, page 3 of 8
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
Input current II — — 0.1 mA VCC = 5.25 V, VI = 7 V
Short-circuit output
current IOS –20 — –100 mA VCC = 5.25 V
Supply current** ICC — 16 27 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with outputs open, serial inputs grounded, the clock input at 2.4 V, and a momentary
grounded, then 4.5 V applied to clear.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
Maximum clock frequency ƒmax 25 36 — MHz
tPHL Clear Q — 24 36 ns
tPLH Clock Q — 17 27 ns
Propagation delay time tPHL Clock Q — 21 32 ns
CL = 15 pF,
RL = 2 kΩ
HD74LS164
Rev.2.00, Feb.18.2005, page 4 of 8
Typical Clear, Shift, and Clear Sequences
Clock
Clear
Clear Clear
Outputs
Serial
Inputs B
A
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
HD74LS164
Rev.2.00, Feb.18.2005, page 5 of 8
Testing Method
Test Circuit
4.5V
QA
Load circuit 1
Output
VCC
RL
CL
Input
P.G.
Zout = 50Ω
Input
P.G.
Zout = 50Ω
See Testing Table
A
B
CK
CLR
QC
QD
QBSame as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
QHSame as Load Circuit 1.
Output
GND
Notes: 1. CL includes prob e and jig capacitance.
2. All diodes are 1S2074(H).
Testing Table
Inputs Outputs
Item From
input to
output CLR CK A B QA Q
B Q
C Q
D Q
E Q
F Q
G Q
H
ƒmax 4.5V IN IN 4.5V OUT OUT OUT OUT OUT OUT OUT OUT
Clear→Q IN IN IN 4.5V OUT OUT OUT OUT OUT OUT OUT OUT tPLH
tPHL CK→Q 4.5V IN IN 4.5V OUT OUT OUT OUT OUT OUT OUT OUT
HD74LS164
Rev.2.00, Feb.18.2005, page 6 of 8
Waveform
Clock
Clear 1.3V 1.3V
1.3V
1.3V
1.3V 1.3V 1.3V
1.3V 1.3V 1.3V
1.3V 1.3V
t
THL
t
w (CLR)
≥ 20ns
t
w (CK)
≥ 20ns
t
THL
t
TLH
t
THL
t
su
t
h
t
su
t
h
t
TLH
t
TLH
QA
A
t
PHL
t
PHL
t
PLH
VOH
VOL
0V
3V
0V
3V
0V
3V
10%10%
10%
10% 10%
10%
90% 90%
90% 90%
90% 90%
Notes: 1. Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, (Clock, Clear), PRR = 500 kHz (A or B)
2. QA output is illustrated. Relationship of serial input A and B data to other Q outputs is
illustrated in the timing chart.
HD74LS164
Rev.2.00, Feb.18.2005, page 7 of 8
Package Dimensions
( Ni/Pd/Au plating )
7.62
DP-14AV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0014AB-BP-DIP14-6.3x19.2-2.54
20.32
7.4
0.40 0.48
2.39
2.54
0.97g
814
7
1
p
3
1
1b
D
E
e
Z
b
LA
A
c
e
θ
1.42
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-14DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.23g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP14-5.5x10.06-1.27 PRSP0014DF-B
Index mark
E
1
*2
*1
7
14 8
F
*3p
Mx
y
D
E
H
Zb
A
p
Terminal cross section
( Ni/Pd/Au plating )
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74LS164
Rev.2.00, Feb.18.2005, page 8 of 8
14 8
7
F
*1
*2
*3p
Mx
y
1
E
Index mark
b
A
Z
H
E
D
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
1
1
Detail F
L
L
A
θ
PRSP0014DE-AP-SOP14-3.95x8.65-1.27
A
L
e
e
c
b
D
E
A
b
c
θ
x
y
H
Z
L
2
1
1
E
1
MASS[Typ.]
0.13g
8.65
1.08
0.25
0
°
8
°
6.10
0.15 0.20 0.25
0.46
0.10 0.14 0.25
3.95
0.40 0.60 1.27
1.75
Reference
Symbol
Dimension in Millimeters
Min Nom Max
Previous CodeJEITA Package Code RENESAS Code FP-14DNV
9.05
1
A
p
0.34 0.40
6.205.80
1.27
0.15
0.635
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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