MC14040B 12-Bit Binary Counter The MC14040B 12-stage binary counter is constructed with MOS P-Channel and N-Channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 12 stages of ripple-carry binary counter. The device advances the count on the negative-going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency-driving circuits. http://onsemi.com MARKING DIAGRAMS Features * * * * * * * Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Common Reset Line Pin-for-Pin Replacement for CD4040B These Devices are Pb-Free and are RoHS Compliant PDIP-16 P SUFFIX CASE 648 16 MC14040BCP AWLYYWWG 1 16 SOIC-16 D SUFFIX CASE 751B 14040BG AWLYWW 1 16 MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter Value Unit -0.5 to +18.0 V -0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C Symbol VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) TSSOP-16 DT SUFFIX CASE 948F 1 14 040B ALYW G G 16 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C SOEIAJ-16 F SUFFIX CASE 966 MC14040B ALYWG 1 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. (c) Semiconductor Components Industries, LLC, 2011 June, 2011 - Rev. 9 1 Publication Order Number: MC14040B/D MC14040B PIN ASSIGNMENT Q12 1 16 VDD Q6 2 15 Q11 Q5 3 14 Q10 Q7 4 13 Q8 Q4 5 12 Q9 Q3 6 11 R Q2 7 10 C VSS 8 9 Q1 TRUTH TABLE Clock Reset Output State X 0 0 1 No Change Advance to next state All Outputs are low X = Don't Care LOGIC DIAGRAM Q1 Q2 9 CLOCK C 10 C R Q3 6 7 Q C Q C R Q C Q C R Q10 14 Q C Q C R Q11 15 Q C Q C R Q12 1 Q C Q C Q R RESET 11 Q4 = PIN 5 Q5 = PIN 3 Q6 = PIN 2 Q7 = PIN 4 Q8 = PIN 13 Q9 = PIN 12 VDD = PIN 16 VSS = PIN 8 ORDERING INFORMATION Package Shipping MC14040BCPG PDIP-16 (Pb-Free) 500 Units / Tape & Ammunition Box MC14040BDG SOIC-16 (Pb-Free) 48 Units / Rail MC14040BDR2G SOIC-16 (Pb-Free) 2500 Units / Tape & Reel MC14040BDTR2G TSSOP-16* 2500 Units / Tape & Reel MC14040BFELG SOEIAJ-16 (Pb-Free) 2000 Units / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC14040B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIII IIIIIIIII IIIII IIII IIIIIIIIIIIII IIIIII IIIIIIIIIIIIII IIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIII IIIIIII IIIIII IIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit "0" Level VOL 5.0 10 15 - - - 0.05 0.05 0.05 - - - 0 0 0 0.05 0.05 0.05 - - - 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 - - - 4.95 9.95 14.95 - - - Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 - - - 1.5 3.0 4.0 - - - 2.25 4.50 6.75 1.5 3.0 4.0 - - - 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 - - - - - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 - - - - - 1.7 - 0.36 - 0.9 - 2.4 - - - - IOL 5.0 10 15 0.64 1.6 4.2 - - - 0.51 1.3 3.4 0.88 2.25 8.8 - - - 0.36 0.9 2.4 - - - mAdc Input Current Iin 15 - 0.1 - 0.00001 0.1 - 1.0 mAdc Input Capacitance (Vin = 0) Cin - - - - 5.0 7.5 - - pF Quiescent Current (Per Package) IDD 5.0 10 15 - - - 5.0 10 20 - - - 0.005 0.010 0.015 5.0 10 20 - - - 150 300 600 mAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IOH Vdc Vdc mAdc IT = (0.42 mA/kHz) f + IDD IT = (0.85 mA/kHz) f + IDD IT = (1.43 mA/kHz) f + IDD 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 mAdc MC14040B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time TTLH, TTHL = (1.5 ns/pF) CL + 25 ns TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q1 tPHL, tPLH = (1.7 ns/pF) CL + 315 ns tPHL, tPLH = (0.66 ns/pF) CL + 137 ns tPHL, tPLH = (0.5 ns/pF) CL + 95 ns tPLH, tPHL VDD Vdc Min Typ (Note 6) Max 5.0 10 15 - - - 100 50 40 200 100 80 5.0 10 15 - - - 260 115 80 520 230 160 5.0 10 15 - - - 1625 720 500 3250 1440 1000 Unit ns ns ns Clock to Q12 tPHL, tPLH = (1.7 ns/pF) CL + 2415 ns tPHL, tPLH = (0.66 ns/pF) CL + 867 ns tPHL, tPLH = (0.5 ns/pF) CL + 475 ns Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 485 ns tPHL = (0.86 ns/pF) CL + 182 ns tPHL = (0.5 ns/pF) CL + 145 ns tPHL Clock Pulse Width ns 5.0 10 15 - - - 370 155 115 740 310 230 tWH 5.0 10 15 385 150 115 140 55 38 - - - ns fcl 5.0 10 15 - - - 2.1 7.0 10.0 1.5 3.5 4.5 MHz tTLH, tTHL 5.0 10 15 Reset Pulse Width tWH 5.0 10 15 960 360 270 320 120 80 - - - ns Reset Removal Time trem 5.0 10 15 130 50 30 65 25 15 - - - ns Clock Pulse Frequency Clock Rise and Fall Time ns No Limit 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD VDD 500 mF 0.01 mF CERAMIC ID PULSE GENERATOR C Q1 Q2 Q R n C Q1 Q2 Q R n CL CL VSS CL CL CL VSS 20 ns CLOCK PULSE GENERATOR 90% 50% 10% CL CLOCK 20 ns 20 ns 20 ns tPLH VDD 90% 50% 10% tWH tPHL 50% DUTY CYCLE 90% 50% 10% tTLH Figure 1. Power Dissipation Test Circuit and Waveform Figure 2. Switching Time Test Circuit and Waveforms Q VSS http://onsemi.com 4 tTHL MC14040B 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CLOCK RESET Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Figure 3. Timing Diagram APPLICATIONS INFORMATION TIME-BASE GENERATOR outputs Q5, Q10, Q11, and Q12 division by 3600 is accomplished. The MC14012B decodes the counter outputs, produces a single output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute. A 60 Hz sinewave obtained through a 1.0 Megohm resistor connected directly to a standard 120 Vac power line is applied to the clock input of the MC14040B. By selecting VCC VCC 1/6 of HC14A 1.0M MC14040B Clock 12 20pF 120Vac 60Hz 13 Q5 Q10 10 Q11 9 NOTE: Q12 Ground MUST be isolated by a transformer or opto-isolator for safety reasons. Figure 4. Time-Base Generator http://onsemi.com 5 1/2 14012B 8 1 2 4 5 1/2 14012B 6 1.0 Pulse/Minute Output MC14040B PACKAGE DIMENSIONS PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 6 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14040B PACKAGE DIMENSIONS SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT* 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC14040B PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U T U M S V S K S EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N DIM A B C D F G H J J1 K K1 L M F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC14040B PACKAGE DIMENSIONS SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE A 16 LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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