Page 1 of 7
Document No. 70-0029-02 www.psemi.com ©2005 Peregrine Semic onduct or Corp. All rights reserved.
Parameter Conditions Minimum Typical Maximum Units
Operation Frequency1 DC 3000 MHz
Insertion Loss 1000 MHz
2000 MHz 0.35
0.55 0.45
0.65 dB
dB
Isolation – RFC to RF1/RF2 1000 MHz
2000 MHz 38
28 39
30 dB
dB
Isolation – RF1 to RF2 1000 MHz
2000 MHz 33.5
26.5 35
28 dB
dB
Return Loss 1000 MHz
2000 MHz 23.5
14.5 25.5
15.4 dB
dB
‘ON’ Switching Time CTRL to 0.1 dB final value, 2 GHz 200 ns
‘OFF’ Switching Time CTRL to 25 dB isolation, 2 GHz 90 ns
Video Feedthrough2 15 mVpp
Input 1 dB Compression 2000 MHz 30 32 dBm
Input IP3 2000 MHz, 17 dBm 50 dBm
RFC
RF1 RF2
CMOS
Control
Driver
CTRL
The PE4230 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from DC through 3000 MHz. This
single-supply reflective switch integrates on-board CMOS
control logic driven by a simple, single-pin CMOS or TTL
compatible control input. Using a nominal +3-volt power supply,
a typical input 1 dB compression point of +32 dBm can be
achieved. The PE4230 also exhibits input-output isolation of
better than 39 dB at 1000 MHz and is offered in a small 8-lead
MSOP package.
The PE4230 SPDT High Power UltraCMOS™ RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Product Specification
SPDT High Power UltraCMOS™
RF Switch
Product Description
Figure 1. Functional Diagram
PE4230
Features
• Single 3-volt power supply
• Low insertion loss: 0.35 dB at
1000 MHz, 0.55 dB at 2000 MHz
• High isolation of 39 dB at 1000 MHz,
30 dB at 2000 MHz
• Typical input 1 dB compression point
of +32 dBm
• Single-pin CMOS or TTL logic control
• Low cost
Notes: 1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to
High or High to Low in a 50 test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 50 )
Figure 2. Package Type
8-lead MSOP
Not for new design
Product Specific ation
PE4230
Page 2 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 UltraCM O S™ RFIC Soluti o ns
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 VDC.
Table 2. Pin Descriptions
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMO S™
devices are immune to latch-up.
Table 3. DC Electrical Specifications
Figure 3. Pin Configuration (Top View)
4230
1
2
3
4
8
7
6
5
V
DD
CTRL
GND
RFC
RF1
GND
GND
RF2
Pin
No. Pin
Name Description
1 VDD Nominal +3V supply connect i on.
2 CTRL CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
3 GND Ground connection. Traces should be
physically short and connected to ground
plane for best performanc e.
4 RFC Common RF port for switch. 1
5 RF2 RF2 port.1
6 GND Ground Connection. Traces should be
physically short and connected to ground
plane for best performanc e.
7 GND Ground Connection. Traces should be
physically short and connected to ground
plane for best performanc e.
8 RF1 RF1 port.1
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input
except for the CTRL input -0.3 VDD+
0.3 V
VCTRL Voltage on CTRL input 5.0 V
TST Storage temperature range -65 150 °C
TOP Operating temperat ure
range -40 85 °C
PIN Input power (50) 35 dBm
VESD ESD voltage (Human Body
Model) 250 V
Parameter Min Typ Max Units
VDD Power Supply Voltage 2.7 3.0 3.3 V
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V ) 29 35 µA
Control Voltage Hi gh 0.7xVDD V
Control Voltage Low 0.3xV DD V
Control Voltage Signal Path
CTRL = CMOS or TTL High RFC to RF 1
CTRL = CMOS or TTL Low RFC to RF2
Table 5. Control Logic Truth Table
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic driv-
ers, the control logic input has been designed to
handle a 5-volt logic HIGH signal. (A minimal cur-
rent will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in t he DC Electrical Specif ications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Not for new design
Product Specific ation
PE4230
Page 3 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 www.psemi.com
Typical Performance Data @ 25 °C (Unless Otherwise Noted)
Figure 4. Insertion Loss – RFC to RF1 Figure 5. Input 1dB Compression Point
Figure 6. Insertion Loss – RFC to RF2 Figure 7. Isolation – RFC to RF1
-2
-1.6
-1.2
-0.8
-0.4
0
0 500 1000 1500 2000 2500 3000
Insertion Loss (dB)
Frequency (MHz)
-40 8C
85 8C
25 8C
0
10
20
30
40
500 1000 1500 2000 2500 3000
1dB Compression Point (dBm)
Frequency (MHz)
-2
-1.6
-1.2
-0.8
-0.4
0
0 500 1000 1500 2000 2500 3000
Insertion Loss (dB )
Frequency (MHz)
-40 8C
85 8C
25 8C
-100
-80
-60
-40
-20
0
0 500 1000 1500 2000 2500 3000
Isolation (dB)
Frequency (MHz)
T = -40 °C to 85 °C
T = -40 °C to 85 °C
Not for new design
Product Specific ation
PE4230
Page 4 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 UltraCM O S™ RFIC Soluti o ns
Typical Performance Data @ 25°C
Figure 8. Isolation – RFC to RF2 Figure 9. Isolation – RF1 to RF2, RF2 to RF1
Figure 10. Return Loss – RFC Figure 11. Return Loss – RF1, RF2
-100
-80
-60
-40
-20
0
0 500 1000 1500 2000 2500
Isolation (dB)
Frequency (MHz)
-100
-80
-60
-40
-20
0
0 500 1000 1500 2000 2500 3000
Isolation (dB)
Frequency (MHz)
RF1
RF2
-40
-30
-20
-10
0
0 500 1000 1500 2000 2500 3000
Return Loss (dB)
Frequency (MHz)
-40
-30
-20
-10
0
0 500 1000 1500 2000 2500
Return Loss (dB)
Frequency (MHz)
RF1
RF2
Not for new design
Product Specific ation
PE4230
Page 5 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 www.psemi.com
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4230 SPDT switch. The RF common port is
connected through a 50 transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50 transmission lines to the
top two SMA connectors on the right side of the
board, J3 and J4. A through transmission line
connects SMA connectors J6 and J8. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.030”, trace
gaps of 0.007”, dielectric thickness of 0.028”,
metal thickness of 0.0014” and r of 4.4.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J2-3) is connected
to the device CNTL input. The fourth pin to the
right (J2-7) is connected to the device VDD input.
A decoupling capacitor (100 pF) is provided on
both CNTL and VDD traces. It is the responsibility
of the customer to determine proper supply
decoupling for their design application. Removing
these components from the evaluation board has
not been shown to degrade RF performance.
Figure 12. Evaluation Board Layouts
Figure 13. Evaluation Board Schematic
Peregrine Specification 102/0035
Peregrine Specification 101/0037
Not for new design
Product Specific ation
PE4230
Page 6 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 UltraCM O S™ RFIC Soluti o ns
8-lead MSOP
Table 6. Ordering Information
Figure 14. Package Drawing
FRONT VIEW
2.95±0.10
0.08 A B C
0.33 +0.07
-0.08
0.10 A0.10±0.05
3.00±0.10
0.86±0.08
1.10 MAX
- C -
- A -
1
0.65BSC
0.51±0.13
2.45±0.10
0.51±0.13
2X
8
3.00±0.10
.25 A B C
234
- B -
.525BSC
TOP VIEW
567
4.90±0.15
3.00±0.10
SIDE VIEW
2.95±0.10
R 0.90 MIN
0.95 BSC
0.55 ±0.15
R 0.90 MIN
0
o
6
o
12
o
REF
12
o
REF
0.25
GAGE
PLANE
Order Code Part Marking Description Package Shipping Method
4230-21 4230 PE4230-08MSOP -50A 8-lead MSOP 50 units / Tube
4230-22 4230 PE4230-08MSOP-2000C 8-lead MSOP 2000 units / T&R
4230-00 PE4230-EK PE4230-08MSOP-EK Evaluation Kit 1 / Box
4230-51 4230 PE 4230G-08MSO P -50A Green 8-lead MSOP 50 units / Tube
4230-52 4230 PE4230G-08MSOP-2000C Green 8-lead MSOP 2000 units / T&R
Not for new design
Product Specific ation
PE4230
Page 7 of 7
©2005 Peregrine Semic onduct or Corp. All rights reserved. Document No. 70-0029-02 www.psemi.com
Sales Offices
The Americas
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
Fax 858-731-9499
North Asia Pacifi c
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor Europe
Commercial Products:
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
Space and Defense Products:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS is a trademark of Peregrine Semiconductor
Corp.
South Asia Pacific
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Not for new design
