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IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2009
IDT74FCT16373AT/CT
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT
TRANSPARENT LATCH
DESCRIPTION:
The FCT16373T 16-bit transparent D-type latch is built using advanced dual
metal CMOS technology. These high-speed, low-power latches are ideal for
temporary storage of data. They can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 8-bit latches, or one 16-bit latch.
Flow-through organization of signal pins simplifies layout. All inputs are designed
with hysteresis for improved noise margin.
The FCT16373T is ideally suited for driving high-capacitance loads and low-
impedance backplanes. The output buffers are designed with power off disable
capability to allow "live insertion" of boards when used as backplane drivers.
2
O
1
2
OE
2
LE
2
D
1
TO SEVEN OTHER CHANNELS
C
D
1
OE
1
LE
1
O
1
1
D
1
TO SEVEN OTHER CHANNELS
C
D
FEATURES:
• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤≤
≤≤
≤1µA (max.)
•VCC = 5V ±10%
• High drive outputs (–32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-5454/6
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
1O1
GND
1O3
VCC
1OE
GND
2O2
GND
VCC
GND
1O2
1O4
1O5
1O6
1O7
1O8
2O1
2O3
2O4
2O5
2O7
2O8
2O6
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
VCC
2D5
2D7
2D8
2D6
2LE
GND
GND
GND
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to 7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
COUT Output Capacitance VOUT = 0V 3.5 8 pF
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Pin Names Description
xDx Data Inputs
xLE Latch Enable Input (Active HIGH)
xOE Output Enable Input (Active LOW)
xOx 3-State Outputs
PIN DESCRIPTION
Inputs Outputs
xDx xLE xOE xOx
HHLH
LHLL
XXHZ
FUNCTION TABLE(1)
NOTE:
1. H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High-impedance
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IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
IOOutput Drive Current VCC = Max., VO = 2.5V(3) –50 — 180 mA
VOH Output HIGH Voltage VCC = Min. IOH = –3mA 2 .5 3.5 — V
VIN = VIH or VIL IOH = –15mA 2 . 4 3. 5 — V
IOH = –32mA(4) 23—V
VOL Output LOW Voltage VCC = Min. IOL = 64mA — 0.2 0.55 V
VIN = VIH or VIL
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN = or VO ≤ 4.5V — — ±1 μA
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current (Input pins)(5) VCC = Max. VI = VCC ——±1µA
Input HIGH Current (I/O pins)(5) ——±1
IIL Input LOW Current (Input pins)(5) VI = GND — — ±1
Input LOW Current (I/O pins)(5) ——±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ± 1 µA
IOZL (3-State Output pins)(5) VO = 0.5V — — ± 1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA
VHInput Hysteresis — — 100 — m V
ICCL Quiescent Power Supply Current VCC = Max — 5 500 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
OUTPUT DRIVE CHARACTERISTICS
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ΔICC Quiescent Power Supply Current VCC = Ma x. — 0.5 1.5 m A
TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 60 100 µA/
Outputs Open VIN = GND M H z
xOE = GND
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 0.6 1.5 mA
Outputs Open VIN = GND
fi = 10MHz
50% Duty Cycle VIN = 3.4V — 0.9 2.3
xOE = GND VIN = GND
xLE = VCC
One Bit Toggling
VCC = Max. VIN = VCC — 2.4 4.5(5)
Outputs Open VIN = GND
fi = 2.5MHz
50% Duty Cycle VIN = 3.4V — 6.4 16.5(5)
xOE = GND VIN = GND
xLE = VCC
Sixteen Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = I QUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
POWER SUPPLY CHARACTERISTICS
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IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE
FCT16373AT FCT16373CT
Symbol Parameter Condition(2) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 5.2 1.5 3.6 ns
tPHL xDx to xOx RL = 500Ω
tPLH Propagation Delay 2 8.5 2 3.7 ns
tPHL xLE to xOx
tPZH Output Enable Time 1.5 6.5 1.5 4.4 ns
tPZL
tPHZ Output Disable Time 1.5 5.5 1.5 3.9 ns
tPLZ
tSU Set-up Time HIGH or LOW, xDx to xLE 2 — 2 — ns
tHHold Time HIGH or LOW, xDx to xLE 1.5 — 1.5 — ns
tWxLE Pulse Width HIGH 5 — 5 — ns
tSK(o) Output Skew(3) — 0.5 — 0.5 ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF 500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
V
OH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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IDT74FCT16373AT/CT
FAST CMOS 16-BIT TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
Temp. Range
XXXX
Device Type
XX
Package
X
Process
PVG
PAG
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
16-Bit Transparent Latch
74 40C to +85C
16 Double-Density, 5 Volt, High Drive
Blank Industrial (-40°C to +85°C)
FCT XXX
Family
373AT
373CT
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 logichelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
Datasheet Document History
09/10/09 Pg.7 Updated the ordering information by removing the "IDT" notation and non RoHS part.
