MTC-20278PQ-I - ON Semiconductor L.L.C.

MTC-20278/9 150200 [1]

MTC-20278/9 ILT

Key Features

▼Quad ISDN LT ‘U’ interface

functions in a single monolithic

integrated circuit

▼Pin compatible 2B1Q and 4B3T

line code versions

* MTC-20278 ILTQ for 2B1Q

* MTC-20279 ILTT for 4B3T

▼Full compliance with the

applicable ETSI, FTZ and ITU

requirements

▼DECT Synchronization Support

(2BTQ)

▼Digital interface bus using

industry-standard GCI

▼Minimal external components

▼3.3V operating voltage

▼80 pin Plastic Quad Flat Pack

package

Key Applications

▼ISDN Exchange Line Cards

▼Remote Access Multiplex

Systems

▼FTTx Systems

General Description

The MTC-20278/9 chip contains all

the functions necessary to make 4 ‘U’

interfaces in an ISDN Line Termination

card. It comprises 4, fully integrated

echo-canceling ‘U’ interfaces, plus the

necessary support and test functions.

The general block diagram is shown

in Figure 1. By integrating 4 complete

U Interfaces in a single high density

package, the MTC-20278/9 makes it

possible to integrate more lines on one

card, this reducing the cost per line.

Two versions of the device are available

- the MTC-20278 offering the 2B1Q line

code, and the MTC-20279 which has

4B3T line coding. Both devices are pin

compatible, and are fully compliant with

the relevant parts of ETSI, FTZ and ITU

requirements for ISDN connection.

The MTC-20278/9 device offers a user

transport rate of 144kbit/s full duplex

(2B + D) per channel, as well as fully

automatic control of activate/deactivate

protocols, and full support of the main-

tenance channel. Digital I/O for Power-

feed Control, and DECT Synchronization

(MTC-20278 only) are provided for 4

identical channels.

Quad ISDN U-Interface

ISDN Standard Products

Data Sheet

Rev. 2.0 - February 2000

TSP NRESET

Channel Support

Channel ‘U’

Interface

Power

Feed Control

JTAG

Test Interface

TRST

TCK

TMS

TDI

TDO

GCI Port

DOUT

DIN

DCLK

DFR

POS

AVDD

AVSS

AREF

LOUT2

LOUT1

LIN2

LIN1

RD2

RD1

FD2

FD1

RD3

4 Identical

Channels

VDD

VSS

Fig.1: General Block Diagram

Ordering Information

Part number Package Temp.

MTC-20278PQ-I 80PQFP -40 to + 85°C

MTC-20278PQ-C 80PQFP 0 to + 70°C

MTC-20279PQ-I 80PQFP -40 to + 85°C

MTC-20279PQ-C 80PQFP 0 to + 70°C

The digital interface on the ‘exchange’

side uses the industry-standard GCI

interface in 2 Mbit burst mode. This

mode allows for 8 channels to be multi-

plexed onto the same interface. The

MTC-20278/9 can be set to respond to

either the first 4 or the last 4 timeslots in

the GCI frame. This allows two devices,

totalling 8 ISDN lines, to be multiplexed

onto the same GCI interface.

The MTC-20278/9 takes all timing

information from the GCI clocks, and

so does not require a separate clock

oscillator.

MTC-20278/9 150200 [2]

MTC-20278/9 ILTQ/ILTT

12 Ω

1:2

LOUT2

LOUT1

ILTQ 135 ΩVI

Fig.2: Test Circuit for Single Pulse VI

Relevant Standards

- ETSI TS 102 080, 1998

- ETS 300 012

- ETS 300 297

- CCITT / ITU Recommendation

G.961

- ANSI T1.601, BA ISDN

specifications 1992

Functional Characteristics

The U-Interface

NOTE: Some of the specifications in

this section refer to the U0 Inter-

face and not to the line ports

(LOUT1, LOUT2, LIN1, LIN2).

The characteristics at the line

port are affected by the design

of the transformer and the other

external components.

MTC-20278

Physical Characteristics

The quaternary symbol stream on the

U-interface complies to the following

physical characteristics:

1) Symbol Rate

The symbol rate is 80 kbaud ±

1 ppm and applies to synchronous

symbol transmission. The symbol

rate is controlled by the external

clock.

2) Input Jitter

The ILTQ tolerates a sinusoidal input

jitter of the quaternary symbols as

shown in Figure 5.

3) Output Jitter

The peak-to–peak jitter produced

by the ILTQ doesn’t exceed 0.02 UI

when measured via a high pass filter

with a cut-off frequency of 30Hz.

Without this filter, the same measure-

ment doesn’t read more than 0.1 UI.

To obtain this performance, the jitter

on the GCI input clock should not

exceed 15ns peak-to-peak

4) Transmit Signal Amplitude

The absolute peak value VImax of

a single pulse VI at U0 interface

terminated with a 135Ωresistance

is 2.5V ± 5%. See Figure 2 and 8.

5) Stability

The transmit signal amplitude mea-

sured over a periode of one minute

doesn’t vary by more than 1%

beginning 5ms after the ILTQ is

switched into power-up state.

6) Transmit Spectrum

The spectrum of the quaternary

transmit signal at U0 interface

doesn’t exceed the limits given

in Figure 7.

7) Pulse Shape

A single pulse measured across a

135Ωresistance at U0 interface

complies to the spectral require-

ments presented in Figure 7 and

the pulse mask requirements given

in Figure 8.

8) Maximum Voltage

The maximum peak-to-peak value

VUmax of the voltage VU as shown

in Figure 3 with full receive signal

(short line) is 2.5V. Due to the ana-

log echo subtraction the maximum

peak-to-peak value Vinmax of the

voltage Vin between LIN1 and LIN2

is 1.7V.

9) Input/Output Impedance

The line terminating impedance is

135Ωin power-up and in power-

down state. The return loss at U0

measured against 135Ω(real)

exceeds; 20 dB between 10kHz

and 25kHz.

- slope below 10kHz: 20 dB /

decade

- slope above 25kHz: -20 dB /

decade

10) Load

The load is given by the line trans-

former and the subscriber line.

The loops are standardized by

the ANSI and ETSI documents.

Turns ratio of line transformer 1:2

Transformer coil inductance (from

line side): 15 mH ± 10%

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [3]

Analog Echo Subtraction

12 Ω

1:2

LIN1

LIN2

LOUT2

LOUT1

ILT

U0, short line

Fig.3: Test Circuit for Voltages VU and Vin at UO Interface

MTC-20278/9 150200 [4]

MTC-20278/9 ILTQ/ILTT

MTC-20279

Requirements for the

U- Line Ports

NOTE: Some of the specifications in

this section refer to the UK0

Interface and not to the line

ports (LOUT1, LOUT2, LIN1,

LIN2). The characteristics at the

line port are affected by the

design of the transformer and

the other external components.

Physical Characteristics

The ternary symbol stream on the U-

interface must comply to the following

physical characteristics:

1) Symbol Rate

The symbol rate is 120 kbaud ±

1 ppm and applies to synchronous

symbol transmission. The symbol

rate is controlled by an external

clock.

2) Input Jitter

The ILTT tolerates a sinusoidal input

jitter of the ternary symbols as indi-

cated in Figure 4.

3) Output Jitter

The peak-to-peak jitter produced by

the ILTT doesn’t exceed 0.02 UI

(166ns), when measured via a high

pass filter with a cut-off frequency of

30Hz. Without this filter the same

measurement doesn’t read more

than 0.1 UI. This performance is

only guaranteed when the input jitter

at the GCI clock is less than 15ns

peak-to-peak.

4) Transmit Signal Amplitude

The absolute peak value VImax of

a single pulse VI at UK0 interface

terminated with a 150Ωresistance

is 2V ± 0.2V. See the following

Figure. The absolute peak value of

the coded ternary signal measured

at UK0 interface terminated with

150Ωdoesn’t exceed 4V.

See Figure 4.

Jitter Amplitude

(peak-to-peak)

Jitter Amplitude

(peak-to-peak)

UI = Unit

Interval

UI = Unit

Interval

0,25 UIpp

0,025 UIpp

20 db/Decade

3 Hz 30 Hz 10 KHz

Jitter Frequency

Fig.4: Range of Admissable Sinusoidal Input Jitter, MTC-20278 and MTC-20279

MTC-20278/9 150200 [5]

MTC-20278/9 ILTQ/ILTT

5) Stability

The transmit signal amplitude mea-

sured over a period of one minute

doesn’t vary by more than 1%

beginning 5ms after the ILTT is

switched into power-up state.

6) Transmit Spectrum

The spectrum of the ternary transmit

signal at UK0 interface doesn’t

exceed the limits given in Figure 6.

7) Pulse Shape

A single pulse measured across a

150Ωresistance at the UK0 interface

comply to the spectral requirements

presented in Figure 7 and the pulse

mask requirements given in Figure 8.

8) Maximum Voltage

The maximum peak-to-peak value

VUmax of the voltage VU as shown

in Figure 5 with full receive signal

(short line), that must be accepted,

is 4V. Due to the analog echo sub-

traction the maximum peak-to-peak

value Vinmax of the voltage Vin

between LIN1 and LIN2 is 2.7V.

For ILTT, the value of n must be 1.6.

Analog Echo Subtraction

25 Ω

1:1.6

LIN1

LIN2

LOUT2

LOUT1

ILTT

UK0, short line

Fig.5: Test Circuit for Voltages VU and Vin at UK0 Interface

MTC-20278/9 150200 [6]

MTC-20278/9 ILTQ/ILTT

9) Input/Output Impedance

The line terminating impedance must

be 150Ωin power-up and in power-

down state. The return loss at UK0

measured against 150Ωreal must

exceed 16 dB between 12kHz and

50kHz.

- slope below 12kHz: 20 dB/decade

- slope above 50kHz: -10 dB/decade

10) Load

The load is given by the line trans-

former and the subscriber line.

Turns ratio of line transformer: 1.6

Transformer coil inductance (from line

side): 6.8mH ± 10%.

Measurement bandwith = 1 Khz

500 kHz

50 kHz

-90 dB

-30 dB

-80 dB

-20 dB

-70 dB

-60 dB

-50 dB

-40 dB

Frequency

Fig.6: Spectrum of Signal at UK0 Interface, MTC-20278

0.1 0.15 0.5 1 10 30 MHz

Frequency

5 dB/Decode

Band Width above 150 KHz = 9 KHz

1 V

100 mV

10 mV-40

-32

-26

-20

-23.4

0 dB

Fig.7: Single Pulse Mask

MTC-20278/9 150200 [7]

MTC-20278/9 ILTQ/ILTT

-U

-T 0

2.625 V

2.5 V

2.375 V

T= = 12.5 µs

80 KHz

25 mV

-25 mV T 14T2T

Time t

0.075 V

-0.125 V

0.4T-0.4T

SS SSSS

SSSS

Fig.8: Single Pulse Mask, MTC-20278

MTC-20278/9 150200 [8]

MTC-20278/9 ILTQ/ILTT

SSSS

2.2 V

2 V

1.8 V

T = 1

120 KHz = 8.33 µs

10 mV

-10 mV 0 T 2T 8T 30T

-U

-T

-0.2 V

0.2 V

Time t

Fig.9: Single Pulse Mask, MTC-20279

MTC-20278/9 150200 [9]

MTC-20278/9 ILTQ/ILTT

LOUT11

AVDD1

AVSS1

RD11

TRST

TCK

TMS

VDD

TDO

VSS

TDI

AREF2

LIN21

LIN22

RD23

NRESET

TSP

DOUT

VDD

DCLK

VSS

RD21

RD22

FD21

FD22

VSS

VDD

RD13

FD12

FD11

RD12

LIN12

RD31

RD32

RD33

FD31

VDD

FD42

FD41

RD42

AVSS4

MTC-20278 PQ-I

MTC-20279 PQ-I

ILTQ/ILTT

(80PQFP)

LIN11

AREF1

LOUT12

DIN

DFR

POS

AVSS3

AVDD3

RD43

RD41

LIN42

LINE41

AREF4

AVDD4

LOUT41

LOUT42

VSS

FD32

LOUT22

LOUT21

AVDD2

AVSS2

LOUT32

LIN32

LIN31

AREF3

LOUT31

Fig.10: ILT Pinout - 80 PQFP

MTC-20278/9 150200 [10]

MTC-20278/9 ILTQ/ILTT

Pin Description

Nr. Function Name Dir. Description

80 LOUT11 O U-Interface analog outputs. The pins LOUT11 and LOUT12

connect the U-driver outputs via termination resistors and the line

coupling transformer to the U0 reference point.

4 LOUT12 O

6 LIN11 I U-Interface analog inputs from the analog hybrid

7 LIN12 I

5 U1 AREF1 O Analog ground. Used as reference voltage for A/D and D/A.

79 Interface AVDD1 P +3.3V power supply for analog U-Interface functions

78 AVSS1 P 0V ground for analog U-Interface functions

77 RD11 / SPICS O Relay drivers 1

8 RD12 / SPICK O

11 RD13 IO Bidirectional I/O. Put in Input mode after HW reset, not affected by

SW reset

9 FD11 / SPIDI I Power feed status and control 1

10 FD12 / SPIDO O

20 LOUT21 O U-Interface analog outputs. The pins LOUT21 and LOUT22

connect the U-driver outputs via termination resistors and the line

coupling transformer to the U0 reference point.

24 LOUT22 O

26 LIN21 I U-Interface analog inputs from the analog hybrid

27 LIN22 I

25 U2 AREF2 O Analog ground. Used as reference voltage for A/D and D/A

19 Interface AVDD2 P +3.3V power supply for analog U-Interface functions

18 AVSS2 P 0V ground for analog U-Interface functions

17 RD21 O Relay drivers 2

16 RD22 O

28 RD23 IO Bidirectional I/O. Put in Input mode after HW reset, not affected by

SWreset

15 FD21 / SEL0 I Power feed status and control 2

14 FD22 O

40 LOUT31 O U-Interface analog outputs. The pins LOUT31 and LOUT32

connect the U-driver outputs via termination resistors and the line

coupling transformer to the U0 reference point.

44 LOUT32 O

46 LIN31 I U-Interface analog inputs from the analog hybrid

47 LIN32 I

45 AREF3 O Analog ground. Used as reference voltage for A/D and D/A.

39 U3 AVDD3 P +3.3V power supply for analog U-Interface functions

38 Interface AVSS3 P 0V ground for analog U-Interface functions

48 RD31 O Relay drivers 3

49 RD32 O

50 RD33 IO Bidirectional I/O. Put in Input mode after HW reset, not affected by

SW reset

51 FD31 / SEL1 I Power feed status and control 3

52 FD32 O

MTC-20278/9 150200 [11]

MTC-20278/9 ILTQ/ILTT

60 LOUT41 O U-Interface analog outputs. The pins LOUT41 and LOUT42

connect the U-driver outputs via termination resistors and the line

coupling transformers to the U0 reference point.

64 LOUT42 O

66 LIN41 I U-Interface analog inputs from the analog hybrid

67 U4 LIN42 I

65 Interface AREF4 O Analog ground. Used as reference voltage for A/D and D/A.

59 AVDD4 P +3.3V power supply for analog U-Interface functions

58 AVSS4 P 0V ground for analog U-Interface functions

68 RD41 O Relay drivers 4

57 RD42 O

69 RD43 IO Bidirectional I/O. Put in Input mode after HW reset, not affected by

SW reset

56 FD41 I Power feed status and control 4

55 FD42 O

31 DOUT O GCI data output at 2048 Kbits/s. Open drain output.

35 GCI DIN I GCI data input at 2048 Kbit/s

33 Interface DCLK I 4096kHz GCI clock

36 DFR I 8kHz GCI frame clock which identifies the beginning of the frame of

DIN and DOUT Normal use

76 TRST I TAP controller reset, active low 0

75 JTAG TCK I TAP controller clock, maximum 10MHz 0

74 Test TMS I TAP controller mode selection 0

70 Interface TDI I TAP controller input 0

72 TDO O TAP controller output open

29 NRESET I Hardware reset, active low. Schmit trigger input with treshold at 1.65V

(CMOS level).

30 TSP/DECT I 1. Transmit Single Pulses. ILT transmits single pulses of alternating

General maximum positive and negative polarity. Pulse repetition rate is 666Hz.

Applications: test purposes and search tone on the line.

2. DECT synchronization of the U-superframes (2B1Q only)

The distinction between the 2 modes is made based on the duty cycle of

the applied input signal: if logic ’1’ is present for more then 200ms,

TSP is assumed ; otherwise, a DECT sync is executed.

37 POS I ILT works in burst mode and consists of 4 line drivers, 1 line per burst.

POS = ’0’ means the 4 fisrt GCI bursts are taken

POS = ’1’ means the 4 last GCI bursts are taken

12 VDD P +3.3V power supply for digital functions

32 VDD P

54 Power VDD P

73 VDD P

13 VSS P 0V Ground for digital functions

34 VSS P

53 VSS P

71 VSS P

MTC-20278/9 150200 [12]

MTC-20278/9 ILTQ/ILTT

1:2

15 mH

(2B1Q)

VDD

VSS

LOUTn1

LOUTn2

LINn2

LINn1

AVDDn

AVSSn

AREFn

RDn1

FDn1

FDn2

RDn2

LINE

TEST RELAY

Test Bus

VDD

100 kΩ

NRESET

100 nF C1

VDD

VSS

VDD

VSS

TSP (0 for normal operation)

POS VDD

(strap to 0 or 1)

One of 4 indentical channels

Common for all channels

GCI bus

Passive Hybrid

R ,C

H H

1:1.3

6 mH

(4B3T)

RDn3

Line Feed

Power Supply

Fig.11: MTC-20278/9 ILT - Typical Component Configuration

MTC-20278/9 150200 [13]

MTC-20278/9 ILTQ/ILTT

Line 0

GCI bus 2k22k2

DIN

DOUT

DLCK

DFR

DIN

DOUT

DLCK

DFR

POS

DIN

DOUT

DLCK

DFR

POS

VDD

VSS

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

MTC-20278/9

Fig.12: Connection of two, MTC-20278/9 for an 8-line access on one GCI bus

MTC-20278/9 150200 [14]

MTC-20278/9 ILTQ/ILTT

Component Function Value Comment

Rh U feed bridge and hybrid ±1%

resistors see Fig. 13/14

R1 reset delay 100kΩ±5%

C1 reset delay 100 nF ±5%

C2 Digital supply decoupling 100 nF

C3 Analog reference decoupling 100 nF

C4 Analog supply decoupling 100 nF

CL Line-feed coupling 2.2 µF 250V

Ch Hybrid capacitance see Fig. 13/14 2%

Z overvoltage protection

Recommended Component Values

Table 2

Min/Typ Max Min/Typ Max

Turns Ratio 2:1 1.6:1

Prelimary Inductance (mH) 14.25 15.75 5.25 6.75

Leakage Inducatance (uH) 60 60

Interwinding Capacitance (pF max.) 90 90

PRI DCR (Ohms) 6 7 6 7

SEC DCR (Ohms) 2.8 3.3 3.5 4.2

(Alcatel Part Code TMP 00087 0003) (Alcatel Part Code TMP 00087 0002)

Transformer-Recommended Specifications

Table 1a (MTC-20278) Table 1b (MTC-20279)

MTC-20278/9 150200 [15]

MTC-20278/9 ILTQ/ILTT

Common Hybrid Shematics for 4B3T (MTC-20279) and 2B1Q (MTC-20278)

12,3 Ω

4n7

4k32

6k81

470p

39n

100

2n7

576

LIN 2

LOUT 2

LOUT 1

LIN 1

Fig.13: MTC-20278 - Recommended Hybrid component Configuration

Fig.14: MTC-20279 - Recommended Hybrid component Configuration

25 Ω

3k3

7k *

470p

LIN 2

LOUT 2

LOUT 1

LIN 1

+ short

++ open

* for FTZ loops, 470p -> 680p and 7 kΩ -> 6k8

MTC-20278

Logical Characteristics

of the U Interface

The quaternary symbol stream crossing

the U-interface complies with the follow-

ing logical characteristics:

Frame Structure

The information flow across the sub-

scriber line uses frames as shown in

Figure 15. The length of such a frame

corresponds to 120 quaternary symbols

being transmitted within 1.5ms. The

frame structure is detailed as follows.

B+B+D - Data

108 quaternary symbols represent 216

bits of scrambled and encoded B+B+D

data. The 108 quaternary symbols are

transmitted in succession. These blocks

are assembled as follows:

Synchronizing Word

9 quaternary symbols in each direction

represent a non-scrambled synchroniz-

ing word. They are used to generate

frame clocks. If they are out of position

for 60 . . . 200 consecutive frames,

the line resynchronization procedure

is started. The quaternary values and

the frame positions are as follows:

From LT to NT or analog loop in LT

(loop 1) and from NT to LT.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [16]

Quad

Position

Bit

Position

1-9

1-18

10-117

19-234

118-120

235-240

Frame 1 ISW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 2 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 3 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 4 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 5 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 6 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 7 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 8 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Fig.15: Frame and Superframe Structure

Data of: B1 + B2 + D + B1 + B2 + D

Number of bits: 8 8 2 8 8 2

SW Polarity: +3 +3 -3 -3 -3 +3 -3 +3 +3

ISW Polarity: -3 -3 +3 +3 +3 -3 +3 -3 -3

Maintenance and Service Channel

3 quaternary symbols per frame are

transmitted to convey maintenance and

embedded operations channel info-

rmation. This information is contained

in a superframe consisting of 8 frames

(duration: 12ms). The start of a super-

frame in the up and downstream direc-

tions is marked by a single inversion of

the synchronisation word. The quater-

nary symbol sequences represent data

that can be transmitted at a rate of 4

kbit/s. They are transmitted immediately

before the sync word.

The M symbol is used for various

purposes:

1) Maintenance Channel (control test

loops and report frame errors)

2) Service Channel (carry transparent

user data in both directions)

In detail the following convention

applies (LT to NT):

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [17]

M1 M2 M3 M4 M5 M6

Frame 1 EOC a1 EOC a2 EOC a3 ACT 1 1

Frame 2 EOC dm EOC i1 EOC i2 DEA 1 FEBE

Frame 3 EOC i3 EOC i4 EOC i5 1 CRC 1 CRC 2

Frame 4 EOC i6 EOC i7 EOC i8 1 CRC 3 CRC 4

Frame 5 EOC a1 EOC a2 EOC a3 1 CRC 5 CRC 6

Frame 6 EOC dm EOC i1 EOC i2 1 CRC 7 CRC 8

Frame 7 EOC i3 EOC i4 EOC i5 UOA CRC 9 CRC 10

Frame 8 EOC i6 EOC i7 EOC i8 AIB CRC 11 CRC 12

ACT: Activation bit (set to ONE during activation)

AIB: Alarm indication bit (set = 0 to indicate interruption)

CRC: Cyclic Redundancy Check: covers 2B+D & M4:

1 = most significant bit;

2 = next most significant bit, etc.

DEA: turn-off bit (set = 0 to announce turn-off)

EOC: Embedded operations channel:

a = address bit;

dm = data/message indicator;

i = information (data/message).

FEBE: Far end block error bit (ZERO for errored multiframes)

UOA: U-only-activation bit

Encoding

The encoding of a binary bit stream is

made such that 2 binary bits correspond

to 1quaternary symbol. The first symbol

of a frame will always contain the

information of the first 2 bits of a B1

channel (although these bits are of

course scrambled.

In the receive direction, the first symbol

of the quaternary frame is always

converted (after descrambling) into

the first two bits of a B1 channel.

The exact convertion is done according

to the following rules (ANSI specifica-

tion):

Quaternary Symbol First bit (sign) Second bit (Magnitude)

+3 1 0

+1 1 1

-1 0 1

-3 0 0

-1

X -1

-1

-p

Ds.X -23

Ds.X

: XOR function

Do = Di Ds.X Ds.X

-p -23

Scrambling

The received binary data stream is

divided by generating polynomials.

The scrambler contains supervision cir-

cuitry which flags if a continuous series

of ones or zeros have been detected at

the output for a complete 1ms frame.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [18]

-1

X -1

-1

-5

Ds.X -23

Ds.X

: XOR function

Fig.16: LT Transmit Scrambler

Fig.17: LT Receive Descrambler

Descrambling

The quaternary signals received on each

side of the subscriber line are converted

back into a binary bit stream and multi-

plied by the generating polynomials in

order to recover the original data.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [19]

Activation and Deactivation

In order to reduce the power con-

sumption of circuits connected to the

subscriber line, ILTQ can be switched

to stand-by or powered down during

the idle period. The components are

powered up again during the line

activation procedure. Two states are

defined:

- Power-down state

Power consumption of the majority of

the functions is reduced by stopping

the clocks; maximum power

reduction;

- Power-up state

All functions powered up; GCI inter-

face is activated; exchange of C/I

messages possible.

The activation procedure consists of

three phases: awake (see the following

sections), synchronize, and connect

through.

The phases of activation are shown in

the following table.

Conditions for ACT and CT (see table 3

on page 22).

Maximum activation time (from com-

mand ACT to indication CT) without

repeater for LT +NT:

- < 300ms under normal conditions

(starting with stored coefficients:

See note on DECT synchronisation).

- 15s after reset of the coefficients

With repeater, the activation may take

twice as long.

Maximum activation time (from com-

mand ACT to indication CT) without

repeater for LT:

- < 150ms under normal conditions

(starting with stored coefficients)

- 10s after reset of the coefficients

The deactivation procedure consists

of two phases: line deactivation and

power-down (see table 3).

The deactivation can be initiated only

by the command DEAC in the LT. The

deactivation of the LT can be initiated

only by INFO U0. The phases of deacti-

vation are indicated in the following

table.

Conditions for DC and DEAC (see table 3

on page 22).

Deactivation time (from Command

DEAC to Indication DC) is of the order

of 4ms.

With repeater the deactivation may take

twice as long.

Reset

The ILTQ can be reset via an external

pin (NRESET = LOW) or via the com-

mand RES in the C/I channel. Normally

the ILTQ is reset via the pin NRESET

(hardware reset).

The ILTQ is initialized such that a ”cold

start” (resetting of the coefficients) is

performed.

Resetting the component affects the

status of the driver pins; after HW reset

the drivers are switched off (low output

level) but not changed after SW reset.

(See also the Monitor channel).

Loops

For maintenance purposes a loop

can be closed by applying the correct

command via the M channel or the

GCI C/I channel.

Phase Indication

power-down DC

awake ACT

synchronize

connect through CT

Phase Indication

power-up CT

(connected through)

Line deactivation DEAC

power-down DC

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [20]

XXX

TSP/Dect

U line frame0 frame1

Fig.18b: Dect Synchronisation

DECT Synchronisation

The 4 U frames and superframes are

aligned with the DECT synchronisation

signal with a precision of 1 symbol, in

the activation procedure.

At the rising edge of the DECT signal,

bit and frame counters are set to zero.

DECT synchronisation needs soft or

hard reset, precludes total power-down

(that is replaced by partial power-

down), and warm-start may require 2.4

additional seconds. The DECT signal

has a periodicity of 2.4 seconds and

the width of the pulse can be between

13 and 375 microseconds.

Activation signals

Table 3: LT Activation Signals

Information

Station Description

TL A 10 kHz tone consisting of alternating four + 3 quats followed by four - 3 quats for a time period of two

frames.

SL0 No signal transmitted.

SL1 Synchronization word present, no superframe synchronization word (ISW), and 2B+D+M = 1.

SL2 Synchronization word present, superframe synchronization word (ISW) present, 2B+D = 0, and M =

Normal.

SL3 Synchronization word present, superframe synchronization word (ISW) present. M channel bits active.

Transmitted 2B+D data operational when M4 act bit = 1. When M4 act = 0, transmitted 2B+D data = 0.

The MTC-20278 can transmit any of the

signals shown in Table 3.

SL1 (optional)

SN2 SN3

2 frames SL2

TL SL3

T0 T1 T5T0 T0 T0 T0

T2 T4 T6 T7

6 frames

(optional)

6 frames

(optional)

6 frames

(optional)

A + C 5s for cold start

A + C 150ms for warm start

B + D 10s for cold start

B + D 150ms for warm start

AB C D

4 ms 480 ms

NT1 --> Network

Network --> NT1

Time: Description of event or state:

T0 RESET state.

T1 Network and NT1 are awake.

T2 NT1 discontinues transmission, indicating that the NT1 is ready to receive signal.

T3 Network responds to termination of signal and begins transmitting signal towards to NT1.

T4 Network begins transmitting SL2 towards the network, indicating that the network is ready to receive SN2.

T5 NT1 begins transmitting SN2 towards the network, indicating that NT1 has acquired FW frame and detected SL2.

T6 NT1 has acquired multiframe marker and is fully operational.

T7 Network has acquired multiframe marker and is fully operational.

NOTE 1: If the TL is repeated due to the persistence of FE 1, the repetition interval shall be > 25ms. At a repetition

interval larger than 480ms, the state machine will cause a TL tone if FE 1 remains.

NOTE 2: The maximum time between TL tone is defined to be 4ms. This requirement is unnecessarily strict.

To allow transceivers which cannot meet this the LT should wait for, and accept the TN tone, for a

period of 10ms from the beginning of issuing the TL tone.

Fig.18a: State sequence for transceiver start-up

MTC-20278/9 150200 [21]

MTC-20278/9 ILTQ/ILTT

Logical Characteristics

of the GCI Interface

MTC-20279

The ternary symbol stream crossing the

U-interface comply with the following

logical characteristics:

Frame Structure

The information flow across the sub-

scriber line utilizes frames as shown in

Figure 9. The length of such a frame

corresponds to 120 ternary symbols

being transmitted within 1ms. The

frame structure is detailed as follows.

B+B+D - Data

108 ternary symbols (T1 . . . T8) re-

present 144 bits of scrambled and

encoded B+B+D data. The 108 ternary

symbols are divided into four equally

structured groups in which each group

of 27 ternary symbols corresponds to

a block of 36 binary bits (consult also

Figure 9 and Figure 10). These blocks

are assembled as follows:

Data of: B1 + B2 + D + B1 + B2 + D

Number of bits: 8 8 2 8 8 2

Synchronizing Word

11 ternary symbols in each direction

(SW1, SW2) represent a non-scram-

bled synchronizing word. They are

used to generate frame clocks. If they

are out of position for 60 . . . 200

consecutive frames, the line resyn-

chronization procedure is started.

The ternary values and the frame

positions are as follows:

From LT to NT or analog loop in LT (loop 1) (LT Transmit):

Frame position: 110 111 112 113 114 115 116 117 118 119 120

SW1 Polarity: + + + - - - + - - + -

From NT to LT (LT Receive):

Frame position: 50 51 52 53 54 55 56 57 58 59 60

SW1 Polarity: - + - - + - - - + + +

MTC-20278/9 150200 [22]

MTC-20278/9 ILTQ/ILTT

Table 4: Ternary Frame Structure

T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1

T1 T1 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2

T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2

T2 T2 T2 T2 T2 T2 T3 T3 T3 T3 T3 T3

T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3

T3 T3 T3 T3 T3 T3 T3 T3 T3 T4 T4 T4

M1 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4

T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4

LT -› NT or analog loop in LT (loop 1)

123456789101112

108

120

123456789101112

T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5

M2 T5 T5 T5 T6 T6 T6 T6 T6 T6 T6 T6

T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6

T6 T6 T6 T6 T6 T6 T7 T7 T7 T7 T7 T7

T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7

T7 T7 T7 T7 T7 T7 T7 T7 T7 T8 T8 T8

T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8

108

120

NT -› LT

Legend:

T1 . . . T8: B + B + D - Data (ternary)

M1, M2: Maintenance and Service

Data (ternary)

SW1, SW2: Synchronizing Word

MTC-20278/9 150200 [23]

Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti Ti

B1 B1 B2 B2 B1 B1 B1 B2 B2 DDDD

1 3 6 9 12 15 18 25 27

. . .

14 8 1216182024 323436

. . .

i = 1 . . . 8

MTC-20278/9 ILTQ/ILTT

Fig.19: Binary to Ternary Unit Correspondence of B + B + D - Data

Maintenance and Service

Channel

The ternary symbols (M1, M2) re-

present non-scrambled data that can

be transmitted at a rate of 1 kBaud.

The frame position for M1 is 85 and

for M2 it is 25 (see Figure 9).

The M symbol is used for various

purposes:

1) Maintenance Channel (control test

loops and report frame errors)

2) Service Channel (carry transparent

user data in both directions); this is not

supported by the MTC-20279.

In detail the following convention

applies:

Meaning Encoding Direction

Idle 0 Both

Maintenance

Channel Loop 2 in NT (1) ++++........ from LT to NT

(M + Channel) Loop 4 in RPTR +0+0+...... from LT to RPTR

Frame Error (2) + (single symbol) from NT to LT

Table 5: Service and Maintenance Data Convention

MTC-20278/9 150200 [24]

MTC-20278/9 ILTQ/ILTT

NOTE 1:

A loop function is performed, if on

eight consecutive frames the ternary

encoding is recognized.

A loop function is finished if eight con-

secutive ternary zeros are recognized,

or on line deactivation.

Encoding

The encoding of a binary bit stream is

made such that 4 binary bits correspond

to 3 symbols of the ternary symbol

stream (4B/3T encoding scheme). The

encoding follows the rules of modified

monitoring state 43 (MMS 43) which

contains four alphabets. The left most

bit of the binary value in column 1 of

Figure 12 represents the first received

bit of the binary bit stream.

Corresponding to this, the left most

indicated symbol of the ternary word

is transmitted first.

The alphabet used for encoding of

a given binary block depends on the

digital sum of previous three ternary

symbols transmitted. Therefore, the

alphabet to be used for encoding of

the next binary block is indicated by

a suffix number beside each ternary

word.

After reset any alphabet can be used.

The running digital sum (RDS) is com-

puted in the RDS monitor (RDSM) from

the received ternary symbols.

NOTE 2:

One or more code violations detected

by RDS (Running Digital Sum) checks or

non-permissible series of 8 0_polarity

symbols within one frame lead to one

frame error.

When at the end of a ternary block the

running digital sum equals zero or five

a code violation has occured.

The RDS monitor is reset to one at the

beginning of each frame. RDS errors

which are reported back from the NT

to the LT are also accumulated in the

RDS monitor.

One or more RDS errors or one or

more series of five or more zeros within

one frame lead to one frame error.

Binary Ternary Alphabets (left symbol is transmitted first)

Information S1 S2 S3 S4

0001 0-+1 0-+2 0-+3 0-+4

0111 -0+1 -0+2 -0+3 -0+4

0100 -+01 -+02 -+03 -+04

0010 +-01 +-02 +-03 +-04

1011 +0-1 +0-2 +03 +0-4

1110 0+-1 0+-2 0+-3 0+-4

1001 +-+2 +-+3 +-+4 - - -1

0011 00+2 00+3 00+4 - - 02

1101 0+02 0+03 0+04 -0-2

1000 +002 +003 +004 0- -2

0110 -++2 -++3 -- --+2 - -+3

1010 ++-2 ++-3 +-- --2 +- -3

1111 ++03 00-1 00-2 00-3

0000 +0+3 0-01 0-02 0-03

0101 0++3 -001 -002 -003

1100 +++4 -+-1 -+-2 -+-3

Table 6: MMS 43 - Code

Note that the received 3T-word 000 is

transformed into a 4B-word of 0000.

This pattern occurs only during de-

activation.

MTC-20278/9 150200 [25]

Descrambling

The ternary signals received on each

side of the subscriber line are converted

back into a binary bit stream and multi-

plied by the generating polynomials in

order to recover the original data.

MTC-20278/9 ILTQ/ILTT

Scrambling

The received binary data stream is

divided by generating polynomials.

The scrambler contains supervision cir-

cuitry which flags if a continuous series

of ones or zeros have been detected at

the output for a complete 1ms frame.

Fig.20: LT transmit scrambler

-1

X -1

-1

-5

Ds.X -23

Ds.X

: XOR function

Ds = Di Ds.X Ds.X

-5 -23

Fig.21: LT receive descrambler

-1

X -1

-1

-p

Ds.X -23

Ds.X

: XOR function

Do = Ds Ds.X Ds.X

-p -23

p = 18 in Normal mode, p = 5 in Analog Loop (Loop1) mode

MTC-20278/9 150200 [26]

MTC-20278/9 ILTQ/ILTT

Activation and Deactivation

In order to reduce the power consump-

tion of circuits connected to the sub-

scriber line,the ILTT is powered down

during idle period. The components are

powered up again during the line acti-

vation procedure. Two states are

defined:

- Power-down state

Power consumption of the majority of

the functions is reduced by stopping

the clocks; maximum power reduction;

- Power-up state

All functions powered up.

The activation procedure consists of

three phases: awake (see the following

sections), synchronize, and connect

through.

The phases of activation are indicated

according to the following table.

Conditions for RDS, ACT and CT

see 8.2.

Maximum activation time (from com-

mand ACT to indication CT) without

RPTR:

-≤210ms under normal conditions

(starting with stored coefficients)

- 1.5s after reset of the coefficients

The deactivation procedure consists of

two phases: line deactivation and

power-down (see 8.2).

The deactivation can be initiated

only by the command DEAC in the

LT. The deactivation of the LT can be

initiated only by INFO U0. The phases

of deactivation are indicated in the

following table.

Phase Indication

power-down DC

awake ACT

synchronize RDS

connect through CT

Phase Indication

power-up CT

(connected through)

Line deactivation DEAC

power-down DC

Conditions for DC and DEAC see 8.2.

Deactivation time (from Command

DEAC to Indication DC) is in the order

of 4ms.

With RPTR the deactivation may take

twice as long.

Loop2 (Loop in NT)

For maintenance purposes a loop

can be closed by applying the correct

command into the M channel or into

the GCI C/I channel.

Reset

The ILTT can be reset via an external

pin (NRESET = LOW) or via the

command RES in the C/I channel.

Normally the ILTT is reset via the pin

NRESET (hardware reset).

Both reset requests cause via the activa-

tion/deactivation control (ACDECO)

and the reset logic a reset for various

functional blocks. The ILTT is initialized

such that after reset a “cold start”

(resetting of the coefficients) is forced.

Resetting the component affects the

status of the Relay drivers; after HW

reset the Relay drivers are switched

off (low output level), but after a SW

reset the status of the Relay drivers is

not modified. See also 8.4.

Note:

When powered down, execution of

commands via the M-Channel is not

possible. To allow M-Channel com-

mands to be used, issue the DGAC

command on the CII bits.

MTC-20278/9 150200 [27]

MTC-20278/9 ILTQ/ILTT

Logical Characteristics of the GCI Interface

Data Format and Timing

at the GCI Interface (DIN,

DOUT, DCLK, DFR)

Continuous Modes

- Nominal bitrate of data (DIN and

DOUT): 2048 kbit/s

- Nominal frequency of clock (DCLK):

4096kHz

- Nominal frequency of frame clock

(DFR): 8kHz

The frame is marked by the rising

edge of the frame clock DFR and the

data/frames are sampled on falling

edge of DCLK. Note that the position of

the falling edge of DFR is not important.

One frame contains 8 bursts 4 bytes.

The data streams at DIN and DOUT

consist of 32 bytes per frame. See

Figure 13. The input data DIN and the

output data DOUT are synchronous

and in phase.

Depending on the level of the pin POS.

The quad-LT takes the 4 first or the 4

last time-slots.

The following Figure shows the timing

of data and clocks at the digital inter-

face 2048 kbit/s (continuous modes).

See the AC characteristics section for

details. Transitions of the data occur

after even-numbered rising edges of

the clock DCLK. The data is valid on

the odd-numbered rising edges of the

clock DCLK.

Even-numbered rising edges of the

clock are defined as the second rising

edge following the rising edge of the

frame clock and every second rising

edge thereafter.

12345678

1234

DIN

DOUT

POS = 0

POS = 1

POS = 0

POS = 1

DFR

Valid ILT channel

Ignored

Hi-Z output

KEY

Fig.22: GCI Bus Multiplexing Timing Diagram

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [28]

DCLK

4096 kHz

Port

Signal

DFR

8 kHz

DIN

2048 kbit/s

(burstId-bitId)

DOUT

2048 kbit/s

(burstId-bitId)

Rising

edge no.

7-28 7-29 7-30 7-31 0-0 0-1 0-2 0-3 0-4 0-5 0-6 0-7 0-8

0 246 810121416

Fig.23: Timing of Data and Clocks at the 2048 kbit/s Interface

Frame Format

Within each time-slot, 4 bytes are transmitted:

1st byte B1: B channel (64 kbit/s data), transparent

2nd byte B2: B channel (64 kbit/s data), transparent

3rd byte B2*: Monitor channel

4th byte B1*: 2 bit D channel (16 kbit/s data)

4 bit C/I channel A1, A2, A3, A4

A, E bit used to control the transfer of information on the Monitor channel

Deactivate DEACR 0000 Request to deactivate U0. The transmitter outputs INFO U0.

After detecting the disappearance of an incoming signal at U0 the

indication DC is transmitted at module interface.

Reset RESI 0001 Reset of ILTQ to initial state.

Reset receiver RESR 0100 Reset of the ILTQ receiver only

Send Single Pulses TXSSP 0101 The ILTQ transmits single pulses at 1.5ms time intervals with alternate

polarity +3/-3.

Test TEST 0110 The ILTQ will be connected through from module interface to line

interface (transparent) without wake-up procedure.

U activation request ARUO 0111 Activation request of the U0 interface only.

Activate ACT 1000 Request to activate. ACT is indicated. The ILTQ is set in power-up state,

executing the complete activation of layer 1: the wake-up procedure is

executed by transmission of INFO U2W.

After successful wake-up process, the synchronization procedure is

started by transmission of INFO U2 (in case of LT).

Activation request 2 ACTX 1001 Activation request without 15 sec limit.

Analog Loop AL 1010 ACT is indicated.The analog transmitter output is looped back to the

receiver input (channels B+B+D), which is disconnected from the U0

interface.

Activation request 3 ACT0 1101 Activation request with ACT bit = 0.

DeactivateConfirmation DCON 1111 No signal is transmitted at U0 and the ILTQ is powerd down.

The wake-up detect circuitry remains enabled: thus a detected wake-up

signal INFO U1W is able to power-up the UIC and to initiate the

activation procedure, as in case of control ACT applied.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [29]

EAA4A3A2A1D2D1

B2* B1*B2B1

Time_slot

Fig.24: GCI Frame Format

Command and Indicate (C/I) Channel (A bits), MTC-20278

Command (DIN)

Note that RES or RES1 do not change the driver pins status while a hard reset configures RDi3 as input.

Note that at power-up, a DC command has to be given prior to any other command or DIN has to be one.

Deactivate DEACA 0001 The ILTQ is deactivating. Data transmission is impossible.

Loss of synchronization RSYN 0100 Loss of synchronization.

Error indication 2 EIST 0101 Error indication on the S/T interface.

U activation indication UAIN 0111 U activation indication.

Activate ACT 1000 The signal INFO U1W has been recognized by the wake-up detect

circuitry. The ILTQ is powered up and the activation procedure will be

executed.

Activation request info. ARMB 1001 Activation request maintenance bits

Error indication 3 EIRTI 1011 Error indication for timeout T1 (15s) or error on the U0 interface.

ConnectionThrough CT 1100 The transparent channels are connected through from module to line

interface (transparent). The activation of Layer 1 up to the terminals is

completed.

Loss of signal level on U LSLU 1101 Loss of signal level on U.

Deactivate indication DIN 1111 After deactivation of U0 (by the command DEAC) the disappearance of

incoming signal (INFO U0) has been detected.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [30]

Indication (DOUT)

Summary of C/I Codes:

Evaluation of any command is done

according to a double last look criterion:

any command is executed only after the

same command has been detected in

two successive frames. Until then, the

preceding command is considered

valid.

In case commands are received that

are not included in the list, the last

recognized command is considered

valid. Commands which are logically

impossible in the current state are

ignored (cfr ETR 80).

The indications are transmitted con-

tinuously in each frame.

Under no circumstances can an indica-

tion that is not included in the list be

transmitted.

Code A-bits

1 2 3 4 HEX DIN DOUT

0 0 0 0 0 DEACR

0 0 0 1 1 RESI DEACA

0010 2

0011 3

0 1 0 0 4 RESR RSYN

0 1 0 1 5 TXSSP EIST

0 1 1 0 6 TEST

0 1 1 1 7 ARUO UAIN

1 0 0 0 8 ACT ACT

1 0 0 1 9 ACTX ARMB

1010 A AL

1 0 1 1 B EIT1

1100 C CT

1 1 0 1 D ACT0 LSLU

1110 E

1 1 1 1 F DCON DIN

Table 8: C/I Codes Summary

A and E Bits

The A and E bits provide a handshake

procedure for the transfer of monitor

channel messages.

The transmitted E bit is put low for one

frame when a new information has

been written in the monitor channel. The

transmitter then waits for confirmation

indicted by the receiver puting low the

A bit for one frame.

Thus to send a monitor message from

the Exchange to the ILTQ, the E bit on

DIN and the A bit on DOUT are used.

In the opposite direction, the E bit on

DOUT and the A bit on DIN are used.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [31]

Code (hex) Down stream Up stream

00 Hold Hold Hold

50 CCLB Complete loop

51 CLB1 Close Loop B1

52 CLB2 Close Loop B2

53 RCCRC Request corrupt

CRC

54 NCCRC Notify corrupt CRC

AA NAC Not able to comply

FF Return Return to normal

XX ACKN Acknowledge*

MON-0 messages

Format:

0000 AAA1 FFFF FFFF

0000 = MON-0 command

AAA = Address

0 = NT

1..6 = Repeater

7 = Broadcast

FF...FF: EOC code (see table)

* ACKN: Acknowledge. The NT will acknowledge a valid MON command by

echoing it in the upstream direction.

Monitor Channel

Monitor messages sent to the ILTQ are

2 bytes long and monitor messages

returned by the ILTQ are also 2 bytes

long.

The monitor messages are split into

3 categories:

- MON-0: EOC programming

- MON-2: Overhead bits

- MON-8: Local functions

MTC-20278/9 150200 [32]

MTC-20278/9 ILTQ/ILTT

After hard reset:

RDx1: output

RDx2: output

RDx3: input

FDx1: input

FDx2: output

MON-command 817x will set the value

of the driving pins

The MON-command 816x will change

the direction of the RDx3 pin:

8160: input direction

8168: output direction

Note: so, for applications requiring

3 driver pins and 2 sens pins, the

MON-command and Hard-reset can

affect them.

The status of the drivers is not affected

by a soft-reset, only MON-command

and HARD-reset can affect them.

The MON-commands are executed in

“soft-reset” mode.

Up stream

D11 ACT Activation bit

D10 1

D9 1

D8 PS1 Power supply 1bit

D7 1

D6 FEBE Far-end block error occured

D5 PS2 Power supply 2 bit

D4 NTM

D3 CSO Nt-activation with cold start only

D2 1

D1 SAI S activity indicator

D0 1

MON-2 messages

Format:

0010 D11..8 D7..4 D3..0

Only the Up stream EOC messages

are supported. Down stream EOC

commands are controlled by the ILTQ.

MON-8 messages

Format: 1000 000A D7..4 D3..0

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [33]

7..0 Down stream Up stream

0 1111 0000 SCCRC Corrupt CRC

0 1111 1111 RTN Return to Normal

0 1111 1011 RBECN Read Near-end block error counter

0 1111 1010 RBECF Read Far-end block error counter

0 aaaa aaaa ABEC* Answer block error counter

1 0111 dcba SETDD Set state of driver pins

a: RDi1

b: Di2

c: FDi2

d: not used (RDi3 is INPUT)

1 0110 dcba SETDO Set status of driver pins

a: RDi1

b: RDi2

c: FDi2

d: RDi3 (pin is OUTPUT)

1 0000 0000 RSP Read status pins

1 xxxx xxxba ASP Answer status pins

a: read the pin FDi1

b: read the pin RDi3 (used as sens pin)

1 1000 0000 RPDUI Read propagation delay U-interface

e aaaa aaaa APDUI Answer propagation delay on U-interface

0 1111 1001 ZFEBE Set FEBE-Bit to zero

0 0000 0000 RCID Read chip identification

0 0000 1000 ACID Answer chip identification

e is 3 bits in length.

Total delay (inns) is given by the approximate formula:

D = N * 12,500 + S * M * 65ns

Where: N is the value represented by bits 10..8 of PDu

S is +1 when bit 7 of APDU is 0, or -1 if it is 1

M is the value represented by bits 6..0 of PDu

PDu is the 11-bit propagation-delay (U interface) word.

A more precise description can be found in application note ”DECT delay calibration for ILTQ”.

Format: 1000 100A D7..4 D3..0

7..0 Down stream Up stream

0 cccc cccc RCF Read coefficients at address cccc cccc

0 0000 0000 DCF Data coefficients, 1 byte, put to zero

MTC-20278/9 150200 [34]

MTC-20278/9 ILTQ/ILTT

Reset

CI = DEAC Deactivated

CI = DI

PowerDown

CI = DI

WaitTN

CI = DI

PendActivation

CI = ACT

Awake

CI = ARM TimeOut

CI =EI3

ResetReceiver

CI = LSL

Uactivated

CI = UAI

Act = 0, Deact = 1

Sactivated

CI = ACT

Act = 0, Deact = 1 Sdeactivated

CI = UAI

Act = 0, Deact = 1 ErrorOnS

CI =EI2

Act = 1, Deact = 1

LossOfSignal

CI = LSL

Act = 0, Deact = 1 LossOfSync

CI = RSY

Act = 0, Deact = 1 PendDeactivation

CI =DEAC

Act = 0, Deact = 0

Connection True

CI = CT

Act =1, Deact = 1

From Any State

CI = RES CI = DEAC

CI = RES1

15 sec.

Hardware Reset

CI = DC

CI = activationRequest

SN2received

15 sec.

toneNT

(CI = RES1) and LossOfSignal

[ (EOC_ACT = 1) and (CI I = ACT0) ] or (CI = AL)

CI = ACT0

LossOfSignal

LossOfSignal LossOfSignal CI = DEAC

CI = RES1 (CI = RES1) and

LossOfSignal

CI = UAR (EOC_SAI = 0) &

(EOC_ACT = 0) (EOC_SAI = 1) &

(EOC_ACT = 0)

SN3received and

fully converged

toneNT or (CI = AL)

MTC-20278 State Machine

activationRequest

CI = ACT

CI = ACTX

CI = ACT0

CI = UAR

CI = AL

CI CMD. IND.

0 DEAC

1 RES DEAC

4 RES1 RSY

5 SSP EI2

6 TEST

7 UAR UAI

8 ACT ACT

9 ACTX ARM

AAL

B EI3

CCT

D ACT0 LSL

FDCDI

Fig.25: MTC-20278 State Machine

MTC-20278/9 150200 [35]

MTC-20278/9 ILTQ/ILTT

MTC-20279 State Machine

Deactivated

CI = DI PendDeactivation

CI = DEAC

PowerDown

CI = DI

WaitTN

CI = ACT TestState

CI = DEAC

Usynchronizing

CI = ACT

Ssynchronizing

CI = RDS

U & S synchronizing

CI = RDS

ConnectionTrue

CI = CT Uresynchronizing

CI = RSYN

From Any State

CI = TEST

From Any State

CI = RES

CI = LTD

CI = SSP

From Any State

CI = DEAC

SIG3received

LossOfSync or

LossOfSignal

SIG3received

SIG1received

SIG3received or (CI = AL)

toneNT or (CI = AL)

LossOfSignal

CI = activationRequest

toneNT Hardware Reset

CI = DC

CI = activationRequest

CI = AL

1 ms

activationRequest

CI = ACT

CI = AL

CI = L2

CI = L4

CI CMD. IND.

0 DEAC

1 DEAC

3 LTD

4 RSYN

5 SSP

6 TEST

7 RDS

8 ACT ACT

9AL

AL2

BL4

CCT

D RES

FDCDC

Fig.26: MTC-20279 State Machine

Activate ACT 1000 ACT is indicated. The ILTT is set in power-up state, executing the complete activation of

layer 1: the wake-up procedure is executed by transmission of INFO U2W.

After successful wake-up process, the synchronization procedure is started by trans-

mission of INFO U2 (in case of LT).

When the receiver has been synchronized RDS is indicated.

When INFO U3 is recognized, INFO U4H is transmitted. Then the transparent channels

are connected through from module to line interface (transparent).

Analog Loop AL 1001 ACT is indicated. The analog transmitter output is looped back to the receiver input

(channels B+B+D), which is disconnected from UK0 interface.

The ILTT is set in power-up state, executing the activation of layer 1: A pseudo wake-up

procedure is executed. After successful wake-up procedure the transmitter generates

INFO U2. When synchronization is completed successfully, RDS is indicated. INFO

U4H is transmitted. The UIC is connected through from module interface to line interface

transparent).

Loop 2 L2 1010 ACT is indicated.Command to close loop 2 in the NT.As ACT, with the difference that

continuous positive polarity is transmitted in the M symbol at UK0.

NOTE: An L2 command can be applied in the deactivated state as well as in the

activated state.

Loop 4 L4 1011 ACT is indicated.Command to close loop 4 in the RPTR. As ACT with the difference that

continuous +/0 code is transmitted in the M symbol at UK0.

Deactivate DEAC 0000 Request to deactivate UK0. The transmitter outputs INFO U0. After detecting the dis-

appearance of an incoming signal at UK0 the indication DC is transmitted at module

interface. A wake-up signal will be disregarded.

Deactivate DC 1111 No signal is transmitted at UK0 and the ILTT is powered down. The wake-up detect

Confirmation circuitry remains enabled: thus a detected wake-up signal INFO U1W is able to power-

up the UIC and to initiate the activation procedure, as in case of control ACT applied.

NOTE: This command can be used to deactivate UK0 in case that after the command

DEAC the disappearance of an incoming signal is not detected and there is no indica

tion DC.

Reset RES 1101 Reset of ILTT to initial state.

Send SinglePulses SSP 0101 The ILTT transmits single pulses at 1ms time intervals with alternate polarity.

Test TEST 0110 The ILTT will be connected through from module interface to line interface (transparent)

without wake-up procedure.

Line Termination LTD 0011 The ILTT stops transmitting signals on the corresponding channel, ignoring awake

Disable signals. The channel stays in this state until a command RES, DEAC or DC is issued.

It then goes in power-down. Note that if RES or DEAC are used, they have to be

followed by DC.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [36]

Command and Indicate (C/I) Channel (A bits), MTC-20279

Command (DIN)

Activate ACT 1000 (1) The signal INFO U1W has been recognized by the wake-up detect circuitry.The

ILTT is powered up and the activation procedure will be executed.

(2) The control ACT is acknowledged by ACT. The controls L2, L4, AL are also ackn.

by ACT (not included in FTZ 1 R 210).

Running RDS 0111 During activation procedure, the receiver has synchronized (on INFO U1/U3/U5).

Digital Sum Evaluation of transmission quality is enabled.

Connection CT 1100 The transparent channels are connected through from module to line interface

Through (transparent). The activation of Layer 1 up to the terminals is completed. In case of a

loop 4 the activation up to the loop is completed.

In case of loop 2 the activation up to the NT is completed.

Deactivate DEAC 0001 The ILTT is deactivating. Data transmission is impossible.A wake-up signal at UK0

will be disregarded.The ILTT transmits either INFO U0 or single pulses (when the

command SSP or TSP is applied).

Deactivate DC 1111 After deactivation of UK0 (by the command DEAC) the disappear

Confirmation ance of in incoming signal (INFO U0) has been detected.

Resynchronization RSYN 0100 The receiver has lost framing and is attempting to resynchronize. The ILTT remains

connected through from module to line interface (transparent).

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [37]

Indication (DOUT)

List of codes:

Evaluation of any command is done

according to a double last look criterion:

any command is followed only after the

same command has been detected in

two successive frames. Until then the

preceding command is considered

valid.

In case commands are received that

are not included in the list the last

recognized command is considered

valid. Commands which are logically

impossible to receive in the correct

state are ignored (cfr ETR 80).

The indications are transmitted con-

tinuously in each frame.

Under no circumstances an indication

that is not included in the list is

transmitted.

Code A-bits

1 2 3 4 HEX DIN DOUT

0 0 0 0 0 DEAC

0 0 0 1 1 DEAC

0010 2

0 0 1 1 3 LTD

0 1 0 0 4 RSYN

0 1 0 1 5 SSP

0 1 1 0 6 TEST

0 1 1 1 7 RDS

1 0 0 0 8 ACT ACT

1 0 0 1 9 AL ARMB

1010 A L2

1011 B L4

1100 C CT

1 1 0 1 D RES

1110 E

1111 F DC DC

DEAC = Deactivate

LTD = Line Termination

Deactivate

RSYN = Resynchronization

SSP = Send Single Pulses

TEST = Test

ACT = Activate

AL = Analog Loop

L2 = Loop 2

L4 = Loop 4

Deactivate

CT = Connection Through

DC = Deactivate Confirmation

Master clock

The master clock of 15.36 MHz is

derived by PLL from the 4096 MHz GCI

clock. It is only available to the internal

circuits.

Boundry Scan

The JTAG State Machine

Production test of the device IO pins

is performed using the JTAG state

machine implemented in the on-chip

ARM. The test controller state transitions

are shown in the following Figure 27.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [38]

Fig.27: JTAG State Machine

Test-Logic reset

0xF

Run-Test/Idle

0xC

tms=0

tms=1

Select-DR-Scan

0x7

Capture-DR

0x6

Shift-DR

0x2

Exit-DR

0x1

Pause-DR

0x3

Exit2-DR

0x0

Update-DR

0x5

tms=1 tms=0

Select-IR-Scan

0x4

Capture-IR

0xE

Shift-IR

0xA

Exit-IR

0x9

Pause-IR

0xB

Update-IR

0xD

tms=1 tms=0

Exit2-IR

0x8

tms=0

tms=1

tms=0

tms=1

tms=1 tms=1

tms=1

tms=0

tms=1

tms=0

Reset

The boundary scan interface includes a

state-machine controller (TAP controller)

according to the IEEE standard. In order

to force the TAP controller into the cor-

rect state after power-up of the device, a

reset pulse must be applied to the TRST

signal. If the boundary scan interface is

to be used, TRST must be driven LOW,

and then HIGH again. If the boundary

scan is not to be used, the TRST input

pin should be tied permanently low. A

clock on TCK is not necessary to reset

the device.

Instruction Register

The instruction register is 4 bits in

length.

There is no parity bit. The fixed value

loaded into the instruction register

during the CAPTURE-IR controller state

is 0001.

Public Instructions

The following public instructions are

supported

Codes not listed in the table should be

considered reserved and must not be

used during boundary scan testing.

In the descriptions that follow, TDI and

TMS are sampled on the rising edge of

TCK and all output transitions on TDO

occur as a result of the falling edge of

TCK

EXTEST (0000)

The scan chain is placed in test mode

by the EXTEST instruction. The EXTEST

instruction connects the scan chain

between TDI and TDO.

In the CAPTURE-DR state, inputs from

the system logic and outputs from the

output scan cells to the system are cap-

tured by the scan cells. In the SHIFT-DR

state, the previously captured test data

is shifted out of the scan chain via the

TDO pin, while new test data is shifted

in via the TDI input. This data is applied

immediately to the system logic and

system pins.

SAMPLE/PRELOAD (0011)

The scan chain is placed in test mode

by the SAMPLE/PRELOAD instruction.

This instruction connects the scan chain

between TDI and TDO.

In the CAPTURE-DR state, inputs from the

system logic and outputs from the output

scan cells to the system are captured by

the scan cells. In the SHIFT-DR state, the

previously captured test data is shifted

out of the scan chain via the TDO pin.

The capture of the pins levels can be

done in normal operation.

INTEST (1100)

The scan chain is placed in test mode by

the INTEST instruction. This instruction

connects the scan chain between TDI

and TDO.

In the CAPTURE-DR state, the value of

the data applied from the core logic to

the output scan cells is captured. At the

same time, the value of the data applied

from the system logic to the input scan

cell is also captured by the scan cells.

In the SHIFT-DR state, the previously

captured test data is shifted out of the

scan chain via the TDO pin, while new

test data is shifted in via the TDI input.

BYPASS (1110)

The BYPASS instruction connects a 1 bit

shift register (the BYPASS register)

between the TDI pin and the TDO pin.

When the BYPASS instruction is loaded

into the instruction register, all the scan

cells are placed in their normal mode of

operation. The instruction has no effect

on the system pins.

In the CAPTURE-DR state, a logic 0 is

captured by the bypass register. In the

SHIFT-DR state, test data is shifted into

the bypass register via the TDI pin and

out via the TDO pin after a delay of one

TCK cycle. Note that the first bit out will

be a zero. The bypass register is not

affected in the update-DR state.

SCAN_N (0010)

This instruction connects the Scan Path

Select Register between TDI and TDO.

During the CAPTURE-DR state, the fixed

value 1000 is loaded into the register.

During the SHIFT-DR state, the ID num-

ber of the desired scan path is shifted

into the scan path select register. In the

UPDATE-DR state, the scan register of

the selected scan chain is connected

between TDI and TDO, and remains

connected until a subsequent SCAN_N

instruction is issued. On reset, scan

chain 3 is selected by default. The scan

path select register is 4 bits long.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [39]

Instruction Binary code

EXTEST 0000

SCAN_N 0010

SAMPLE/PRELOAD 0011

INTEST 1100

BYPASS 1111

Test Data Registers

There are a number of data registers

which may be connected between TDI

and TDO. They are: Bypass register,

Instruction register, Scan chain select

chains are reserved). Only the bypass

select register and scan chain 3 are

discussed.

Bypass Register

Purpose: Bypasses the device during

scan test by providing a path between

TDI and TDO.

Length: 1 bit

Operating mode: when the BYPASS

instruction is the current instruction in the

instruction register, serial data is trans-

ferred from TDI to TDO in shift-DR state

with a delay of one TCK clock cycle.

There is no parallel output from the

bypass register. A logic 0 is loaded

from the parallel input of the bypass

Instruction Register

Purpose:Changes the current TAP

instruction.

Length: 4 bits

Operating mode: when in SHIFT-IR

state, the instruction register is selected

as the serial path between TDI and TDO.

During the CAPTURE-IR state, the values

0001 binary is loaded into this register.

This is shifted out during shift-IR (LSB

first), while a new instruction is shifted

in (LSB first). During the UPDATE-IR state,

the value in the instruction register

becomes the current instruction. On

reset, IDCODE (reserved) becomes the

current instruction.

Scan Chain Select Register

Purpose: changes the currently active

scan chain.

Length: 4 bits

Operating mode: The external bound-

ary scan is selected by default at reset.

It is not allowed to select other registers

for boundary scan testing. The external

boundary scan corresponds to the scan

chain number 3.

External Boundary Scan Register

Purpose: boundary scan testing

Length: 25 bits

Operation: following digital component

pins are scanned and tested in bound-

ary scan mode

The relation betweeen the scanned pins

and the scan register sequence is de-

scribed in the following table (all digital

pins are included in the boundary scan

except for TDI, TDO,TMS, TCK, FD21,

FD31)

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [40]

Pin Direction INTEST EXTEST

TDI TDO TDI TDO

RD11 out x x

RD43 inout x x x x

RD41 out x x

RD42 out x x

FD41 in x x

FD42 inout x x x x

FD32 inout x x x x

RD33 inout x x x x

RD32 out x x

RD31 out x x

POS in x x

DFR in x x

DIN in x x

MTC-20278/9 150200 [41]

MTC-20278/9 ILTQ/ILTT

Pin Direction INTEST EXTEST

TDI TDO TDI TDO

DCLK in x x

DOUT out x x

TSP in x x

NRESET in x x

RD23 inout x x x x

RD21 out x x

RD22 out x x

FD22 out x x

RD13 inout x x x x

FD12 inout x x x x

FD11 in x x

RD12 out x x

Data entered at TDI will shift from position RD11 to RD12. Total delay between TDI and TDO is 26 clocks of TCK.

The positions marked ’x’ in the table should be interpreted as follows:

INTEST: data shifted in through TDI will be presented to the internal chip inputs

data from the internal chip outputs will be shifted to TDO

EXTEST: data shifted in through TDI will be presented to the external chip pins

data from the external chip pins will be shifted to TDO

MTC-20278/9 150200 [42]

Electrical Characteristics and Ratings

The NRESET input is a Schmitt Trigger input.

Absolute Maximum

Ratings

Stresses above those listed in this clause

can cause permanent device failure.

Exposure to absolute maximum ratings

for extended periods can effect device

reliability.

MTC-20278/9 ILTQ/ILTT

Symbol Description Min Max Unit

DVDD, AVDD power supply voltage VSS - 0.3 3.63 V

VIN input voltage on any pin VSS - 0.3 VDD + 0.3 AND < 3.63 V

Absolute Maximum Ratings,

Operating Ranges and Storage Conditions

Symbol Parameter Conditions Min Max Unit

VIH High Level Input Voltage 80% of VDD V

VIL Low Level Input Voltage 20% of VDD V

VIH NRESET Rising NRESET 1.7 1.9 V

VIL NRESET Falling NRESET 0.9 1.1 V

VOH High Level Output Voltage 85% of VDD V

VOL Low Level Output Voltage 0.4 V

CIN Input Capacitance, all inputs 1 pF

COUT Load Capacitance, all outputs 100 pF

MTC-20278/9 150200 [43]

MTC-20278/9 ILTQ/ILTT

Operating Ranges

Operating ranges define the limits for

functional operation and schematic

characteristics of the device as

described above, and for the reliability

specifications as listed. Functionality

outside these limits is not implied.

(1) U nominally loaded (U: 135Ωline

equivalent) for random signal.

(2) Transition from power-up to power-

down automatically follows when trans-

mission on U is terminated. Transition to

power-up state occurs when a wakeup

signal is received from U or when

activity is detected on the data input

of the GCI interface.

Total cumulative dwell time outside the

normal power supplyVoltage range or

the ambient temperature under bias

must be less than 0.1% of the useful life

as defined in the reliability section.

Symbol Description Min Max Unit

DVDD, AVDD power supply 3.135 3.465 V

PTOT total power consumption 250 (1) mW/line

PPD power down power consumption 16 (2) mW/line

Tamb ambient temperature - I version -40 85 °C

Tamb ambient temperature - C version 0 70 °C

SNAVDD analog supply noise 30 mVPP

SNDVDD digital supply noise 100 mVPP

AC Characteristics

GCI Pins

Timing for: DCLK, DFR, DIN, DOUT

bit 0 bit1 bit2

Detail A

DCLK

DFR

DOUT/DIN

Fig.28: Timing for: DCLK, DFR, DIN, DOUT

Timing ReferenceVoltages

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [44]

tr tf

twH

DCLK

DFR

tDCL twL

tsF thF

twFH

tdDC

tdDF

tsD thD

DIN

DOUT

Voltage High Low

Output 2.4V 0.4V

Input 2.0V 0.8V

Parameter Signal Mnem. Units Min Max

Clock Period DCLK tDCL ns 239 249

Pulse width DCLK twL, twH ns 90 -

(2048 kbps)

Frame DFR tsF ns 70 tDCL-50

Frame Rise/Fall DFR tr, tf ns 60

Frame Width H DFR twFH ns 130 -

Frame Width L DFR twFL ns tDCL -

Frame Hold DFR thF ns 50 -

Data delay, Clock DOUT tdDC ns - 100 (1)

Data delay, Frame DOUT tdDF ns - 150 (1)

Data setup DIN tsD ns twH + 20 -

Data Hold DIN thD ns 50 -

Note 1: Cload = 150pF.

Fig.29: Timing for: DCLK, DFR, DIN, DOUT

Timing for JTAG, PINS: TCK, TMS, TDI, TDO (TRST asynchronous).

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [45]

T bscl T bsch

T bsis T bsih

T bsod

T bsoh

T bsss T bssh

T bsdd

T bsdh T bsdh T bsdd

Symbol Parameter (Time inns) Min Typ Max Notes

Tbscl TCK low period 15.1

Tbsch TCK high period 15.1

Tbsis TDI, TMS setup to [TCr] 3.6

Tbsih TDI, TMS hold from [TCr] 7.6

Tbsoh TDO hold time 2.4

Tbsod TCr to TDOValid 16.4

Tbsss I/O signal setup to [TCr] 3.6

Tbssh I/O signal hold from [TCr] 7.6

Tbsdh data output hold time 2.4

Tbsdd TCf to data outputValid 17.1

Tbsr Reset period 25

Fig.30: Timing for JTAG, PINS: TCK, TMS, TDI, TDO (TRST asynchronous)

MTC-20278/9 150200 [46]

MTC-20278/9 ILTQ/ILTT

Operating Environment

The components are intended for

application in equipment for indoor

operation without forced cooling air

flow, only convection.

Storage Conditions

Temperature should be in the range -55

to 110°C.

In case of IC deliveries in dry bag,

the conditions of time and humidity

during storage are specified in Alcatel

specification16650.

In case of IC deliveries not in dry bag,

the conditions for a maximum storage

period of 2 years are as follows:

Ambient Temperature (°C) Relative Humidity (%)

20 80

30 70

40 60

50 50

MTC-20278/9 150200 [47]

MTC-20278/9 ILTQ/ILTT

Quality

Product Accaptance

Tests

All products are tested 100%, at ambient

temperature with full temperature range

guardband, by means of production

test programs that guarantee optimal

coverage of the product specification.

Lot-by-lot Acceptance

Test

Lot conformance to specification of pro-

ducts delivered in Volume production is

guaranteed by means of following tests:

Delivery lot certification

Each delivery lot is accompanied by a

Certificate of Conformance.

Quality system

A quality system with certification

against ISO9001 is maintained.

Test Conditions AQL Level Inspection Level

Electrical, functional and parametric To product specification at Tamb = 25°C 0.04 II

with full temperature range performance

guardband.

ExternalVisual Physical damage to body or leads. 0.04 II

Dimensions affecting PCB manufacturability

such as bent leads, coplanarity, ...

ExternalVisual Correctness of marking 0.65 II

Reliability Specification

In order to guarantee the specified

reliability, a product qualification

for each product is performed. This

qualification is described in the Alcatel

Microelectronics specification document

15503.

In order to minimize reliability testing,

structural similarity is applied. Methods

and criteria are defined in the

documents 15501 (assembly) and

15502 (wafer fabrication).

Monitoring of assembly and wafer

fabrication is performed according to

the specifications 15910 and 15205.

These monitoring tests include the

solderability tests.

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [48]

Tjunction (°C) Early failure period (Hrs) Long term failure rate (FIT)

55 8760 100

65 4000 200

75 2000 400

85 1000 800

90 800 1000

The Intrinsic Failure

Rate

When operating the component under

benign conditions, the intrinsic failure

rate will not exceed:

- 5000 ppm during the early failure peri

od defined below

- the long term failure rate as specified

below after the early failure period

Failures due to external overstresses

such as ESD,Voltage and current over-

stress (e.g. due to EMI), excessive

mechanical and thermal shocks, ... are

not included in these Figures (see next

paragraph).

External Stress Immunity

Electrostatic discharges:

The device withstands 1000Volts

Standardized Human Body Modle

ESD pulses when tested according

to MIL883C method 3015.5 (pin com-

bination 2).

Latch-up:

Static latch-up protection level is 100

mA at 25°C when tested according to

JEDEC no. 17.

The Useful Life

The useful life, when used under

moderate conditions, is at least 25

years. The term useful life is specified

as the point in the lifetime where the

intrinsic failure rate exceeds the long

term failure rate specified above.

MTC-20278/9 150200 [49]

MTC-20278/9 ILTQ/ILTT

Fig.31: 80 PQFP Package Drawing

0.791(20.10)

0.783(19.90)

0.923(23.45)

0.903(22.95)

.113(2.87)

.101(2.57)

.018(0.45)

.008(0.20)

TYP .063(1.60)

Pin 1

TYP .031(0.80)

MAX .134(3.40)

MIN .002(0.05)

0°C - 10°C

.041(1.03)

.025(0.65)

0.555(14.10)

0.547(13.90)

0.687(17.45)

0.667(16.95)

0°C - 10°C

TYP.006(0.15)

All dimensions are in inches and

parenthetically in millimeters.

Inches dimensions are approximated.

Notes

MTC-20278/9 150200 [50]

MTC-20278/9 ILTQ/ILTT

MTC-20278/9 150200 [51]

MTC-20278/9 ILTQ/ILTT

Notes

MTC-20278/9 150200 [52]

03/00-0278b

Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document.

This document contains information on a new product.

Alcatel Microelectronics

reserves the right to make

changes in specifications at any time and without notice.

The information furnished by

Alcatel Microelectronics

this document is believed to be accurate and reliable.

However, no responsibility is assumed by

Alcatel

Microelectronics

for its use, nor for any infringements of

patents or other rights of third parties resulting from its use.

No licence is granted under any patents or patent rights

Alcatel Microelectronics

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Fax +90 216 420 7584

USA

3101 Industrial Drive

Suite 206, Raleigh

North Carolina 27609,

Tel. +1 919 850 67 31

Fax +1 919 850 66 89

USA

P.O. Box 750699

Petaluma, CA 94975

0699

Tel. +1 707 665 8013

Fax +1 707 792 6310

REPRESENTATIVES / DISTRIBUTION

Europe

Northern Germany, TRIAS, Moerser Landstraße 408, 47802 Krefeld, Germany, Tel. +49 2151 95 30 111, Fax +49 2151 95 30 115

UK,

Alpha Micro Comp., Springfield House, Cranes Road, Sherborne St. John, Basingstoke, Hampshire RG24 9LJ, Tel. +44 1256 851770, Fax +44 1256 851771

Spain, Newtek Electronica SA, Centro Empresarial El Plantio, c/Ochandiano 8, 2 Izq., 28023 Madrid, Spain, Tel. +34 91 3076893, Fax +34 91 3729453

Portugal, Comdist, Rua Entreposto Industrial, 3-20 Sala E Edificio Turia, 2720 Alfragide, Portugal, Tel. +35 1 147 251 90, Fax +35 1 147 25 1 99

Israel, Newtek, nr5 Yoni Nethanyahu St., Or-Yehuda 60200, Israel, Tel. +972 3 6344 564, Fax +972 3 6344 568

Asia

China, Shangai Belling Corp., 810 YiShan Rd., Shangai, China, Tel. +86 21 64850700, Fax +86 21 64854424

Hong Kong, Pr. Microelectr. Sales, Room 2101/2, 21/F, Westlands Centre, 20 Westlands Rd, Quarry Bay, Tel. +852 29604611, Fax +852 29600185

Taiwan, Pr. Microelectr. Sales, 3F, No.68, Chou-Tze St., Nei Hu Dist., Taipei 114, Taiwan, R.O.C., Tel. +886 2 8797 6826, Fax +886 2 8797 6827

USA (Premier Technical Sales)

East Canada, 43 Pretty Street, Stittsville, Ontario, K2S1N5 Canada, Tel. +1 613 836 1779, Fax +1 613 836 4459

N. California, 3235 Kiffer Road, Suite 110, Santa Clara, CA 95051, Tel. +1 408 736 2260 (105), Fax +1 408 736 2826

Arizona, 84 West Cypress St, Phoenix, AZ 85003, Tel. +1 602 254 8952, Fax +1 602 229 1100

Boston, 33 Boston Post West, Suite 270, Marlboro, MA 01752, Tel. +1 508 460 1730, Fax +1 508 460 1731

Chicago, 7628 W. Fullerton Avenue, Elorwood Park, IL 60707, Tel. +1 708 583 2372, Fax +1 708 583 2364

Oregan, 5319 S.W. Westgate Dr. Suite 136, Portland, OR 97221, Tel. +1 503 297 3956, Fax +1 503 297 4956

Texas, 800 East Campbell Road, Suite 199, Richardson, TX 75081, Tel. +1 972 680 5233, Fax +1 972 680 5234

Colorado, 1010 Broadview Place, Colorado Springs, CO 80904, Tel. +1 719 632 8340, Fax +1 719 632 1951

Georgia, 11140 Quailbrook Chase, Duluth, GA 30097, Tel. +1 770 476 1235, Fax +1 770 476 3989

New Jersey, 1015 Horseshoe Trail, Volley Forge, PA 194820342, Tel. +1 610 783 1919, Fax +1 610 783 6492

Alcatel Microelectronics

info@mie.alcatel.be

http://www.alcatel.com/telecom/micro