8085A 8085A 8-Bit Microprocessor MILITARY INFORMATION DISTINCTIVE CHARACTERISTICS @ SMD/DESC qualified @ 3- and 5-MHz selections available On-chip system controller, advanced cycle status infor- mation available for large system control Four vectored interrupts (one is non-maskable) On-chip clock generator (with external crystal, LC or R/C network) Serial-in/serial-out port Decimal, binary, and double-precision arithmetic Direct addressing capability to 64K bytes of memory 1.3 ys instruction cycle (8085A) 0.8 us instruction cycle (8085A-2) 100% software-compatible with 8080A Single +5 V power supply GENERAL DESCRIPTION The 8085A is a new generation, complete 8-bit parallel central processing unit (CPU). !ts instruction set is 100% software compatible with the 8G80A microprocessor. Spe- cifically, the 8085A incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provid- ed for the 8080A. The 8085A-2 is a faster version of the 8085A. The 8085A is a 3-MHz CPU with 10% supply tolerances and lower power consumption. The 8085A uses a multiplexed data bus. The address is split between the 8-bit address bus and the 8-bit data bus. The on-chip address latches of 8155H/56H memory prod- ucts allow a direct interface with 8085A. The 8085A components, including various timing-compatible support chips, allow system speed optimization. BLOCK DIAGRAM TTTTTT TT a it -BIT TERNAL OATA BUS B c s AEG. REG. 2 a a REG. REG, H s L 8 REG. fEG. stacxpowren 8} | ARPAY program counren * power | +5 supecy | ano ADDRESS LATCH 1% TING AND CONTROL ue x x2 CuK CONTROL sta OMA, RESET | s | 86 BUFFER | Gen __ _ TT | DATAIADORE! wr a SET RESET A07-AD0 cixour neapy #6 WR ALE $0 St 10 HOLD HLDA RESET IN pied AIS-AS ADO os BD003790 Publication # Rev. 09231 A Issue Date: November 1987 Amendment 40CONNECTION DIAGRAM Top View DIPs ucjre 40 [7 vec xT] 2 39 [MOLD RESET OUT(C] 3 38 [JHLDA soo] 4 37 [CLK (OUT) sit] s 36 FORESET IN TRAP{_] 6 35 [JREaDy RST 7.5(-]7 4 Dom astes(Cl}a 33/781 RsT55C]9 32 (CAG intA (J 10 aC WR WA] 11 30 [ace apa (J 12 29 [7180 abi([7 13 20 [Fats ad2(7} 14 27 [ata a03(] 15 26 [J ara ADs] 16 25 [Jatz aps(_] 17 24 [ant aoe (J 18 23 [Jato AQ? 19 22 [lag vss] 20 21 [as cb005564 Note: Pin 1 is marked for orientation. MILITARY ORDERING INFORMATION Standard Military Drawing (SMD)/DESC Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Military Drawing (SMD)/DESC products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Military Drawing Part Number b. Device Type c. Case Outline d. Lead Finish 79010 OL Q x [__ d. LEAD FINISH X = Any Lead Finish Acceptable c. CASE OUTLINE Q = 40-Pin Ceramic DIP (CD 040) b. MILITARY DEVICE TYPE 01 =3 MHz (8085A) a. MILITARY DRAWING PART NUMBER 79010 8-Bit Microprocessor Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD OX sales office to confirm availability of specific valid combinations or to check on newly released valid combinations. 7901001 Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. 3-15 vseos8085A AMD products for Aerospace and D MILITARY ORDERING INFORMATION (Cont'd.) APL Products efense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MiL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) c. Device Class d. Package Type e. Lead Finish a A f . LEAD FINISH A=Hot Solder Dip d. PACKAGE TYPE Q = 40-Pin Ceramic DIP (CD 040) c. DEVICE CLASS /B=Class B 8085A 8-Bit Microprocessor b. SPEED OPTION Blank = 3 MHz -2=5 MHz a. DEVICE NUMBER/DESCRIPTION Valid Combinations Valid Combinations Valid Combinations list configurations planned to be 80a5A /BQA 8085A-2 supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check for newly released valid combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, B, 9, 10, 17. 3-16ABSOLUTE MAXIMUM RATINGS Storage Temperature ........0000... cece eee. -65 to +150C Voltage on Any Pin With Respect to Ground........0....00ccc..00 0. -0.5 to +7 V Power Dissipation ........0.. 0000... ccceccecceeeecccseeseceeeee 15 W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Military (M) Devices Temperature (TC)....... oe cccccecccccecceee ee -55 to +125C Supply Voltage (Vcc) ... 5 V +10% Supply Current (ICC) .........eeccceccceceecccevencenees 200 mA Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range (for SMD/DESC and APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Parameter Parameter Symbol Description Test Conditions Min. Max. Unit VIL Input LOW Voltage Veco =5 V +10% +0.8 Vv Vin Input HIGH Voltage Voc =5 V 10% J Vcc +0.5* Vv VoL Output LOW Voltage lov =2 MA, Voc =5 V +3 a BO 0.45 Vv Vou Output HIGH Voitage low =-400 pAy, Vaky= 5 fo he Vv Ioc Power Supply Current Voc Ni } 4 200 mA tua Input Leakage, Except Pin 1 : = IN =M%icc to 0 V +10 BA lite Input Leakage, Pi : VV, ViIN=Voc too Vv +70 BA ILo * cc = 5.5 V, VouT= Voc to .45 V +10 BA Vir Voo=5 V 10% -0.5* +08 v VIHR Voc =5 V +10% 2.4 Voc +0.5* v Vuy Voc = 5 V 10% 0.25 Vv Guaranteed by design; not tested. Notes: 1. Icc is measured while running a functional pattern with no loads applied. See Section 6 af the MOS Microprocessors and Peripherals Data Book (Order #09067A) for Thermal Characteristics Information. 3-17 vss0s8085A SWITCHING CHARACTERISTICS over operating range (for SMD/DESC and APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) 8085A 8085A-2 (Note 2) (Note 2) Parameter Parameter Symbol Description Min. Max. Min. Max. Unit Icyc CLK Cycle Period 320 2000 200 2000 ns " CLK LOW Time (Standard CLK Loading) 80 40 ns te CLK HIGH Time (Standard CLK Loading) 120 70 ns ty, tf CLK Rise and Fall Time 30 30 ns ixkA X; Rising to CLK Rising 20 126 20 100 ns &XKF X41 Rising to CLK Falling 20 150 20 110 ns tac Ag.15 Valid to Leading Edge of Control (Note 1) 270 115 ns tact Ao.7 Valid to Leading Edge of Control 240 115 ns tad Ag.15 Valid to Valid Data In 575 350 ns tara Adcress Ita After Leading Edge of 0 0 ns (INTA) TAL Ag.15 Valid Before Trailing Edge of ALE (Note 1) 90 50 ns TALL Ao.7 Valid Before Trailing Edge of ALE 70 50 ns tary READY Valid from Address Valid 220 100 ns tca Address (Ag.15) Valid After Control 120 a. De E50 ns toc eaae o panto! Low (RD, WR, INTA) 400 : ae F030 ns tot eae Edge of Control to Leading Edge 50. 2 25 ns tow Data Valid to Trailing Edge of WRITE 420 230 ns tHABE HLDA to Bus Enable a mw 210 150 ns tHABF Bus Float After HLDA , ., 210 150 ns tHACK HLDA Valid to Trailing Edge of CLK a _ 1 40 ns tHDH HOLD Hold Time ge | FO 0 ns tHDS HOLD Setup Time to Trailing Edge of CLK a, 170 120 ns TINH INTR Hold Time Z 0 0 ns tLA Address Hold Time After 100 50 ns ve arama E c ~ tLcK ALE LOW Duri 100 50 ns {LDR ALE to Valid Data Read 460 270 ns tLow ALE to Valid Data Diring Write 200 120 ns tLe ALE Width 140 80 ns tLRY ALE to READY Stable 110 30 ns IRAE Trailing Ease of READ to Re-Enabling 150 90 ns tro READ (or INTA) to Valid Data 300 150 ns try Conroe anna. Edge to Leading Edge 400 220 ns tRDH Data Hold Time After READ INTA (Note 6) 0 0 ns tavH READY Hold Time 0 0 ns trys READ Setup Time to Leading Edge 410 400 ns two Data Valid After Trailing Edge of WRITE 100 60 ns tWDL LEADING Edge of WRITE to Data Valid 40 20 ns Notes: 1. Ag-A15 address Specs apply to 10/M, So, and Sy, except Ag-A1s are undefined during T4-Tg of OF cycle; whereas, 10/M, So, and S$; are stable. 2 Test conditions: tovc = 320 ns (80B5A)/200 ns (B085A-2); CL = 100 pF, Vog= 5 V #10%, ViL = 45 V, Vin=2.4 Vs VoL=.8 V Vou = 2.0 V. 3. For all output timing where C, = 150 pF use the following correction factors: 25 pF mm 0257525 027000 0 ~~ CHAPTER 6 al General Information T-90-20 PACKAGE OUTLINES* Ceramic DIPs (CD) CD 024 1.235 1.290 o Moo oon 24 13 565 ) 3 1 12 ae aa | Is) rl | .005 MIN 050 .100 id 065 BSC 015 (| 060 160 | 0 n Kiso 908 0 ae Tie " .700 O15 022 Fibs 071563 CD 028 1.435 1.490 OOo oo ooor 28 15 SES ) s 1 14 COO WT OO Oooo | > Is] rt Ht .005 MIN, 050 100 on 065 Bsc 015 (| 060 2160 0 220 t 15 008 ia r 150 MIN. O12 1 700 Iq [+- iin O15 022 PIDs 068978 * For reference only. NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 1780 A-11 6-1ADVANCED MICRO DEVICES AbD D> CHAPTER 6 General Information Mm ocs?se5 ao27001 2 | T-90-20 PACKAGE OUTLINES (Continued) Ceramic DIPs (CD) (Continued) CD 040 2.035 2,090 40 ) 20 le | => | MAX. OOOO OOOO ooo 21 TITITITICIP OO wt BCU tr Oi ti lic bi or lie 3 m J+ .005 MIN. CDV040 2.035 I" 2.000 pono H- 098 MAX, 40 21 20 ~ ) + \/ COC Cr cr cr cc cr a i le 005 MIN. 050 100 065 BSC NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. PDs o7s808 1781 Aa-12 6-2ADVANCED MICRO DEVICES = IhD D MM O2S7525 O027002 4 mm CHAPTER 6 ; General information PACKAGE OUTLINES (Continued) T-90-20 Ceramic Sidebrazed DIPs (SD) | SD 040 | 1.970 a0 14,098 MAX, T CL LL on it 20 WI eto oo Co Or oo ooo rear araareaaees 005 Mn [ 018 wn $9 __y i } et ajpunF 008 ee ms O12 age ws | 28 SD 048 4 CJS BT oo ooo oT Eo eT eo 2 005 MIN. 005MIN~*|le 4 cn 015 S30 100 060 : , 1175 ; t 125 160 gout of 8 ea .090 .030 o| [015 410 060 022 PID s075468 NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 6-3 17 82 A-13CHAPTER 6 T-90-20 General Information PACKAGE OUTLINES (Continued) Ceramic Leadless Chip Carriers (CL/CLV) CL 044 PLANE 2 PLANE 41 ; a * ale ai 44 PLACES / a (txt) C--. Tf r= 045 ; .055 3 eo @ $60 0g # | 022 F- [7 At J a y lm 923 | [+#.625 MAX +__ 3 > PID soee2se CLV044 ow Zz ss 080 + 500 +30 054 . + (08s 44 PLACES a (x11) (VF | C 2 eo 660 L J | | = .625 MAX. j+$ 3 PID #097098 NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 6-4 1783 A-14ADVANCED MICRO DEVICES ib) D = OGes?sesS OGOe?004 & Mm 99-200 CHAPTER 6 General Information PACKAGE OUTLINES (Continued) 68-Pin Square Leadless Chip Carrier (CA2) CA2068 a 860 842 B88 +794 983 le | TH 1-88 pte 842 a + : 455 ~ T $8 438 os Ff oe (TOP) : v A ~ 4 + 045 MIN. | nur "L| te PLaces) 5 z cedtrom ~ | Aa_/N0EX CORNER PID #072878 NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 6-5 1784 B-01ADVANCED MICRO DEVICES WbD D MM OeS?S5e5 OOe?ous T CHAPTER 6 T~-90-20 General Information PACKAGE OUTLINES (Continued) Ceramic Pin-Grid-Array Package (CG/CGX) CGX068 BOTTOM VIEW 4 1.140 > pl eq 028 (REFERENCE CORNER) + ns ee ee NY BCODE F GuHJK tL 1 ccoobooce| | I 2] 6000000000 ? 3] | ay 4] i e , 4.140 5] 1 v0 | gt -o-@-|- --1- -|-0-@ + - - -+- . asc 71 @ \ ee 080 + s| I o 140 9 OO { @@ 045 10 vopeogeoee| 6, == 11+ OOOOOOO we feeeeee? | | Sk / : >| 400 BSC .030 x 45 REF, (100 (3 PLACES) 300 jg 2080 .080 105 _ .195 PID #07547B NOTE: Package dimensions are given in inches. To convert to millimeters, multiply by 25.4. 1785 B~02 6-6