NUP4201MR6T1G - ON SEMICONDUCTOR

September, 2009 − Rev. 5

1Publication Order Number:

NUP4201MR6/D

NUP4201MR6

Transient Voltage

Suppressors

ESD Protection Diodes with Low

Clamping Voltage

The NUP4201MR6 transient voltage suppressor is designed to

protect high speed data lines from ESD, EFT, and lighting.

Features

•Low Clamping Voltage

•Stand−Off Voltage: 5 V

•Low Leakage

•TSOP−6 is footprint compatible with SC−74, SC−59 6 Lead and

SOT−23 6 Lead

•Protection for the Following IEC Standards:

IEC 61000−4−2 Level 4 ESD Protection

•UL Flammability Rating of 94 V−0

•Pb−Free Package is Available

Typical Applications

•High Speed Communication Line Protection

•USB 1.1 and 2.0 Power and Data Line Protection

•Digital Video Interface (DVI)

•Monitors and Flat Panel Displays

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Peak Power Dissipation

8 x 20 mS @ TA = 25°C (Note 1)

Ppk 500 W

Operating Junction Temperature Range TJ−40 to +125 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Solder Temperature −

Maximum (10 Seconds)

NUP4201MR6T1

NUP4201MR6T1G

235

260

°C

Human Body Model (HBM)

Machine Model (MM)

IEC 61000−4−2 Air (ESD)

IEC 61000−4−2 Contact (ESD)

ESD 16000

400

20000

IEC 61000−4−4 (5/50 ns) EFT 40 A

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)

See Application Note AND8308/D for further description of

survivability specs.

TSOP−6 LOW CAPACITANCE

DIODE TVS ARRAY

500 WATTS PEAK POWER

6 VOLTS

MARKING DIAGRAM

Device Package Shipping

ORDERING INFORMATION

NUP4201MR6T1 TSOP−6 3000/Tape & Reel

TSOP−6

CASE 318G

PLASTIC

PIN CONFIGURATION

AND SCHEMATIC

6 I/O

5 VP

4 I/O

I/O 1

VN 2

I/O 3

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63 = Specific Device Code

M = Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

NUP4201MR6T1G TSOP−6

(Pb−Free)

3000/Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

*Date Code orientation may vary

depending upon manufacturing location.

NUP4201MR6

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ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

IFForward Current

VFForward Voltage @ IF

Ppk Peak Power Dissipation

CCapacitance @ VR = 0 and f = 1.0 MHz

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional TVS

IPP

VRWM

VCVBR

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM (Note 2) 5.0 V

Breakdown Voltage VBR IT=1 mA, (Note 3) 6.0 V

Reverse Leakage Current IRVRWM = 5 V 5.0 mA

Clamping Voltage VCIPP = 5 A (Note 4) 12.5 V

Clamping Voltage VCIPP = 8 A (Note 4) 20 V

Maximum Peak Pulse Current IPP 8x20 ms Waveform (Note 4) 25 A

Junction Capacitance CJVR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF

Junction Capacitance CJVR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF

Clamping Voltage VC@ IPP = 1 A (Notes 5 and 6) 16.6 V

Clamping Voltage VCPer IEC 61000−4−2 (Note 7) Figure 1 and 2 V

2. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC

or continuous peak operating voltage level.

3. VBR is measured at pulse test current IT

4. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)

5. Non−repetitive current pulse per FIgure 5 (Any I/O Pins)

6. Surge current waveform per Figure 5.

7. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot

Positive 8 kV Contact per IEC61000−4−2

Figure 2. ESD Clamping Voltage Screenshot

Negative 8 kV Contact per IEC61000−4−2

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IEC 61000−4−2 Spec.

Level

Test

Voltage

(kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Figure 4. Diagram of ESD Test Setup

50 W

Cable

TVS Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

Figure 5. 8 X 20 ms Pulse Waveform

100

0020406080

t, TIME (ms)

% OF PEAK PULSE CURRENT

PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8 ms

PEAK VALUE IRSM @ 8 ms

HALF VALUE IRSM/2 @ 20 ms

NUP4201MR6

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TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

Figure 6. Pulse Derating Curve

100

00 25 50 75 100 125 150 175 200

TA, AMBIENT TEMPERATURE (°C)

Figure 7. Junction Capacitance vs Reverse Voltage

5.0

2.5

0.0 01

VBR, REVERSE VOLTAGE (V)

JUNCTION CAPACITANCE (pF)

2345

I/O lines

I/O−Ground

PEAK POWER DISSIPATION (%)

4.5

2.0

4.0

1.5

3.5

1.0

3.0

0.5

Figure 8. Clamping Voltage vs. Peak Pulse Current

(8 x 20 ms Waveform)

0010

PEAK PULSE CURRENT (A)

CLAMPING VOLTAGE (V)

20 30 40 50

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APPLICATIONS INFORMATION

The new NUP4201MR6 is a low capacitance TVS diode

array designed to protect sensitive electronics such as

communications systems, computers, and computer

peripherals against damage due to ESD events or transient

overvoltage conditions. Because of its low capacitance, it

can be used in high speed I/O data lines. The integrated

design of the NUP4201MR6 offers surge rated, low

capacitance steering diodes and a TVS diode integrated in

a single package (TSOP−6). If a transient condition occurs,

the steering diodes will drive the transient to the positive rail

of the power supply or to ground. The TVS device protects

the power line against overvoltage conditions to avoid

damage to the power supply and any downstream

components.

NUP4201MR6 Configuration Options

The NUP4201MR6 is able to protect up to four data lines

against transient overvoltage conditions by driving them to

a fixed reference point for clamping purposes. The steering

diodes will be forward biased whenever the voltage on the

protected line exceeds the reference voltage (Vf or VCC +

Vf). The diodes will force the transient current to bypass the

sensitive circuit.

Data lines are connected at pins 1, 3, 4 and 6. The negative

reference is connected at pin 2. These pins must be

connected directly to ground by using a ground plane to

minimize the PCB’s ground inductance. It is very important

to reduce the PCB trace lengths as much as possible to

minimize parasitic inductances.

Option 1

Protection of four data lines and the power supply using

VCC as reference.

I/O 1

I/O 2

I/O 3

I/O 4

VCC

For this configuration, connect pin 5 directly to the

positive supply rail (VCC), the data lines are referenced to

the supply voltage. The internal TVS diode prevents

overvoltage on the supply rail. Biasing of the steering diodes

reduces their capacitance.

Option 2

Protection of four data lines with bias and power supply

isolation resistor.

VCC

10 k

I/O 1

I/O 2

I/O 3

I/O 4

The NUP4201MR6 can be isolated from the power supply

by connecting a series resistor between pin 5 and VCC. A

10 kW resistor is recommended for this application. This

will maintain a bias on the internal TVS and steering diodes,

reducing their capacitance.

Option 3

Protection of four data lines using the internal TVS diode

as reference.

I/O 1

I/O 2

I/O 3

I/O 4

In applications lacking a positive supply reference or

those cases in which a fully isolated power supply is

required, the internal TVS can be used as the reference. For

these applications, pin 5 is not connected. In this

configuration, the steering diodes will conduct whenever the

voltage on the protected line exceeds the working voltage of

the TVS plus one diode drop (Vc = Vf + VTVS).

ESD Protection of Power Supply Lines

When using diodes for data line protection, referencing to

a supply rail provides advantages. Biasing the diodes

reduces their capacitance and minimizes signal distortion.

Implementing this topology with discrete devices does have

disadvantages. This configuration is shown below:

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VCC

Data Line

IESDpos

IESDneg

VF + VCC

−VF

IESDpos

IESDneg

Power

Supply

Protected

Device

Looking at the figure above, it can be seen that when a

positive ESD condition occurs, diode D1 will be forward

biased while diode D2 will be forward biased when a

negative ESD condition occurs. For slower transient

conditions, this system may be approximated as follows:

For positive pulse conditions:

Vc = VCC + VfD1

For negative pulse conditions:

Vc = −VfD2

ESD events can have rise times on the order of some

number of nanoseconds. Under these conditions, the effect

of parasitic inductance must be considered. A pictorial

representation of this is shown below.

VCC

Data Line

IESDpos

IESDneg

VC = VCC + Vf + (L diESD/dt)

IESDpos

IESDneg

Power

Supply

Protected

Device

VC = −Vf − (L diESD/

dt)

An approximation of the clamping voltage for these fast

transients would be:

For positive pulse conditions:

Vc = VCC + Vf + (L diESD/dt)

For negative pulse conditions:

Vc = −Vf – (L diESD/dt)

As shown in the formulas, the clamping voltage (Vc) not

only depends on the Vf of the steering diodes but also on the

L diESD/dt factor. A relatively small trace inductance can

result in hundreds of volts appearing on the supply rail. This

endangers both the power supply and anything attached to

that rail. This highlights the importance of good board

layout. Taking care to minimize the effects of parasitic

inductance will provide significant benefits in transient

immunity.

Even with good board layout, some disadvantages are still

present when discrete diodes are used to suppress ESD

events across datalines and the supply rail. Discrete diodes

with good transient power capability will have larger die and

therefore higher capacitance. This capacitance becomes

problematic as transmission frequencies increase. Reducing

capacitance generally requires reducing die size. These

small die will have higher forward voltage characteristics at

typical ESD transient current levels. This voltage combined

with the smaller die can result in device failure.

The ON Semiconductor NUP4201MR6 was developed to

overcome the disadvantages encountered when using

discrete diodes for ESD protection. This device integrates a

TVS diode within a network of steering diodes.

Figure 9. NUP4201MR6 Equivalent Circuit

During an ESD condition, the ESD current will be driven

to ground through the TVS diode as shown below.

VCC

Data Line

IESDpos

Power

Supply

Protected

Device

The resulting clamping voltage on the protected IC will

be:

Vc = VF + VTVS.

The clamping voltage of the TVS diode is provided in

Figure 8 and depends on the magnitude of the ESD current.

The steering diodes are fast switching devices with unique

forward voltage and low capacitance characteristics.

NUP4201MR6

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TYPICAL APPLICATIONS

UPSTREAM

USB PORT

VBUS

VBUS VBUS

VBUS

DOWNSTREAM

USB PORT

DOWNSTREAM

USB PORT

D−

D+

D−

D+

GND

D−

D+

GND

USB

Controller

NUP2201DT1

NUP4201MR6

Figure 10. ESD Protection for USB Port

Figure 11. Protection for Ethernet 10/100 (Differential mode)

PHY

Ethernet

(10/100)

Coupling

Transformers

NUP4201MR6

RJ45

Connector

N/C N/C

TX+

TX−

RX+

RX−

TX+

TX−

RX+

RX−

GND

VCC

NUP4201MR6

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T1/E1

TRANCEIVER

RTIP

RRING

TRING

TTIP

R2 R3

NUP4201MR6

VCC

Figure 12. TI/E1 Interface Protection

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PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE T

456

0.05 (0.002)

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD

THICKNESS IS THE MINIMUM THICKNESS OF

BASE MATERIAL.

4. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS, OR GATE

BURRS.

DIM

MIN NOM MAX MIN

MILLIMETERS

0.90 1.00 1.10 0.035

INCHES

A1 0.01 0.06 0.10 0.001

b0.25 0.38 0.50 0.010

c0.10 0.18 0.26 0.004

D2.90 3.00 3.10 0.114

E1.30 1.50 1.70 0.051

e0.85 0.95 1.05 0.034

L0.20 0.40 0.60 0.008

0.039 0.043

0.002 0.004

0.014 0.020

0.007 0.010

0.118 0.122

0.059 0.067

0.037 0.041

0.016 0.024

NOM MAX

2.50 2.75 3.00 0.099 0.108 0.118

− −

0°10°0°10°

0.95

0.037

1.9

0.075

0.95

0.037

ǒmm

inchesǓ

SCALE 10:1

1.0

0.039

2.4

0.094

0.7

0.028

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent

rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.

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NUP4201MR6/D

PUBLICATION ORDERING INFORMATION

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USA/Canada

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Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

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For additional information, please contact your local

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