CY25100
Field and Factory-Programmable Spread Spectrum
Clock Generator for EMI Reduction
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document #: 38-07499 Rev. *F Revised November 4, 2008
Features
■
Wide operating output (SSCLK) frequency range
❐
3 MHz to 200 MHz
■
Programmable spread spectrum with nominal 31.5 kHz
modulation frequency
❐
Center spread: ±0.25% to ±2.5%
❐
Down spread: –0.5% to –5.0%
■
Input frequency range
❐
External crystal: 8 to 30 MHz fundamental crystals
❐
External reference: 8 to 166 MHz clock
■
Integrated phase-locked loop (PLL)
■
Field programmable
❐
CY25100SCF and CY25100SIF, 8-pin SOIC
❐
CY25100ZCF and CY25100Z IF, 8-pin TSSOP
■
Programmable crystal load capacitor tuning array
■
Low cycle-to-cycle jitter
■
3.3V opera tion
■
Commercial and industrial operation
■
Spread spectrum on/off function
■
Power down or Outp ut Enable function
Benefits
■
Services most PC peripherals, networking, and consumer
applications.
■
Provides wide range of spread percentages for maximum
electromagnetic interference (EMI) reduction, to meet
regulatory agency electromagnetic compliance (EMC) require-
ments. Reduces development and manufacturing costs and
time-to-market.
■
Eliminates the need for expensive and difficult to use higher
order crystals.
■
Internal PLL to generate up to 200 MHz output. Able to generate
custom frequencies from an external crystal or a driven source.
■
In-house programming of samples and prototype quantities is
available using the CY3672 programmin g kit and
CY3690 (TSSOP) or CY3691 (SOIC) socket adapter.
Production quantities are available through Cypress’s value
added distribution partners or by using third party programmers
from BP Microsystems, HiLo Systems, and others.
■
Enables fine tuning of output clock freque ncy by adjusting
C
Load
of the crystal. Eliminates the need for external C
Load
capacitors.
■
Suitable for most PC, consumer , and networking applications.
■
Application compatibility in standard and low power systems.
■
Ability to enable or disable spread spectrum with an external
pin.
■
Enables low power state or output clocks to High-Z state.
PLL
with
MODULATION
CONTROL
PROGRAMMABLE
CONFIGURATION OUTPUT
DIVIDERS
and
MUX
3
2
4
8
1 5
7
6
VDD VSS
REFCLK
SSCLK
XOUT
XIN
PD# or OE
SSON#
RFB
C
XOUT
C
XIN
Logic Block Diagram
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 2 of 13
Pinouts
Figure 1. CY25100 8-Pin SOIC/TSSOP
General Description
The CY25100 is a S pread Spectrum Clock Generator (SSCG) IC
used to reduce EMI found in today’s high speed digital electronic
systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory or field-programmable configu-
ration memory array to synthesize output frequency, spread
percentage, crystal load capacitor, reference clock output on/off,
spread spectrum on/off function, and PD#/OE options.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range for
center spread is from ±0.25% to ±2.50%. The range for down
spread is from –0.5% to –5.0%. Contact the factory for smaller
or larger spread percentage amounts, if required.
The input to the CY25100 can either be a crystal or a clock
signal. The input frequency range for crystals is 8 to 30 MHz, and
for clock signals is 8 to 166 MHz.
The CY25100 has two clock outputs, REFCLK and SSCLK. The
non spread spectrum REFCLK output has the same frequency
as the input of the CY25100. Th e frequency mod ulated SSCLK
output can be programmed from 3 to 200 MHz.
The CY25100 products are available in 8-pin SOIC and TSSOP
packages with commercial and industrial operating temperature
ranges.
Pin Description
Pin Name Description
1 VDD 3.3V power supply.
2 XOUT Crystal output. Leave this pin floating if external clock is used.
3 XIN/CLKIN Crystal input or reference clock input.
4 PD#/OE Power down pin: Active LOW. If PD# = 0, PLL and Xtal are powered down, and outputs are
weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the
option of choosing either PD# or OE function.
5 VSS Power supply ground.
6 REFCLK Buffered reference output.
7 SSCLK Spread spectrum clock output.
8 SSON# Spread spectrum control. 0 = spread on. 1 = spread off.
4
8
VDD
6
7
VSS
REFCLK
SSON#
1
2
3
XOUT
XIN/CLKIN
PD#/OE
SSCLK
5
Table 1.
Pin Function Input
Frequency Total Xtal
Load
Capacitance Output
Frequency Spread Percent
(0.5% – 5%,
0.25% Intervals) Reference
Output Power down or
Output Enable Frequency
Modulation
Pin Name XIN and XOUT XIN and XOUT SSCLK SSCLK REFOUT PD#/OE SSCLK
Pin# 3 and 2 3 and 2 7 7 6 4 7
Unit MHz pF MHz %On or Off Select PD# or OE kHz
Program Value ENTER DATA ENTER DATA ENTER DATA ENTER DATA ENTER DATA ENTER DATA 31.5
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 3 of 13
Programming Description
Field Programmable CY25100
The CY25100 is programmed at th e package level, that is, in a
programmer socket. The CY251 00 is Flash based, so the parts
can be reprogrammed up to 100 times. This allows fast and easy
design changes and product updates, and eliminates any issues
with old an d ou t-of-date in ventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer with CY3690 (TSSOP) or CY3691
(SOIC) socket adapter.
CyberClocks™ Online Software
CyberClocks™ Online Software is a web based software appli-
cation that allows the user to custom-configure the CY25100. All
the parameters in Table 1 given as “Enter Data” can be
programmed into the CY25100. CyberClocks Online outputs an
industry-standard JEDEC file used for programming the
CY25100. CyberClocks Online is available at www.cyberclock-
sonline.com web site through user registration. To register , fill out
the registration form and make sure to check the “non-standard
devices” box. For more information on the registration process
refer to CY3672 data sheet
For information regarding spread spectrum software
programming solutions, contact your local Cypress sales repre -
sentative or Field Application Engineer (FAE).
CY3672 FTG Programming Kit and CY3690/CY3691
Socket Adapter
The Cypress CY3672 FTG programmer and CY3690 and
CY3691 socket adapters are required to program the CY25100.
The CY3690 enables users to program CY25100ZCF and
CY25100ZIF (TSSOP). CY3691 provides the abili ty to program
CY25100SCF and CY25100SIF (SOIC). Each socket adapter
comes with small prototype quantities of CY25100. The CY3690
and CY3691 is a separate orderable item, so the existing use rs
of the CY3672 FTG development kit or CY3672-PRG
programmer need to order only the socket adapters to prog ram
the CY25100.
Factory Programmable CY25100
Factory programming is availab le for volume manufacturing by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. A
sample request form (refer to “CY25100 Sample Request Form”
at www.cypress.com) must be completed. After the request is
processed, you will receive a new part number, samples, and
data sheet with the programmed values. This part number is
used for additional sample requests and production orders.
Additional information on the CY25100 can be obtained from the
Cypress web site at www.cypress.com.
Product Functions
Input Frequency (XIN, Pin 3 and XOUT, Pin 2)
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signals
is 8 to 166 MHz.
CXIN and CXOUT (Pin 3 and Pin 2)
The load capacitors at Pin 1 (C
XIN
) and Pin 8 (C
XOUT
) can be
programmed from 12 pF to 60 pF with 0.5 pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 t o 60 pF).
The required values of C
XIN
and C
XOUT
are calculated using the
following formula:
C
XIN
= C
XOUT
= 2C
L
– C
P
where C
L
is the crystal load capacitor as specified by the cryst al
manufacturer and C
P
is the parasitic PCB capacitance.
For example, if a fundamental 16 MHz crystal with C
L
of 16 p F is
used and C
P
is 2 pF, C
XIN
and C
XOUT
are calculated as:
C
XIN
= C
XOUT
= (2 x 16) – 2 = 30 pF
If using a driven reference, set C
XIN
and
C
XOUT
to the minimum
value 12 pF.
Output Frequency, SSCLK Output (SSCLK, Pin 7)
The modulated frequency at the SSCLK outp ut is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is the
nominal value of the synthesize d frequency without modulation
(spread percentage = 0). The range of synthesized clock is from
3 to 200 MHz.
Spread Percentage (SSCLK, Pin 7)
The SSCLK spread can be programmed at any percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% down spread.
Reference Output (REFOUT, Pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be programmed
to be enabled (clock on) or disabled (High-Z, clock off). If this
output is not required, it is recommended that users request the
disabled (High-Z, Clock Off) option.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if a
higher modulation frequency is required.
Power Down or Output Enable (PD# or OE, Pin 4)
The part can be programmed to include either PD# or OE
function. PD# funct i on pow ers do wn the o scill ato r a nd PLL. The
OE function disables the outputs.
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 4 of 13
Absolute Maximum Rating
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage ... ................. ... ...............–0.5V to V
DD
+ 0.5
Storage Temperature (Non condensi ng)..... –55°C to +125°C
Junction Temperature................................ –40°C to +125°C
Data Retention at Tj = 125°C ........................... .....> 10 years
Package Power Dissipation......................................350 mW
Static Discharge Voltage................ .. ........................ > 2000V
(per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter Description Comments Min Typ Max Unit
F
NOM
Nominal Crystal Frequency Parallel resonance, fundamental mode, AT cut 8 – 30 MHz
C
LNOM
Nominal Load Capacitance Internal load caps 6 – 30 pF
R
1
Equivalent Series Resistance (ESR) Fundamental mode – – 25 Ω
R
3
/R
1
Ratio of Third Overtone Mode ESR to
Fundamental Mode ESR Ratio used because typical R
1
values are much
less than the maximum spec 3–––
DL Crystal Drive Level No external series resistor assumed – 0.5 2 mW
Operating Conditions
Parameter Description Min Typ Max Unit
V
DD
Supply Voltage 3.13 3.30 3.45 V
T
A
Ambient Commercial Temperatu re 0 – 70 °C
Ambient Industrial Tempera tu re –40 – 85 °C
C
LOAD
Maximum Load Capacitance at Pin 6 and Pin 7 – – 15 pF
F
ref
External Reference Crystal
(Fundamental tuned crystals only) 8–30MHz
External Reference Clock 8 – 166 MHz
F
SSCLK
SSCLK Output Frequency, C
LOAD
= 15 pF 3 – 200 MHz
F
REFCLK
REFCLK Output Frequency, C
LOAD
= 15 pF 8 – 166 MHz
F
MOD
Spread Spectrum Modulation Frequency 30.0 31.5 33.0 kHz
T
PU
Power Up Time for all VDDs to reach minimum specified voltage (power ramp must be
monotonic) 0.05 – 500 ms
DC Electrical Characteristics
Parameter Description Condition Min Typ Max Unit
I
OH
Output High Current V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source) 10 12 mA
I
OL
Output Low Current V
OL
= 0.5, V
DD
= 3.3V (sink) 10 12 mA
V
IH
Input High Voltage CMOS levels, 70% of V
DD
0.7V
DD
–V
DD
V
V
IL
Input Low Voltage CMOS levels, 30% of V
DD
– – 0.3V
D
D
V
I
IH
Input High Current, PD#/OE and
SSON# Pins V
in
= V
DD
––10μA
I
IL
Input Low Current, PD#/OE and SSON#
Pins V
in
= V
SS
––10μA
I
OZ
Output Leakage Current Three-state output, PD#/OE = 0 –10 10 μA
C
XIN
or
C
XOUT[1]
Programmable Capacitance at Pin 2
and Pin 3 Capacitance at minimum setting – 12 – pF
Capacitance at maximum setting – 60 – pF
C
IN[1]
Input Capacitance at Pin 4 and Pin 8 Input pins excludin g X IN an d XOUT – 5 7 pF
Note
1. Guaranteed by characterization , not 100% tested.
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 5 of 13
I
VDD
Supply Current V
DD
= 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
C
LOAD
= 15 pF, PD#/OE = SSON# = V
DD
–2535mA
I
DDS
Standby Cu rrent V
DD
= 3.45V, Device po wered down with
PD# = 0V (driven reference pulled down) –1530μA
DC Electrical Characteristics
(continued)
Parameter Description Condition Min Typ Max Unit
AC Electrical Characteristics
[1]
Parameter Description Condition Min Typ Max Unit
DC Output Duty Cycle SSCLK, Measured at V
DD
/2 45 50 55 %
Output Duty Cycle REFCLK, Measured at V
DD
/2
Duty Cycle of CLKIN = 50% at input bias 40 50 60 %
SR1 Rising Edge Slew Rate SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 20%–80% of V
DD
0.7 1.1 3.6 V/ns
SR2 Falling Edge Slew Rate SSCLK from 3 to 100 MHz; REFCLK from 3 to
100 MHz. 80%–20% of V
DD
0.7 1.1 3.6 V/ns
SR3 Rising Edge Slew Rate SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 20%–80% of V
DD
1.0 1.6 4.0 V/ns
SR4 Falling Edge Slew Rate SSCLK from 100 to 200 MHz; REFCLK from 100
to 166 MHz 80%–20% of V
DD
1.2 1.6 4.0 V/ns
T
CCJ1[2]
Cycle-to-Cycle Jitter
SSCLK (Pin 7) CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK off –90120ps
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK off – 100 130 ps
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK off – 130 170 ps
T
CCJ2[2]
Cycle-to-Cycle Jitter
SSCLK (Pin 7) CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on – 100 130 ps
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on – 105 140 ps
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on – 200 260 ps
T
CCJ3[2]
Cycle-to-Cycle Jitter
REFCLK (Pin 6) CLKIN = SSCLK = 166 MHz, 2% spread,
REFCLK on –80100ps
CLKIN = SSCLK = 66 MHz, 2% spread,
REFCLK on – 100 130 ps
CLKIN = SSCLK = 33 MHz, 2% spread,
REFCLK on – 135 180 ps
t
STP
Power down Time
(pin 4 = PD#) Time from falling edge on PD# to stopped
outputs (Asynchronous) – 150 350 ns
T
OE1
Output Disable Time
(pin 4 = OE) Time from falling edge on OE to stopped outputs
(Asynchronous) – 150 350 ns
T
OE2
Output Enable Time
(pin 4 = OE) Time from rising edge on OE to outputs at a valid
frequency (Asynchronous) – 150 350 ns
t
PU1
Power Up Time,
Crystal is used Time from rising edge on PD# to outputs at valid
frequency (Asynchronous) –3.55ms
t
PU2
Power Up Time,
Reference clock is used Time from rising edge on PD# to outputs at valid
frequency (Asynchronous), reference clock at
correct frequency
–23ms
Note
2. Jitter is configurati on dependent. Act ual jitter is dependen t on XIN ji tter and edge rat e, number of active out put s, output f requencies, spread pe rcentage, temperature ,
and output load.
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 6 of 13
Application Circuit
Figure 2. Application Circuit Diagram
[3, 4, 5]
Switching Waveforms
0.1uF
VDD
1
3
2
45
6
7
8
VDD
XOUT
XIN/CLKIN
PD#/OE VSS
REFCLK
SSCLK
SSON#
Power
CY25100
OUTPUT
Tr
V
DD
0V
Tf
Output Rise time (Tr) = (0.6 x V
DD
)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x V
DD
)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 4. Output Ris e/ Fal l Time (SSCLK and REFCLK)
CLKOUT
V
DD
t
PU
t
STP
V
IL
V
IH
POWER
DOWN 0V
(Asynchronous)
High Impedance
Figure 5. Power Down and Power Up Timing
Notes
3. Because the load capacitors (C
XIN
and C
XOUT
) are provided by the CY25100, no external capacitors are needed on the XIN
and XOUT pins to match the crystal load
capacit o r ( C
L
). Only a single 0.1-μF bypass capacitor is required on the V
DD
pin.
4. If an external clock is used, apply the clock to XI N ( pin 3) and leave XOUT (pin 2) floating (unconnect ed).
5. If SSON# (pin 8) is LOW (V
SS
), the frequency modulation is on at SSCLK pin (pin 7).
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 7 of 13
Switching Waveforms
CLKOUT
V
DD
T
OE1
V
IL
V
IH
OUTPUT
ENABLE 0V
(Asynchronous)
High Impedance
T
OE2
Figure 6. Outp ut Enable/Disable Timing
Informational Graphs
[6]
Spread Spectrum Profile: Fnom=166MH z,
Fmod=30kHz, S p read%= -4%
172.5
171.5
170.5
169.5
168.5
167.5
166.5
165.5
164.5
163.5
162.5
161.5
160.5
159.5
Fnominal
0 20 40 60 80 100 120 140 160 180 200
Time (us)
Sp re ad Sp e c t r um Pro f ile: Fnom=166MHz,
Fmod= 30k Hz, S pread% = +/-1%
0 20 40 60 80 100 12 0 140 160 180 200
Time (us)
Fnominal
169.5
169
168.5
168
167.5
167
166.5
166
165.5
165
164.5
164
163.5
163
162.5
Spread Spect rum Prof ile: Fnom= 66MH z,
Fmod= 30k Hz, S p rea d%= -4%
0 20 40 60 80 100 120 140 160 180 200
Time (us)
Fnominal
68.5
68
67.5
67
66.5
66
65.5
65
64.5
64
63.5
Spread Spectrum Profile: Fnom=66MHz,
Fm o d = 30k Hz, S p re a d%= +/- 1%
0 20 40 60 80 100 120 14 0 160 18 0 200
Time (us)
Fnominal
67.5
67
66.5
66
65.5
65
64.5
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 8 of 13
Informational Graphs
(continued)
[6]
Duty Cycle vs. REFCLK
(CLOAD=15pF)
40
42
44
46
48
50
52
54
56
58
60
0 50 100 150 200
REFCLK (MHz)
Duty Cycle (%)
IDD vs. SSCLK
T emperatu re=25C , VDD=3.3V , CL OA D=15p F, SS of f,
Refc lk = 30 MHz
0
5
10
15
20
25
30
0 50 100 150 200
SSC LK (MHz )
IDD (m A)
Measured Spread% vs. VDD over Temperature
(Target Spread = 0.5%, Fout=100MHz, C
LOAD
=15pF)
0.40%
0.45%
0.50%
0.55%
0.60%
2.7 3 3.3 3.6 3.9
VDD (V)
Spread%
-40C
25C
85C
Measured Spread% vs. VDD over
Temperature
(Target Spread = 5.0%, Fout=100MHz, C
LOAD
=15pF)
4.00%
4.50%
5.00%
5.50%
6.00%
2.7 3 3.3 3.6 3.9
VDD (V)
Spread%
-40C
25C
85C
SSCLK Attenuation vs. VDD over Temperature
(Measured at 7th Harmonic w i th Fnom=100MHz and
Spread=0.5%, C
LOAD
=15pF)
-10
-8
-6
-4
-2
0
2.7 3 3.3 3.6 3.9
VDD (V)
Attenuation (dB)
-40C
25C
85C
SSCLK Attenuation vs. VDD over Temperature
(Measured at 7th Harmoni c with F nom=100MHz and
Spread=5.0%, C
LOAD
=15pF)
-20
-18
-16
-14
-12
-10
2.7 3 3.3 3.6 3.9
VDD (V)
Attenuation (dB)
-40C
25C
85C
Note
6. The Informational Gr aphs are mea nt to convey t he t ypical perform a nce level s. No perf orma nce specifications is i mplied or g uara nte ed. Ref er to the t ab les on pages
4 and 5 for device specifications.
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 9 of 13
Informational Graphs
(continued)
[6]
SSCLK EMI Attenuation vs. Spread%
(Measured at 7th Harmonic T emp=25C, VDD=3.3V,
SSCLK=100MHz, Measured on Cypress
Characterization board with CLOAD=15pF)
-16
-14
-12
-10
-8
-6
-4
-2
0
0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% 4.0% 4.5% 5.0%
Spread %
Attenuation (dB)
Max Cycle-Cycle Jitter on SSCLK vs.
Temperature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/-
2%spread, REFCLK off)
0
25
50
75
100
125
150
175
200
-40 -20 0 20 40 60 80 100
Temperature (deg C)
Jitter (ps)
[+] Feedback
CY25100
Document #: 38-07499 Rev. *F Page 10 of 13
Ordering Information
Part Number Package Description Product Flow
Pb-Free
CY25100SXCF 8-Pin Small Outline Integrated Circuit (SOIC) Commercial, 0 to 70°C
CY25100SXIF 8-Pin Small Outline Integrated Circuit (SOIC) Industrial, –40 to 85°C
CY25100ZXCF 8-Pin Thin Shrunk Small Outline Package (TSSOP) Commercial, 0 to 70°C
CY25100ZXIF 8-Pin Thin Shrunk Small Outline Package (TSSOP) Industrial, –40 to 85°C
CY25100SXC-xxxw
[7]
8-Pin Small Outline Integrated Circu it (SOIC) Commercial, 0 to 70°C
CY25100SXC-xxxwT
[7]
8-Pin Small Outline Integrated Circu it (SOIC) - Tape and Reel Commercial, 0 to 70°C
CY25100SXI-xxxw
[7]
8-Pin Small Outline Integrated Circ uit (SOIC) Industrial, –40 to 85°C
CY25100SXI-xxxwT
[7]
8-Pin Small Outline Integrated Circu it (SOIC) -Tape and Reel Industrial, –40 to 85°C
CY25100ZXC-xxxw
[7]
8-Pin Thin Shrunk Small Outline Package (TSSOP) Commercial, 0 to 70°C
CY25100ZXC-xxxwT
[7]
8-Pin Thin Shrunk Small Outline Package (TSSOP) - Tape and Reel Commercial, 0 to 70°C
CY25100ZXI-xxxw
[7]
8-Pin Thin Shrunk Small Outline Package (TSSOP) Industrial, –40 to 85°C
CY25100ZXI-xxxwT
[7]
8-Pin Thin Shrunk Small Outline Package (TSSOP) -Tape and Reel Industrial, –40 to 85°C
CY3672-USB FTG Programmer, for part numbers ending in “F” n/a
CY3690 CY25100ZXCF/IF Socket Adapter (TSSOP) for use with CY3672-USB n/a
CY3691 CY25100SXCF/IF Socket Adapter (SOIC) for use with CY3672-USB n/a
Package Diagrams
SEATING PLANE
PIN1ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0°~8°
0.016[0.406]
0.010[0.254] X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
8 Lead (150 Mil) SOIC - S08
14
58
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066-*C
Figure 6. 8-Pin (150-Mil) SOIC S8
Notes
7. “xxx” denotes the assigned product dash number. “w” denotes the different programmed frequency and spread percentage options.
8. Not recommended for new designs.
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CY25100
Document #: 38-07499 Rev. *F Page 11 of 13
Package Diagrams
(continued)
8
PIN1ID
SEATING
PLANE
1
BSC.
BSC
0°-8°
PLANE
GAUGE
2.90[0.114]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
6.50[0.256]
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
3.10[0.122]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
0.25[0.010]
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
DIMENSIONS IN MM[INCHES] MIN.
MAX.
51-85093-*A
Figure 7. 8-Pin Thin Shrunk Small Outline Package (4.40 mm Body) Z8
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CY25100
Document #: 38-07499 Rev. *F Page 12 of 13
Document History Page
Document Title: CY25100 Field and Fac tory Programmable Spread Spectrum Clock Generator for EMI Reduc tion
Document Number: 38-07499
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 126578 CKN 06/27/03 Ne w Data Sheet
*A 128753 IJATMP 0 8/29/03 Changes to reflect field programmability
*B 130342 RGL 12/02/03 Changes to Application Circuit diagram and correction to the package
description listed under the Ordering Information table for CY3690 and
CY3691.
*C 204121 RGL See ECN Add Industrial Temperature Range
Corrected the Ordering Information to match the DevMaster
*D 215392 RGL See ECN Added Lead Free devices
*E 2513909 AESA 06/10/08 Updated template. Added Note “Not recommended for new designs.”
Added part number CY25100KSXCF, CY25100KSXIF, CY25100KSXI-xxx,
CY25100KZXC-xxx, CY25100KZXI-xxx, CY25100KSXI-xxxT,
CY25100KZXC-xxxT, CY25100KZXI-xxxT, and CY25100KZXIF in ordering
information table.
Added Pb-Free header in the ordering information table.
Removed Pb-Free from Package description in the ordering information table.
Changed CY3672-PRG with CY3672-USB in the ordering informatio n table.
Removed CY25100SCF, CY251 00SIF, CY25100ZCF, CY25100ZIF, and
CY3672 in the ordering information table.
Changed Lead free to Pb-Free.
*F 2601881 KVM/PYRS 1 1/06/08 Rising edge slew rate (SR3) minimum limit changed from 1.2V/ns to 1.0V/ns.
Removed part numbers added in rev *E.
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Document #: 38-07499 Rev. *F Revised November 4, 2008 Page 13 of 13
CyberClocks is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
CY25100
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