AT24C04B-W1827BF - Atmel Corporation

1. Features

•Medium-voltage and Standard-voltage Operation

– 2.5 (VCC = 2.5V to 5.5V)

•Automotive Temperature Range –40°C to 125°C

•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K) or 1024 x 8 (8K)

•Two-wire Serial Interface

•Schmitt Trigger, Filtered Inputs for Noise Suppression

•Bidirectional Data Transfer Protocol

•400 kHz (2.5V) Compatibility

•Write Protect Pin for Hardware Data Protection

•8-byte Page (1K, 2K) or 16-byte Page (4K, 8K) Write Modes

•Partial Page Writes are Allowed

•Self-timed Write Cycle (5 ms max)

•High-reliability

– Endurance: 1 Million Write Cycles

– Data Retention: 100 Years

•8-lead JEDEC SOIC and 8-lead TSSOP Packages

2. Description

The AT24C01B/02B/04B/08B provides 1024/2048/4096/8192 bits of serial electrically

erasable and programmable read-only memory (EEPROM) organized as

128/256/512/1024 words of 8 bits each. The device is optimized for use in many auto-

motive applications where low-power and low-voltage operation are essential. The

AT24C01B/02B/04B/08B is available in space-saving 8-lead JEDEC SOIC and 8-lead

TSSOP packages and is accessed via a two-wire serial interface. In addition, the

entire family is available in 2.5V (2.5V to 5.5V) versions.

Table 2-1. Pin Configurations

Pin Name Function

A0 − A2 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

Two-wire

Automotive

Temperature

Serial EEPROM

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

8K (1024 x 8)

AT24C01B

AT24C02B

AT24C04B

AT24C08B

8517C–SEEPR–01/09

8-lead SOIC

GND

VCC

SCL

SDA

8-lead TSSOP

GND

VCC

SCL

SDA

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AT24C01B/02B/04B/08B

Figure 3-1. Block Diagram

3. Absolute Maximum Ratings

Operating Temperature...........................−55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature..............................−65°C to +150°C

Voltage on Any Pin

with Respect to Ground..................................−1.0V to +7.0V

Maximum Operating Voltage..........................................6.25V

DC Output Current........................................................5.0 mA

STA R T

STOP

LOGIC

VCC

GND

SCL

SDA

SERIAL

CONTROL

LOGIC

EN H.V. PUMP/TIMING

EEPROM

DATA RECOVERY

SERIAL MUX

X DEC

DOUT/ACK

LOGIC

COMP

LOAD INC

DATA WORD

ADDR/COUNTER

Y DEC

R/W

DOUT

DIN

LOAD

DEVICE

ADDRESS

COMPARATOR

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

4. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM

device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-

drain driven and may be wire-ORed with any number of other open-drain or open-collector

devices.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs

that are hard wired for the AT24C01B/02B/04B. As many as eight 1K/2K devices may be

addressed on a single bus system (device addressing is discussed in detail under the Device

Addressing section). The AT24C04B uses the A2 and A1 inputs for hardwire addressing and a

total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect.

The AT24C08B only uses the A2 input for hardwire addressing and a total of two 8K devices

may be addressed on a single bus system. The A0 and A1 pins are no connect.

WRITE PROTECT (WP): The AT24C01B/02B/04B/08B has a Write Protect pin that provides

hardware data protection. The Write Protect pin allows normal read/write operations when con-

nected to ground (GND). When the Write Protect pin is connected to VCC, the write protection

feature is enabled and operates as shown in the following table.

5. Memory Organization

AT24C01B, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each, the 1K

requires a 7-bit data word address for random word addressing.

AT24C02B, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K

requires an 8-bit data word address for random word addressing.

AT24C04B, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K

requires a 9-bit data word address for random word addressing.

AT24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K

requires a 10-bit data word address for random word addressing.

Table 4-1. Write Protect

WP Pin

Status

Part of the Array Protected

AT24C01B/02B/04B/08B

At VCC Full Array

At GND Normal Read/Write Operations

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AT24C01B/02B/04B/08B

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Table 5-1. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 400 KHz, VCC = +2.5V

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V

Table 5-2. DC Characteristics

Applicable over recommended operating range from: TA = −40°C to +125°C, VCC = +2.5V to +5.5V (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 2.5 5.5 V

ICC Supply Current VCC = 5.0V Read at 100 kHz 0.4 1.0 mA

ICC Supply Current VCC = 5.0V Write at 100 kHz 2.0 3.0 mA

ISB1 Standby Current VCC = 2.5V VIN = VCC or VSS 1.6 4.0 µA

ISB2 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) −0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL Output Low Level VCC = 2.5V IOL = 3.0 mA 0.4 V

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).

2. This parameter is characterized only.

Table 5-3. AC Characteristics

Applicable over recommended operating range from TA = −40°C to +125°C, VCC = +2.5V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted)

Symbol Parameter Min Max Units

fSCL Clock Frequency, SCL 400 kHz

tLOW Clock Pulse Width Low 1.2 µs

tHIGH Clock Pulse Width High 0.6 µs

tINoise Suppression Time(1) 50 ns

tAA Clock Low to Data Out Valid 0.1 0.9 µs

tBUF

Time the bus must be free before

a new transmission can start(2) 1.2 µs

tHD.STA Start Hold Time 0.6 µs

tSU.STA Start Set-up Time 0.6 µs

tHD.DAT Data In Hold Time 0 µs

tSU.DAT Data In Set-up Time 100 ns

tRInputs Rise Time(2) 300 ns

tFInputs Fall Time(2) 300 ns

tSU.STO Stop Set-up Time 0.6 µs

tDH Data Out Hold Time 50 ns

tWR Write Cycle Time 5 ms

Endurance(2) 5.0V, 25°C, Page Mode 1M Write Cycles

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AT24C01B/02B/04B/08B

6. Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.

Data on the SDA pin may change only during SCL low time periods (see Figure 8-2 on page 8).

Data changes during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which

must precede any other command (see Figure 8-3 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a

read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-

ure 8-3 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the

EEPROM in 8-bit words. The EEPROM sends a “0” to acknowledge that it has received each

word. This happens during the ninth clock cycle.

STANDBY MODE: The AT24C01B/02B/04B/08B features a low-power standby mode which is

enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any

internal operations.

2-WIRE SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any

2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b)

clock 9 cycles, (c) create another start but followed by stop bit condition as shown below. The

device is ready for next communication after above steps have been completed.

Figure 6-1. Software Reset

Start bit Stop bitStart bitDummy Clock Cycles

SCL

SDA

12389

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AT24C01B/02B/04B/08B

7. Bus Timing

Figure 7-1. SCL: Serial Clock, SDA: Serial Data I/O

8. Write Cycle Timing

Figure 8-1. SCL: Serial Clock, SDA: Serial Data I/O

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

SCL

SDA IN

SDA OUT

tHIGH

tLOW tLOW

tAA tDH tBUF

tSU.STO

tSU.DAT

tHD.DAT

tHD.STA

tSU.STA

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

Figure 8-2. Data Validity

Figure 8-3. Start and Stop Definition

Figure 8-4. Output Acknowledge

SDA

SCL

DATA STABLE DATA STABLE

DATA

CHANGE

SDA

SCL

STA RT STOP

SCL

DATA IN

DATA OUT

START ACKNOWLEDGE

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

9. Device Addressing

The 1K/2K/4K/8K EEPROM device requires an 8-bit device address word following a start con-

dition to enable the chip for a read or write operation (see Figure 11-1 on page 10).

The device address word consists of a mandatory “1”, “0” sequence for the first four most signif-

icant bits as shown. This is common to all the Serial EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits

must compare to their corresponding hardwired input pins.

The 4K EEPROM only uses the A2 and A1 device address bits with the A0 bit being a memory

address bit (P0) (see Figure 11-1 on page 10). The two device address bits must compare to

their corresponding hardwired input pins. The A0 pin is no connect.

The 8K EEPROM only uses the A2 device address bit with the next two bits (P9, P0) being for

memory page addressing (See Figure 11-1 on page 10). The A2 bit must compare to its corre-

sponding hardwired input pin. The A1 and A0 pins are no connect.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made,

the chip will return to a standby state.

10. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must

terminate the write sequence with a stop condition. At this time the EEPROM enters an internally

timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle

and the EEPROM will not respond until the write is complete (see Figure 11-2 on page 11).

PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write. The 4K/8K devices are

capable of 16-byte page writes.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K/

8K) more data words. The EEPROM will respond with a “0” after each data word received. The

microcontroller must terminate the page write sequence with a stop condition (see Figure 11-3

on page 11).

The data word address lower three (1K/2K) or four (4K/8K) bits are internally incremented fol-

lowing the receipt of each data word. The higher data word address bits are not incremented,

retaining the memory page row location. When the word address, internally generated, reaches

the page boundary, the following byte is placed at the beginning of the same page. If more than

eight (1K/2K) or sixteen (4K/8K) data words are transmitted to the EEPROM, the data word

address will “roll over” and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

operation desired. Only if the internal write cycle has completed will the EEPROM respond with

a “0”, allowing the read or write sequence to continue.

11. Read Operations

Read operations are initiated the same way as write operations with the exception that the

read/write select bit in the device address word is set to “1”. There are three read operations:

current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the last

address accessed during the last read or write operation, incremented by one. This address

stays valid between operations as long as the chip power is maintained. The address “roll over”

during read is from the last byte of the last memory page to the first byte of the first page. The

address “roll over” during write is from the last byte of the current page to the first byte of the

same page.

Once the device address with the read/write select bit set to “1” is clocked in and acknowledged

by the EEPROM, the current address data word is serially clocked out. The microcontroller does

not respond with an input “0” but does generate a following stop condition (see Figure 11-4 on

page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data

word address. Once the device address word and data word address are clocked in and

acknowledged by the EEPROM, the microcontroller must generate another start condition. The

microcontroller now initiates a current address read by sending a device address with the

read/write select bit high. The EEPROM acknowledges the device address and serially clocks

out the data word. The microcontroller does not respond with a “0” but does generate a following

stop condition (see Figure 11-5 on page 11).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-

dom address read. After the microcontroller receives a data word, it responds with an

acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment

the data word address and serially clock out sequential data words. When the memory address

limit is reached, the data word address will “roll over” and the sequential read will continue. The

sequential read operation is terminated when the microcontroller does not respond with a “0” but

does generate a following stop condition (see Figure 11-6 on page 12).

Figure 11-1. Device Address

MSB

1K/2K 1 0 1 0 A2 A1 A0

R/W

4K 1 0 1 0 A2 A1 P0

R/W

8K 1 0 1 0 A2 P1 P0

R/W

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

Figure 11-2. Byte Write

(* = DON’T CARE bit for 1K)

Figure 11-3. Page Write

(* = DON’T CARE bit for 1K)

Figure 11-4. Current Address Read

Figure 11-5. Random Read

( = Don’t care bit for 1K)

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AT24C01B/02B/04B/08B

Figure 11-6. Sequential Read

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AT24C01B/02B/04B/08B

Notes: 1. “-B” denotes bulk.

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.

12. AT24C01B Ordering Information

Ordering Code Package Operation Range

AT24C01BN-SP25-B(1)

AT24C01BN-SP25-T(2)

AT24C01B-TP25-B(1)

AT24C01B-TP25-T(2)

8S1

8A2

Lead-free/Halogen-free/NiPdAu Lead

Finish/Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

−2.5 Low-voltage (2.5V to 5.5V)

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

13. AT24C02B Ordering Information

Notes: 1. “-B” denotes bulk.

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.

Ordering Code Package Operation Range

AT24C02BN-SP25-B(1)

AT24C02BN-SP25-T(2)

AT24C02B-TP25-B(1)

AT24C02B-TP25-T(2)

8S1

8A2

Lead-free/Halogen-free/NiPdAu Lead

Finish/Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

−2.5 Low-voltage (2.5V to 5.5V)

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

Notes: 1. “-B” denotes bulk.

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.

14. AT24C04B Ordering Information

Ordering Code Package Operation Range

AT24C04BN-SP25-B(1)

AT24C04BN-SP25-T(2)

AT24C04B-TP25-B(1)

AT24C04B-TP25-T(2)

8S1

8A2

Lead-free/Halogen-free/NiPdAu Lead

Finish/Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

−2.5 Low-voltage (2.5V to 5.5V)

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

Notes: 1. “-B” denotes bulk.

2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.

15. AT24C08B Ordering Information

Ordering Code Package Operation Range

AT24C08BN-SP25-B(1)

AT24C08BN-SP25-T(2)

AT24C08B-TP25-B(1)

AT24C08B-TP25-T(2)

8S1

8A2

Lead-free/Halogen-free/NiPdAu Lead

Finish/Automotive Temperature

(−40°C to 125°C)

Package Type

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

Options

−2.5 Low-voltage (2.5V to 5.5V)

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

16. Packaging Information

16.1 8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

16.2 8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 B

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0˚ – 8˚

∅

Top View

End View

Side View

8517C–SEEPR–01/09

AT24C01B/02B/04B/08B

17. Revision History

Doc. Rev. Date Comments

8517C 1/2009 Removed Preliminary status.

8517B 3/2008 Added data for 8K device.

8517A 1/2008 Initial document release.

8517C–SEEPR–01/09

Headquarters International

Atmel Corporation

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USA

Tel: 1(408) 441-0311

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Tel: (33) 1-30-60-70-00

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Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Product Contact

Web Site

www.atmel.com

Technical Support

s_eeprom@atmel.com

Sales Contact

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

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