1
FEATURES
DESCRIPTION/ORDERING INFORMATION
TS12A4516 , , TS12A4517
www.ti.com
................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009
DUAL SUPPLY, LOW ON-STATE RESISTANCE SPST CMOS ANALOG SWITCHES
•± 1-V to ± 6-V Dual-Supply Operation •Specified Low ON-Leakage Currents:•Specified ON-State Resistance: – 5 nA at 25 ° C– 25 ΩMax With ± 5-V Supply – 10 nA at 85 ° C– 35 ΩMax With ± 3.3-V Supply •Low Charge Injection: 13 pC ( ± 5-V Supply)– 47 ΩMax With ± 1.8-V Supply •Fast Switching Speed:t
ON
= 85 ns, t
OFF
= 50 ns ( ± 5-V Supply)•Specified Low OFF-Leakage Currents:
•Break-Before-Make Operation (t
ON
> t
OFF
)– 5 nA at 25 ° C
•Latch-Up Performance Exceeds 100 mA Per– 10 nA at 85 ° C
JESD 78, Class II•ESD Performance Tested Per JESD 22– 2500-V Human-Body Model (A114-F)– 1000-V Charged-Device Model (C101-C)– 250-V Machine Model (A115-A)
The TS12A4516/TS12A4517 are single pole/single throw (SPST), low-voltage, dual-supply CMOS analogswitches, with very low switch ON-state resistance. The TS12A4516 is normally open (NO). The TS12A4517 isnormally closed (NC).
These CMOS switches can operate continuously with a dual supplies between ± 1 V and ± 6 V [(2 V < (V
+
– V
–
) <12 V]. Each switch can handle rail-to-rail analog signals. The OFF-leakage current maximum is only 5 nA at 25 ° Cor 10 nA at 85 ° C.
For pin-compatible parts for use with single supply, see the TS12A4514/TS12A4515.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Reel of 1500 TS12A4516DSOIC – D YD516Reel of 2500 TS12A4516DRSOP (SOT-23) – DBV Reel of 3000 TS12A4516DBVR 9CL_– 40 ° C to 85 ° C
Reel of 1500 TS12A4517DSOIC – D YD517Reel of 2500 TS12A4517DRSOP (SOT-23) – DBV Reel of 3000 TS12A4517DBVR 9CM_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
PIN CONFIGURATIONS
N.C. = Not internally connected
NC = Normally closed
NO = Normally open
TS12A4516
D PACKAGE
(TOP VIEW)
COM
N.C.
N.C.
V+
1
2
3
4
NO
V–
IN
N.C.
8
7
6
5
TS12A4517
(TOP VIEW)
D PACKAGE
COM
N.C.
N.C.
V+
1
2
3
4
NC
V–
IN
N.C.
8
7
6
5
INPUT SWITCH STATE
TS12A4516 TS12A4517
ON
ON
OFF
OFFLOW
HIGH
TS12A4516
DBV PACKAGE
(TOP VIEW)
COM 1
NO 2
V–3
V+
5
IN
4
TS12A4517
DBV PACKAGE
(TOP VIEW)
COM 1
NC
2
V–3
V+
5
IN
4
Absolute Minimum and Maximum Ratings
(1) (2)
TS12A4516 , , TS12A4517
SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 .................................................................................................................................................
www.ti.com
voltages referenced to 0 V
MIN MAX UNIT
V
+
Supply voltage range – 0.3 13 VV
NC
V
NO
Analog voltage range
(3)
V
–
– 0.3 V
+
+ 0.3 VV
COM
V
IN
Logic input range V
–
– 0.3 V
+
+ 0.3 VContinuous current into any terminal ± 20 mAPeak current, NO or COM (pulsed at 1 ms, 10% duty cycle) ± 30 mAESD per method 3015.7 > 2000 V8-pin SOIC (derate 5.88 mW/ ° C above 70 ° C) 471Continuous power dissipation (T
A
= 70 ° C) mW5-pin SOT23-5 (derate 7.1 mW/ ° C above 70 ° C) 571T
A
Operating temperature range – 40 85 ° CT
stg
Storage temperature range – 65 150 ° CLead temperature (soldering, 10 s) 300 ° C
(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum(3) Voltages exceeding V
+
or GND on any signal terminal are clamped by internal diodes. Limit forward-diode current to maximum currentrating.
2Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TS12A4516 TS12A4517
Electrical Characteristics for ± 5-V Supply
(1)
TS12A4516 , , TS12A4517
www.ti.com
................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009
V
+
= 4.5 V to 5.5 V, V
–
= – 4.5 V to – 5.5 V, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
V
–
V
+
VV
+
= 4.5 V, V
–
= – 4.5 V, 25 ° C 12 20ON-state resistance r
on
V
COM
= 3.5 V, ΩFull 25I
COM
= 20 mAV
+
= 4.5 V, V
–
= – 4.5 V, 25 ° C 1.2 2.5ON-state resistance
r
on(flat)
V
COM
= – 3.5 V, 0 V, 3.5 V, Ωflatness
Full 3I
COM
= 20 mAV
+
= 5.5 V, V
–
= – 5.5 V, 25 ° C 5NO, NC I
NO(OFF)
,
V
COM
= 4.5 V, nAOFF leakage current
(3)
I
NC(OFF)
Full 10V
NO
or V
NC
= – 4.5 VV
+
= 5.5 V, V
–
= – 5.5 V, 25 ° C 5COM
I
COM(OFF)
V
COM
= – 4.5 V, nAOFF leakage current
(3)
Full 10V
NO
or V
NC
= 4.5 VV
+
= 5.5 V, V
–
= – 5.5 V, 25 ° C 5COM
I
COM(ON)
V
COM
= 5.5 V, nAON leakage current
(3)
Full 10V
NO
or V
NC
= open
Digital Control Input (IN)
Input logic high V
IH
Full V
+
– 1.5 VInput logic low V
IL
Full V
–
V
+
– 3.5 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.010 µA
Dynamic
25 ° C 58 75Turn-on time t
ON
See Figure 2 nsFull 8525 ° C 28 45Turn-off time t
OFF
See Figure 2 nsFull 50C
L
= 1 nF, V
NO
= 0 V,Charge injection
(4)
Q
C
25 ° C – 13 pCR
S
= 0 Ω, See Figure 1NO, NC C
NO(OFF)
,
f = 1 MHz, See Figure 4 25 ° C 5.5 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 4 25 ° C 5.5 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 4 25 ° C 16 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 1.5 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 464 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 83 dBV
NO
= 1 V
RMS
, f = 1 MHzR
L
= 600 Ω, C
L
= 15 pF,Total harmonic distortion THD 25 ° C 0.07 %V
NO
= 1 V
RMS
, f = 20 kHz
Supply
25 ° C 70V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 8025 ° C – 70V
–
supply current I
–
V
IN
= 0 V or V
+
µAFull – 80
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(4) Specified by design, not production tested
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3
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Electrical Characteristics for ± 3.3-V Supply
(1)
TS12A4516 , , TS12A4517
SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 .................................................................................................................................................
www.ti.com
V
+
= 3.0 V to 3.6 V, V
–
= – 3.0 V to – 3.6, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
V
–
V
+
VV
+
= 3.0 V, V
–
= – 3.0 V, 25 ° C 17 25ON-state resistance r
on
V
COM
= 3 V, ΩFull 35I
COM
= 20 mA
25 ° C 1.5 3ON-state resistance V
COM
= – 2 V, 0 V, 2 V,r
on(flat)
Ωflatness I
COM
= 20 mA
Full 4V
+
= 3.6 V, V
–
= – 3.6 V, 25 ° C 5NO, NC I
NO(OFF),
V
COM
= 3 V, nAOFF leakage current
(3)
I
NC(OFF)
Full 10V
NO
or V
NC
= – 3 VV
+
= 3.6 V, V
–
= – 3.6 V, 25 ° C 5COM
I
COM(OFF)
V
COM
= – 3 V, nAOFF leakage current
(3)
Full 10V
NO
or V
NC
= 3 VV
+
= 3.6 V, V
–
= – 3.6 V, 25 ° C 5COM
I
COM(ON)
V
COM
= 3.6 V, nAON leakage current
(3)
Full 10V
NO
or V
NC
= open
Digital Control Input (IN)
Input logic high V
IH
Full V
+
– 1.5 VInput logic low V
IL
Full V
–
V
+
– 3.5 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.01 µA
Dynamic
25 ° C 65 85Turn-on time t
ON
see Figure 2 nsFull 9525 ° C 37 60Turn-off time t
OFF
see Figure 2 nsFull 70C
L
= 1 nF, V
NO
= 0 V,Charge injection
(4)
Q
C
25 ° C – 7.5 pCR
S
= 0 Ω, See Figure 1NO, NC C
NO(OFF)
f = 1 MHz, See Figure 4 25 ° C 5.5 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 4 25 ° C 5.5 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 4 25 ° C 16 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 1.5 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 464 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 83 dBV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 600 Ω, C
L
= 15 pF,Total harmonic distortion THD 25 ° C 0.10 %V
NO
= 1 V
RMS
, f = 20 kHz
Supply
25 ° C 40V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 4525 ° C – 40V
–
supply current I
–
V
IN
= 0 V or V
+
µAFull 45
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(4) Specified by design, not production tested
4Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TS12A4516 TS12A4517
Electrical Characteristics for ± 1.8-V Supply
(1)
TS12A4516 , , TS12A4517
www.ti.com
................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009
V
+
= 1.65 V to 1.95 V, V
–
= – 1.65 V to – 1.95 V, T
A
= – 40 ° C to 85 ° C (unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS T
A
MIN TYP
(2)
MAX UNIT
Analog Switch
Analog signal range V
COM
, V
NO
, V
NC
V
–
V
+
VV
+
= 1.65 V, V
–
= – 1.65 V, 25 ° C 28 40ON-state resistance r
on
V
COM
= 0 V, ΩFull 47I
COM
= 20 mAV
+
= 1.65 V, V
–
= – 1.65 V, 25 ° C 9 13ON-state resistance
r
on(flat)
V
COM
= – 1.8 V, 0 V, 1.5 V, Ωflatness
Full 15I
COM
= 20 mAV
+
= 1.95 V, V
–
= – 1.95 V, 25 ° C 5NO, NC I
NO(OFF),
V
COM
= 1.65 V, nAOFF leakage current
(3)
I
NC(OFF)
Full 10V
NO
or V
NC
= – 1.65 VV
+
= 1.95 V, V
–
= – 1.95 V, 25 ° C 5COM
I
COM(OFF)
V
COM
= – 1.65 V, nAOFF leakage current
(3)
Full 10V
NO
or V
NC
= 1.65 VV
+
= 1.95 V, V
–
= – 1.95 V, 25 ° C 5COM
I
COM(ON)
V
COM
= 1.95 V, nAON leakage current
(3)
Full 10V
NO
or V
NC
= open
Digital Control Input (IN)
Input logic high V
IH
Full V
+
– 1.5 VInput logic low V
IL
Full V
–
V
+
– 3.5 VInput leakage current I
IH
, I
IL
V
IN
= V
+
, 0 V Full 0.01 µA
Dynamic
25 ° C 90 120Turn-on time
(4)
t
ON
See Figure 2 nsFull 15025 ° C 95 150Turn-off time
(4)
t
OFF
See Figure 2 nsFull 200Charge injection
(4)
Q
C
C
L
= 1 nF, See Figure 1 25 ° C – 3.5 pCNO, NC C
NO(OFF)
,
f = 1 MHz, See Figure 4 25 ° C 6 pFOFF capacitance C
NC(OFF)
COM
C
COM(OFF)
f = 1 MHz, See Figure 4 25 ° C 6 pFOFF capacitance
COM
C
COM(ON)
f = 1 MHz, See Figure 4 25 ° C 14.5 pFON capacitance
Digital input capacitance C
I
V
IN
= V
+
, 0 V 25 ° C 1.5 pFR
L
= 50 Ω, C
L
= 15 pF,Bandwidth BW 25 ° C 464 MHzV
NO
= 1 V
RMS
, f = 100 kHzR
L
= 50 Ω, C
L
= 15 pF,OFF isolation O
ISO
25 ° C – 83 dBV
NO
= 1 V
RMS
, f = 1 MHzR
L
= 600 Ω, C
L
= 50 pF,Total harmonic distortion THD 25 ° C 0.37 %V
NO
= 1 V
RMS
, f = 20 kHz
Supply
25 ° C 20V
+
supply current I
+
V
IN
= 0 V or V
+
µAFull 3025 ° C – 20V
–
supply current I
–
V
IN
= 0 V or V
+
µAFull – 30
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.(2) Typical values are at T
A
= 25 ° C.(3) Leakage parameters are 100% tested at maximum-rated hot operating temperature, and are ensured by correlation at 25 ° C.(4) Specified by design, not production tested
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TS12A4516 TS12A4517
TS12A4516 , , TS12A4517
SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 .................................................................................................................................................
www.ti.com
PIN DESCRIPTION
(1)
PIN NO.
TS12A4516 TS12A4517 NAME DESCRIPTION
D, P SOT23-5 D, P SOT23-5
1 1 1 1 COM Common2, 3, 5 – 2, 3, 5 – N.C. No connect (not internally connected)4 5 4 5 V
+
Positive power supply6 4 6 4 IN Digital control to connect COM to NO or NC7 3 7 3 V
–
Negative power supply8 2 – – NO Normally open– – 8 2 NC Normally closed
(1) NO, NC, and COM pins are identical and interchangeable. Any may be considered as an input or an output; signals pass in bothdirections.
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Product Folder Link(s): TS12A4516 TS12A4517
APPLICATION INFORMATION
Power-Supply Considerations
Logic-Level Thresholds
Test Circuits/Timing Diagrams
NO
orNC
TS12A4516 , , TS12A4517
www.ti.com
................................................................................................................................................. SCDS236B – DECEMBER 2006 – REVISED APRIL 2009
The TS12A4516 and TS12A4517 operate with power-supply voltages from ± 1 V to ± 6 V [(2 V < (V
+
– V
–
) < 12 V],but are tested and specified at ± 5V, ± 3.3V, and ± 1.8V supplies. The pin-compatible TS12A4514 and TS12A4515are recommended for use when only a single supply is desirable.
The TS12A4516 and TS12A4517 construction is typical of most CMOS analog switches, except that they haveonly two supply pins: V
+
and V
–
. V
+
and V
–
drive the internal CMOS switches and set their analog voltage limits.Reverse ESD-protection diodes are internally connected between each analog-signal pin and both V
+
and V
–
.One of these diodes conducts if any analog signal exceeds V
+
or V
–
.
Virtually all the analog leakage current comes from the ESD diodes to V
+
or V
–
. Although the ESD diodes on agiven signal pin are identical and, therefore, fairly well balanced, they are reverse biased differently. Each isbiased by either V
+
or V
–
and the analog signal. This means their leakages will vary as the signal varies. Thedifference in the two diode leakages to the V
+
and V
–
pins constitutes the analog-signal-path leakage current. Allanalog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal.This is why both sides of a given switch can show leakage currents of the same or opposite polarity.
V
+
and V
–
also power the internal logic and logic-level translators. The logic-level translators convert the logiclevels to switched V
+
and V
–
signals to drive the analog signal gates.
Since these parts have no ground pin, the logic-level threshold is referenced to V
+
. The threshold limits are V
+– 1.5 V and V
+
– 3.5 V for V
+
levels between 6 V and 3 V. When V
+
= 2 V, the logic threshold is approximately 0.6V.
CAUTION:
Do not connect the TS12A4516/TS12A4517 V
+
to 3 V and then connect thelogic-level pins to logic-level signals that operate from 5-V supply. TTL levelscan exceed 3 V and violate the absolute maximum ratings, damaging the partand/or external circuits.
Figure 1. Charge Injection
Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TS12A4516 TS12A4517
50%
tOFF
tON
VIN 0 V
IN
NO
COM
50 Ω
TS12A4516
300 Ω35 pF
90% 90%
0 V
50%
tON
tOFF
VIN 0 V
IN
NC
COM
50 Ω300 Ω35 pF
90% 90%
0 V
TS12A4517
VNOPEAK
VNOPEAK
VNO
VOUT
VIN
VNO
VOUT
VIN
V+
V+
V+
V+
V+
V+
VOUT
VOUT
V–
V–
Measurements are standardized against short at socket
terminals. OFF isolation is measured between COM and OFF
terminals on each switch. ON loss is measured between COM
and ON terminals on each switch. Signal direction through
switch is reversed; worst values are recorded.
VOUT
IN
NO
COM
VIN
TS12A4516
OFF Isolation = 20log VOUT
VIN
ON Loss = 20log VOUT
VIN
50 Ω
50 Ω50 Ω
50 Ω
MEAS REF
10 nF
TS12A4517
V+
V+
V+
V–
or NC
IN
NO
COM
TS12A4516
1-MHz
As
Required Analyzer
Capacitance
or
NC
TS12A4517
V+
V+
V–
TS12A4516 , , TS12A4517
SCDS236B – DECEMBER 2006 – REVISED APRIL 2009 .................................................................................................................................................
www.ti.com
Figure 2. Switching Times
Figure 3. OFF Isolation and ON Loss
Figure 4. NO, NC, and COM Capacitance
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Product Folder Link(s): TS12A4516 TS12A4517
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TS12A4516D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4516DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4516DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4516DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4516DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4517D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4517DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4517DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4517DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TS12A4517DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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PACKAGE OPTION ADDENDUM
www.ti.com 21-Apr-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TS12A4516DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TS12A4516DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TS12A4517DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS12A4516DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
TS12A4516DR SOIC D 8 2500 367.0 367.0 35.0
TS12A4517DR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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