AS7C1026C-12JIN - Alliance Memory, Inc.

September 2006

Advance Information

AS7C1026C

5 V 64K X 16 CMOS SRAM

12/5/06, v 1.0 Alliance Memory P. 1 of 9

Features

• Industrial (-40o to 85oC) temperature

• Organization: 65,536 words × 16 bits

• Center power and ground pins for low noise

• High speed

- 12 ns address access time

- 6 ns output enable access time

• Low power consumption via chip deselect

• Easy memory expansion with CE, OE inputs

• TTL-compatible, three-state I/O

• Upper and Lower byte pin

• JEDEC standard packaging

- 44-pin 400 mil SOJ

- 44-pin TSOP 2-400

• ESD protection ≥ 2000 volts

Logic block diagram

65,536 x 16

Array

WE Address decoder

Address decoder

VCC

GND

A10

A11

A12

A13

A14

A15

Control circuit

I/O0–I/O7

I/O8–I/O15

I/O

buffer

Pin arrangement

I/O13

I/O12

GND

VCC

I/O11

I/O10

I/O9

I/O8

A10

A11

I/O0

I/O1

I/O2

I/O3

VCC

GND

I/O4

I/O5

I/O6

I/O7

A15

A14

A13

44-Pin SOJ (400 mil), TSOP 2

A12

I/O15

I/O14

A3 3

A2 4

44 A6

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Functional description

The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized

as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing

are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-

performance applications.

When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is

static, then full standby power is reached (ISB1).

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15

is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should

drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or

write enable is active, output drivers stay in hi gh-impedance mode.

The device provides mul tiple cent er pow er and gr ound pi ns, and separate byte en able co ntro ls, all ow ing ind ivi dual by tes to be

written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1026C is packaged in

common industry standard packages.

Note:

Stresses greater than those listed under Absolute Maximum Rating s may cause permanent damage to the device. This is a stress rating only and functi onal

operation of the devic e at these or any other conditions outside th ose indicated in the operational sections of this sp ecification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Key: H = high, L = low, X = don’t care.

Absolute maximum ratings

Parameter Symbol Min Max Unit

Voltage on VCC relative to GN D Vt1 –0.50 +7.0 V

Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V

Power dissipation PD–1.25W

Storage temperature (plastic) Tstg –55 +125 °C

Ambient temperature with VCC applied Tbias –55 +125 °C

DC current into outputs (low) IOUT –50mA

Truth table

CE WE OE LB UB I/O0–I/O7 I/O8–I/O15 Mode

HXXXXHigh ZHigh Z Standby (I

SB), ISBI)

LHLLHD

OUT High Z Read I/O0–I/O7 (ICC)

LHLHLHigh ZD

OUT Read I/O8–I/O15 (ICC)

LHLLLD

OUT DOUT Read I/O0–I/O15 (ICC)

LLXLL D

IN DIN Write I/O0–I/O15 (ICC)

LLXLHD

IN High Z Write I/O0–I/O7 (ICC)

LLXHLHigh ZD

IN Write I/O8–I/O15 (ICC)

HHigh Z High Z Output disable (ICC)

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Recommended operating conditions

Notes:

VIL min = -1.5V for pulse width less than 5ns, once pe r cyc le.

VIH max = VCC+2.0V for pulse wid th less than 5n s, once per cycle.

Parameter Symbol Min Nominal Max Unit

Supply voltage VCC 4.5 5.0 5.5 V

Input voltage VIH 2.2 – VCC + 0.5 V

VIL –0.5 – 0.8 V

Ambient operating temperature (Industrial) TA–40 – 85 o C

DC operating characteristics (over the operating range)1

Parameter Sym Test conditions

AS7C1026C-12

UnitMin Max

Input leakage current | ILI | VCC = Max,

VIN = GND to VCC –5µA

Output leakage current | ILO | VCC = Max, CE = VIH,

VOUT = GND to VCC –5µA

Operating power supply current ICC

VCC = Max,

CE ≤ VIL, IOUT = 0mA,

f = fMax – 210 mA

Standby power supply current

ISB VCC = Max,

CE ≥ VIH , f = fMax –60mA

ISB1

VCC = Max, CE ≥ VCC–0.2 V,

VIN ≤ 0.2 V or

VIN ≥ VCC–0.2 V, f = 0 –10mA

Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V

VOH IOH = –4 mA, VCC = Min 2.4 – V

Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)2

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN A, CE, WE, OE, LB, UB VIN = 0 V 6 pF

I/O capacitance CI/O I/O VOUT = 0 V 7 pF

Note:

This parameter is guar anteed by device characterization, but is not production tested.

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Key to switching waveforms

Read waveform 1 (address controlled)3,6,7,9

Read waveform 2 (OE, CE, UB, LB controlled)3,6,8,9

Read cycle (over the operating range)3,9

Parameter Symbol

AS7C1026C-12

Unit NotesMin Max

Read cycle time tRC 12 – ns

Address access time tAA –12ns3

Chip enable (CE) access time tACE –12ns3

Output enable (OE) access time tOE –7ns

Output hold from address change tOH 4–ns5

CE low to output in low Z tCLZ 4 – ns 4, 5

CE high to output in high Z tCHZ – 6 ns 4, 5

OE low to output in low Z tOLZ 0 – ns 4, 5

Byte select access time tBA –7ns

Byte select Low to low Z tBLZ 0 – ns 4, 5

Byte select High to high Z tBHZ – 6 ns 4, 5

OE high to output in high Z tOHZ – 6 ns 4, 5

Power up time tPU 0 – ns 4, 5

Power down time tPD –12ns4, 5

Undefined output/do n’t careFalling inputRising input

Data

OUT

Address

Data validPrevious data valid

Data valid

BLZ

OLZ

OHZ

BHZ

ACE

Address

LB, UB

Data

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Write waveform 1 (WE controlled)11

Write cycle (over the operating range) 11

Parameter Symbol

AS7C1026C-12

Unit NotesMin Max

Write cycle time tWC 12 – ns

Chip enable (CE) to write end tCW 9–ns

Address setup to write end tAW 9–ns

Address setup time tAS 0–ns

Write pulse width tWP 9–ns

Write recovery time tWR 0–ns

Address hold from end of write tAH 0–ns

Data valid to write end tDW 7–ns

Data hold tim e tDH 0–ns5

Write enable to output in high Z tWZ – 6 ns 4, 5

Output active from write end tOW 1 – ns 4, 5

Byte select low to end of write tBW 9–ns

Address

LB, UB

Data

OUT

Data undefined high Z

Data valid

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Write waveform 2 (CE controlled)11

AC test conditions

Notes:

1 During VCC power-up, a pul l - u p r esistor to VCC on CE is required to meet ISB specification.

2 This parameter is sampled, but no t 100% te sted.

3 For test conditions, see AC Test Conditions, Figures A and B.

4 These parameters are specified with CL = 5 pF, as in Figures B. Transition is measured ± 200 mV from steady-state voltage.

5 This parameter is guaranteed, but not tested.

6WE

is high for read cycl e.

7CE

and OE are low for read cy cle.

8 Address is valid prior to or coincident with CE transition low.

9 All read cycle timings are referenc ed from the last valid address to the first transitioning addre ss.

10 N/A.

11 All write cycle timings are referenc ed from the last valid addre ss to the first transitioning address.

12 Not applicable.

13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

Address

LB, UB

Data

OUT

Data undefined

high Z high Z

Data valid

CLZ

168

Thevenin Equivalent:

OUT

+1.728 V

255

480

GND

+5 V

Figure B: 5 V Output load

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

3 ns

OUT

– Output load: see Figure B.

– Input pulse level: GND to 3.0 V. See Fig ure A.

– Input rise and fall times: 3 ns. See Figure A.

– Input and output timing reference levels: 1.5

AS7C1026C

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Package dimensions

44-pin TSOP 2

Min

(mm) Max

(mm)

A1.2

A1 0.05 0.15

A2 0.95 1.05

b0.30 0.45

c0.120 0.21

D18.31 18.52

E10.06 10.26

He 11.68 11.94

e0.80 (typical)

l0.40 0.60

1234567891011121314

444342414039 383736 35 3433 32 31

1516

3029

1718 1920

2827 26 25

44-pin TSOP 2

0–5

Seating

plane

44-pin SOJ

400 mil

Min (in) Max (in)

A0.128 0.148

A10.025 –

A20.105 0.115

B0.026 0.032

b0.015 0.020

c0.007 0.013

D1.120 1.130

E0.370 NOM

E10.395 0.405

E20.435 0.445

e0.050 NOM

Pin 1

AA2

AS7C1026C

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Ordering codes

Package Volt/Temp 12 ns

Plastic SOJ, 400 mil 5V Industrial AS7C1026C-12JIN

TSOP 2, 10.2 x 18.4 mm 5V Industrial AS7C1026C-12TIN

Part numbering system

AS7C 1026C –XX X X X

SRAM prefix Device number Access time

Package:

J = SOJ 400 mil

T = TSOP 2, 10.2 x

18.4 mm

Temperature range:

I = industrial: -40° C

to 85° C

N = LEAD FREE

PART

Alliance Memory, Inc.

1116 South Amphlett

San Mateo, CA 94402

Tel: 650-525-3737

Fax: 650-525-0449

www.alliancememory.com

Part Number: AS7C1026C

Document Version: v 1.0

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product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended

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AS7C1026C